TWI335070B - Semiconductor package and the method of making the same - Google Patents

Semiconductor package and the method of making the same Download PDF

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Publication number
TWI335070B
TWI335070B TW096110034A TW96110034A TWI335070B TW I335070 B TWI335070 B TW I335070B TW 096110034 A TW096110034 A TW 096110034A TW 96110034 A TW96110034 A TW 96110034A TW I335070 B TWI335070 B TW I335070B
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Taiwan
Prior art keywords
substrate
conductors
wafer
package structure
solder balls
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TW096110034A
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English (en)
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TW200839970A (en
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Yu Ching Sun
Ren Yi Cheng
Tsai Wan
Chihhung Hsu
Kuang Hsiung Chen
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Advanced Semiconductor Eng
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Priority to TW096110034A priority Critical patent/TWI335070B/zh
Priority to US12/052,815 priority patent/US8143101B2/en
Publication of TW200839970A publication Critical patent/TW200839970A/zh
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

1330070 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種半導體封裝結構及其製造方法，詳言 之，係關於一種可堆疊之半導體封裝結構及其製造方法。 【先前技術】 參考圖1至7,顯示習知堆疊式半導體封裝結構之各個製 程步驟之示意圖。首先，參考圖丨，提供一基板1〇，該基 板10具有一第一表面101及一第二表面丨02。接著，附著一 晶片11至該基板10之第一表面101，且該晶片丨丨係利用複 數條導線12電性連接至該基板10。 參考圖2，覆蓋一模具13於該基板1()之第一表面1〇1。該 模具13具有一模穴131以容納該晶片n及該等導線12 ^ 參考圖3，進行灌模（Molding)製程，注入一封膠材料14 於該模穴131内，以包覆該晶片丨丨及該等導線12。接著， 移除該模具13。 參考圖4 ’進行植球（Ball Mounting)製程，形成複數個第 一銲球15於該基板1〇之第一表面1〇1未被該封膠材料14覆 盖之區域。 參考圖5,提供一上封裝結構16，該上封裝結構16包括 一上基板17、一上晶片18、複數條上導線19、一上封膠材 料20及複數個第三銲球21。該上基板17具有一第一表面 171及一第二表面172。該上晶片18係利用該等上導線19電 性逹接該上基扳17之第一表面171。該等第三銲球21係位 於該上基板17之第二表面172。
Il7576.doc • 6 - 1335070 參考圖6,堆疊該等第三銲球21於該等第一銲球。上， 且進行回銲（Reflow),使得該等第三銲球21及該等第一銲 球15融接以形成複數個第四銲球2 2。 參考圖7，形成複數個第二銲球23於該基板1〇之第二表 面102 ’以形成一堆疊式封裝結構。 該習知堆疊式封裝結構之缺點在於，在上述灌模製程 時，容易產生溢膠，亦即該封膠材料14會溢出該模穴131 外，而進入該模具13與該基板10第一表面1〇1之間。因而 會污染該等第一銲球15之植球區域，而j致植球製程失 气缺陷。此外，該基板10之剛性較差，當該等 第三銲球171及該等第一銲球15融接形成複數個第四銲球 22後，會對該基板10產生應力，該基板1〇會被拉扯而產生 叙曲（Wrapage)缺陷。 因此，有必要提供一種創新且具進步性的半導體封裝結 構及其製造方法’以解決上述問題。 【發明内容】 本發明之主要目的在於提供一種半導體封裝結構之製造 方法，包括以下步驟：⑷提供一基板，該基板具有一第一 表面及一第二表面；（b)附著一晶片至該基板之第一表 且該BB片係電性連接至該基板；（c)形成複數個導體於 該基板之第一表面；⑷覆蓋一模具於該等導體上，該模具 具有複數個缺口，每—缺口係容置每—該等導體之上端； 及⑷形成-封膝材料以包覆該基板之第一表面該晶片及 部分該等導體’其中該封夥材料之厚度係小於每一該等導 117576.doc 1335070 體之高度β 本發明之另一目的在於提供一種半導體封裝結構，包括 基板、一晶片、一上基板、一上晶片、複數個第四銲球 封勝材料。該基板具有一第一表面及一第二表面。該 曰曰片附著至該基板之第一表面，且電性連接至該基板。該 上基板具有一第一表面及一第二表面。該上晶片附著至該 上基板之第一表面，且電性連接至該上基板。該等第四銲 球連接該上基板之第二表面及該基板之第一表面。該封膠 材料，包覆該基板之第一表面、該晶片及部分該等第四銲 球，該封膠材料之厚度係小於每一該等第四銲球之高度。 藉此，在本發明中，由於該封膠材料係包覆該基板第一表 面整個平面，因在不會產生溢膠之問題，而且可提高該奉 性一。 【實施方式】 參考圖8至圖13 ’顯示本發明半導體封裝結構之第一實 施例之各個製程步驟之示意圖。參考圖8,提供一基板 30’該基板30具有一第一表面3〇1及一第二表面3〇2。接 著，附著一晶片31至該基板30之第一表面301，且該晶片 3 1係電性連接至該基板3 〇。在本實施例中，該晶片3〖係利 用複數條導線32電性連接至該基板30。接著，形成複數個 導體33於该基板30之第一表面301。在本實施例中，該等 導體33係為複數個第一銲球，其係為球狀。 參考圖9，覆蓋一模具34於該等導體33上，該模具34具 有複數個缺口 341 ’每一缺口 341係容置每一該等導體33之 117576.doc 1335070 一上基板39、一上晶片40、複數個第三銲球42及一上封膠 材料43。該上基板39具有一第一表面391及一第二表面 392。該上晶片40係電性連接該上基板39之第一表面gw。 在本實施例令，該上晶片4〇係利用複數條上導線41電性連 接至該上基板39之第一表面391。該等第三銲球42係位於 該上基板39之第二表面392。該上封膠材料43係包覆該上 晶片40 '該上基板39之第一表面391及該等上導線41。
參考圖13，堆疊該等第三銲球42於該等導體33上。接 著’進行回銲（Reflow) ’使得該等第三銲球42及該等導體 33融接以形成複數個第四銲球44，且形成一半導體封裝結 構45，該半導體封裝結構45係為一堆疊式半導體封裝結 構。 在本實把例中，係先形成該等第二銲球3 7 (圖1丨），再 進行堆疊及回銲作業（圖12及丨3)。然而可以理解的是， 也可以在未形成該等第二銲球37的情況下，先進行堆疊及
回銲作業，之後再形成該等第二銲球37於該基板之第二 表面302。 片 再參考圖13，該半導體封裝結構45包括一基板3〇、一晶 31、一上基板39' —上晶片4〇、一上封膠材料43、複數 個第四銲球44及一封膠材料35。該基板3〇具有一第一表面 3〇1及一第二表面302。該晶片31係附著至該基板扣之第一 表面301 ’且利用複數條導線32電性連接至該基板。該 上基板39具有一第一表㈣i及一第二表㈣卜該上晶只 ㈣附著至該上基板39之第—表面391，且利用複數條上 II7576.doc 1335070 導線41電性連接至該上基板39。該上封膠材料43係包覆該 上晶片40、該上基板39之第一表面391及該等上導線41。 該等第四銲球44係連接該上基板39之第二表面392及該 基板30之第—表面301。該封膠材料36係包覆該基板3〇之 第一表面301、該晶片31、該等導線32及部分該等第四銲 球44 ,該封膠材料36之厚度係小於每一該等第四銲球払之 南度’亦即該等第四銲球44係暴露於該封膠材料36之外。 較佳地’該半導體封裝結構45更包括複數個第二銲球 37’其係位於該基板3〇之第二表面3〇2。 參考圖14至圖19，顯示本發明半導體封裝結構之第二實 施例之各個製程步驟之示意圖。參考圖14，提供一基板 5〇’該基板50具有一第一表面501及一第二表面5〇2。接 著附著一晶片51至該基板50之第一表面501，且該晶片 5 1係電性連接至該基板5〇。在本實施例中，該晶片5丨係利 用複數條導線52電性連接至該基板50〇接著，形成複數個 導體53於該基板50之第一表面501。在本實施例中，該等 導體5 3係為複數個第—銲球，其係為球狀。 參考圖15，覆蓋一模具54於該等導體53上，該模具54具 有複數個凸出部541，每一凸出部541係接觸每一該等導體 53之上端。 參考圖16’進行灌模製程，形成一封膠材料55以包覆該 基板50之第一表面501、該晶片51、該等導線52及部分該 等導體53，其中該封膠材料55之厚度係大於每一該等導體 53之咼度，且該封膠材料55具有複數個開口 551，以暴露 I17576.doc -11· 1335070 出該等導體53之上端，該等開口 551之形狀係相對應於該 等凸出部541之形狀。當該封膠材料55凝固後，移除該模 具54’即可得一半導體封裝結構56。 再參考圖16 ’該半導體封裝結構56包括一基板50、一晶 片51、複數個導體53及一封膠材料55。該基板50具有一第 一表面501及一第二表面502。該晶片51係附著至該基板5〇 之第一表面501，且電性連接至該基板5〇 »在本實施例
中’該晶片51係利用複數條導線52電性連接至該基板50。 該等導體53係位於該基板5〇之第一表面501。在本實施 例中，該等導體53係為複數個第一銲球。該封膠材料55包 覆该基板50之第一表面5〇1 '該晶片51及部分該等導體 53，該封膠材料55之厚度係大於每一該等導體53之高度， 且該封膠材料55具有複數個開口 551，以暴露出該等導體 53之上端。 該半導體封裝結構56還可以再進行以下製程。
參考圖17，形成複數個第二銲球57於該基板50之第二表 面 502。 該上封裝結構58包括 參考圖18，提供一上封裝結構58» 一上基板59、一上晶片6〇、複數個第三銲球“及一上封膠 材料63 1¾上基板59具有一第一表面59 ^及一第二表面 592。該上晶片60係電性連接該上基板59之第一表面591。 本實知例中’該上晶片60係利用複數條上導線61電性連 接至該上基板59之第—矣品Hr ^ ^ 弟表面591。該等弟三銲球62係位於 該上基板59之第-志^ 第-表面592。該上封勝材料63係包覆該上 117576.doc -12· 1335070 晶片60、該上基板59之第一表面591及該等上導線61。 參考圖19，堆疊該等第三銲球62於該等導體幻上。接 著，進行回銲（Reflow)，使得該等第三銲球62及該等導體 5 3融接以形成複數個第四銲球64，且形成一半導體封.裝结 構65，該半導體封裝結構65係為一堆疊式半導體封裝結 構β 在本實施例中，係先形成該等第二銲球57 (圖丨7 )，再 進行堆疊及回銲作業（圖18及19 )。然而可以理解的是， 也可以在未形成該等第二銲球57的情況下，先進行堆疊及 回銲作業，之後再形成該等第二銲球57於該基板5〇之第二 表面502。 ，再參考圖19,該半導體封裝結構65包括一基板5〇、一晶 片5 1上基板59、一上晶片60、一上封膠材料63、複數 個第四銲球64及一封膠材料55 ^該基板50具有一第一表面 501及一第二表面5〇2。該晶片51係附著至該基板％之第一 表面501 ’且利用複數條導線52電性連接至該基板5〇。該 上基板59具有一第一表面591及一第二表面59ι。該上晶片 60係附著至該上基板59之第一表面591，且利用複數條上 導線61電吐連接至該上基板59。該上封膠材料〇係包覆該 上阳片60該上基板59之第一表面591及該等上導線61。 §第四銲球64係連接該上基板59之第二表面592及該 基㈣之第—表面501。該封膠材⑽係包覆該基板50之 第表面501、該晶片51、該等導線52及部分該等第四銲 球64 ’該封膠材料56之厚㈣小於每—料第四銲球以之 117576.doc -13- 叫〇7〇 门度亦即該等第四銲球μ係暴露於該封膠材料56之外。 較佳地，^ ^ -λ , 々牛導體封裝結構65更包括複數個第二銲球 57’其係、位於該基板50之第二表面502。 准述實化例僅為說明本發明之原理及其功效，而非用 艮制本發明。因此’ f於此技術之人士對上述實施例進 :::及變化仍不脫本發明之精神。本發明之權利範圍應 如後述之申請專利範圍所列。 【圖式簡單說明】 圖⑴顯示習知堆叠式半導體封裝結構之各個 之示意圖； v鄉 圖8至圖13顯示本發明半導體封裝結 各個製程步驟之示意圖;及之第實知例之 圖14至圖19顯示本發明丨導體封|結構之 各個製程步驟之示意圖。 列之 【主要元件符號說明】 10 基板 11 晶片 12 導線 13 模具 14 封膠材料 15 第一銲球 16 上封裝結構 17 上基板 18 上晶片 117576.doc 133-5070
19 上導線 20 上封膠材料 21 第三銲球 22 第四銲球 23 第二鮮球 30 基板 31 晶片 32 導線 33 導體 34 模具 35 封膠材料 36 半導體封裝結構 37 第二銲球 38 上封裝結構 39 上基板 40 上晶片 41 上導線 42 第三銲球 43 上封膠材料 44 第四鲜球 45 半導體封裝結構 50 基板 51 晶只 52 導線 117576.doc -15· 1335070
53 導體 54 模具 55 封膠材料 56 半導體封裝結構 57 第二鮮球 58 上封裝結構 59 上基板 60 上晶片 61 上導線 62 第三銲球 63 上封膠材料 64 第四銲球 65 半導體封裝結構 101 基板第一表面 102 基板第二表面 131 模穴 171 上基板第一表面 172 上基板第二表面 301 基板第一表面 302 基板第二表面 341 缺口 391 上基板第一表面 392 上基板第二表面 501 基板第一表面 117576.doc -16- 1335070
502 基板第二表面 541 凸出部 551 開口 591 上基板第一表面 592 上基板第二表面 117576.doc • 17-

Claims (1)

1335070 竹年7月？日修(更>正本 第〇96110〇34號專利申請案 . 中文申請專利範圍替換本(99年7月） 十、申請專利範圍： 1. 一種半導體封裝結構之製造方法，包括以下步驟： (a)提供一基板，該基板具有一第一表面及一第二表 面； W附著一晶片至該基板之第一表面，且該晶片係電性 連接至該基板； (C)形成複數個導體於該基板之第一表面； (d) 覆蓋一模具於該等導體上，該模具具有複數個缺 口，每一缺口係容置每一該等導體之上端，且該等 導體之上端係與該等缺口之側壁相接觸；及 (e) 形成一封膠材料以包覆該基板之第一表面、該晶片 及部分該等導體，其中該封膠材料之厚度係小於a 一該等導體之高度。 、’ 2.=:们之方法’其中該步驟㈨中該晶片係 條導線電性連接至該基板。 數 3 · 如請求項1 $古.土 、 法，其中該步驟（c)中該等導體係為複| 個第一銲球。 设數 4. 如請求項1 $太.土 # i 狀。、 法，其中該步驟（C)中該等導體係為球 5. 如明求項1之方法，其中該步驟⑷之後更包括： 成複數個第二銲球於該基板之第二表面。 6. 如請求項5夕f .4· ^ 、 方法’其中該步驟（el)之後更包括： (f) k供一上封举έ士 m 一 上对裝結構，該上封裝結構包括一上基板、 上曰曰片及複數個第三銲球，該上基板具有一第一 1335070 第096110034號專利申請案 . 中文申凊專利範圍替換本(99年7月） 表面及一第二夹而，▲*· 。 之m "曰日片係電性連接該上基板 义弟一表面，該等第二钽 鲜球係位於該上基板之第二 衣面； (g) 堆豐該等第三銲球於該等導體上；及 (h) 進行回銲（Reflow)，使得該 ’ 才币一綷垛及該等導體融 接以形成複數個第四銲球。 7. 如請求項6之方法，其十噹+ •隹奴作、. 步驟（f)中上封裝結構更包括 複數條上導線及一上封膠材料，^r耸μ道 • 上導線係電性連接 上美Γ 該上封膠材料係包覆該上晶片、該 土板之第一表面及該等上導線。 8. 如請求項1之方法，其中爷牛 甲及步驟（e)之後更包括： (f) 提供一上封裝結構 °亥上封裝結構包括-上基板、 一上晶片及複數個第三銲 上基板具有一第一 表面及一第二表面，該曰 之笛主 日日片係電性連接該上基板 之第一表面，該等第X：锃扑 鲜球係位於該上基板之第二 衣曲； (g) 堆疊該等第三銲球於該等導體上；及 (h) 進行回銲（Reflow)吏 接；及 更传°玄#第二銲球及該等導體融 (i) 形成複數個第二銲球於該基板之第二表面 9.如請求項8之方法，其中該步驟 一 ^ 。 複數條上導線及一上封牌材 4 $更包括 該上曰片及等上導線係電性連接 -片及上基板’該上封膠材料係 上基板之第-表面及該等上導線。 以上曰曰片、该 • 2 · 1335070 第096110〇34號專利申請案 • 中文申請專利範圍替換本(99年7月） 10. —種半導體封裝結構，包括： 二表面 ； ’且電性連接至該基 一基板，具有一第一表面及—第 晶片，附著至該基板之第—表面 板； 複數個導體，位於該基板之第一表面；及 -封膠材料’係利用一模具進行灌模製 具具有複數個缺口，每一> 成4杈 山 母轵口係各置母一該等導體之上
端’且該等導體之上端係與該等缺口之側壁相接觸，泫 封膠材料包覆該基板之第—表面、該晶片及部分該等導 體，該封膠材料之厚度係小於每一該等導體之高度。 1 1 .如β求項1 〇之半導體封裝結構，更包括複數條導線，該 等導線係電性連接該晶片及該基板。 ° 1 2.如。月求項1G之半導體封裝結構其中該等導體係為複數 個第一 _球。 U.如請求項10之半導體封裝結構，纟中該等導體係為球 狀。 14.如明求項10之半導體封裝結構更包括複數個第二銲 球，位於該基板之第二表面。 15· —種半導體封裝結構，包括： 基板’具有一第一表面及一第二表面； 片附者至遠基板之第一表面’且電性連接至該 基板； 複數個導體，位於該基板之第一表面； 一上基板’具有—第一表面及一第二表面； 第096110034號專利申請案 中文申請專利範圍替換本(99年7月） 上曰曰片，附著至該上基板之第一表面且電性連接 至該上基板； 複數個第三銲球，位於該上基板之第二表面； 複數個第四録球’係由堆疊該等導體及該等第三桿球 再回鲜而成，料第四銲球連接該上基板之第二表面及 该基板之第一表面；及 -封膠材料，係利用一模具進行灌模製程而成，該模 具具有複數個缺口，各— 母缺口係容置每一該等導體之上 k ’且έ亥等導體之上端係盘 乐玄等缺口之側壁相接觸， 封膠材料包覆該基板之第一 ^ 表面、該晶片及部分該等第 四銲球，該封膠材料之厘序 古办 +之厗度係小於每一該等第四銲球之 南度。 ’如。月求項1 5之半導體封裝έ士槿，由— 冓更包括複數條導線，該 專導線係電性連接該晶片及該基板。 如請求項15之半導體封 娜更包括複數個第二銲 球，位於該基板之第二表面。 18.如請求項15之半導體封裝結構， -上封膠材料，該等上導 G⑯’、上導線及 …… 電性連接該上晶片及上基 面及該等上導線。 山曰片、該上基板之第-表 A一種半導體封裂結構之製造方法，包括以下步驟： (a) 提供一基板，該基板具 面· 第一表面及一第二表 (b) 附著一晶片至該基板 表面，且該晶片係電性 1335070 第096110034號專利申請案 • 中文申請專利範圍替換本("年7月） 連接至該基板； (0形成複數個導體於該基板之第—表 (d) 覆蓋一模具於該等導體上哕 Φ， Α Λ無具具有複數個凸出 4，母一凸出部係接觸每_ 上 Α寻導體之上端；及 (e) 形成一封膠材料以包覆該 伙^^弟一矣面、贫a μ 及部分該等導體，其中 。日日片 ^古 封勝材料之厚度係大於每 一该荨導體之高度，且令封 -封膠材料具有複數個開 Φ 口，以暴露出該等導體之上端。 20. 如請求項19之方法，其中該步驟 中該日曰片係利用複數 條導線電性連接至該基板。 21. 如請求項19之方法，其中嗜牛 干°玄步驟（c)中該等導體係為複數 個第一銲球。 巧吸歎 22. 如請求項19之方法，其中 甲°亥步驟（c)中該等導體係為球 狀。 23. 如請求項19之方法，其中該步驟⑷之後更包括： • (el)形成複數個第二銲球於該基板之第二表面。 24. 如請求項23之方法，其中該步驟⑼之後更包括： ⑴提供-上封裝結構，該上封裝結構包括―上基板、 一上晶片及複數個第三銲球，該上基板具有—第一 表面及一第二表面，該上晶片係電性連接該上基板 之第一表面，該等第三銲球係位於該上基板之第二 表面； (g) 堆疊該等第三鋅球於該等導體上；及 (h) 進仃回銲（Refl〇w)，使得該等第三銲球及該等導體融 1335070 第096110034號專利申請案 . 中文申請專利範圍替換本(99年7月） 接以形成複數個第四銲球。 25. 如請求項24之方法，其中該步驟⑴中上封裝結構更包括 複數條上導線及一上封膠材料’該等上導線係電性連接 該上晶片及上基板，該上封膠材料係包覆該上晶片該 上基板之第一表面及該等上導線。 26. 如請求項19之方法，其中該步驟（e)之後更包括： ⑴提供—上封裝結構，該上封裝結構包括—上基板、 • 一上晶片及複數個第三銲球，該上基板具有一第一 表面及一第二表面’該上晶片係電性連接該上基板 之第-表面，該等第三銲球係位於該上基板之第二 表面； (g)堆疊該等第三銲球於該等導體上；及 融 ⑻進行回銲（Reflow)，使得該等第三鲜球及該等導體 接；及 (1)形成複數個第二銲球於該基板之第二表面。
27. 如請求項26之方法，1中訪牛趣丄 ，、中°亥步驟（f)中上封裝結構更包括 複數條上導線及-上封膠材料，料上導線係電性連接 该上晶片及上基板，該上封膠材料係包覆該上晶片該 上基板之第一表面及該等上導線。 28. —種半導體封裝結構，包括： 第一表面； 表面’且電性連接至該 一基板，具有一第一表面及一 一晶片’附著至該基板之第一 基板； 面；及 複數個導體，位於該基板之第—表 第096110034號專利申請案 中文申請專利範圍替換本(99年7月） 一封膠材料，係利用一楛 換八進仃灌模製程而成，該模 具具有複數個凸出部’每_凸出部係、接觸每—該等導體 之上端’該封膠材料包覆該基板之第—表面、該晶 部分該料體，該封膠㈣之厚度係大於每—該等導體 ::度’且該封膠材料具有複數個開口，以暴露出該等 導體之上端。 29.如請求項28之半導體 笪道妗更包括複數條導線，該 專導線係電性連接該晶片及該基板。 3〇·如請求項28之半導體封裝結構， 個第一銲球。 、中該專導體係為稷數 31.如請求項28之半導體封裝好 狀。 、，，°構其中該等導體係為球 更包括複數個第二鮮 第二表面； 表面，且電性連接至該 32. 如請求項28之半導體封裝結構 球，位於該基板之第二表面。 33. —種半導體封裝結構，包括： 一基板，具有—第一表面及一 一晶片’附著至該基板之第— 基板； 衣曲 後数個導體，位於該基板之第 一上基板，具有-第-表面及-第二表面; - 1_ α . < 複數個第三銲球 複數個第四銲球 位於該上基板之第二表面； 係由堆疊該等導體及該等第 三銲球 第096110034號專利申請索 中文申請專利範圍替換本(99年7月) 再回銲而成，該等第四銲球連接該 該基板之第一表面；及 且：：膠广係利用-模具進行灌模製程而成，該模 稷個凸出部，每一凸出部係接觸每_該等導體 該封膠材料包覆該基板之第-表面、該晶，及 等第四銲球，該封膠材料之厚度係小於每一該等 第四銲球之高度。
上基板之第二表面及 ^ ^ € Μ之半導體封裝結構更包括複數條導線，該 專導線係電性連接該晶片及該基板。 35.如請求項33之半導體封裝結構1包括複數個第二銲 球’位於該基板之第二表面。 一月长項33之半導體封裝結構’更包括複數條上導線及 上封膠材料，該等上導線係電性連接該上晶片及上基 板’該上封膠材料係包覆該上晶片、該上基板之第一表 面及該等上導線。
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