TWI261877B - Method for fabricating semiconductor device with recessed channel region - Google Patents

Method for fabricating semiconductor device with recessed channel region Download PDF

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Publication number
TWI261877B
TWI261877B TW093139636A TW93139636A TWI261877B TW I261877 B TWI261877 B TW I261877B TW 093139636 A TW093139636 A TW 093139636A TW 93139636 A TW93139636 A TW 93139636A TW I261877 B TWI261877 B TW I261877B
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Taiwan
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hard mask
layer
forming
substrate
oxide layer
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TW093139636A
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English (en)
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TW200537609A (en
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Soo-Young Park
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Hynix Semiconductor Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H01L21/823425—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
    • E—FIXED CONSTRUCTIONS
    • E03—WATER SUPPLY; SEWERAGE
    • E03C—DOMESTIC PLUMBING INSTALLATIONS FOR FRESH WATER OR WASTE WATER; SINKS
    • E03C1/00—Domestic plumbing installations for fresh water or waste water; Sinks
    • E03C1/12—Plumbing installations for waste water; Basins or fountains connected thereto; Sinks
    • E03C1/22—Outlet devices mounted in basins, baths, or sinks
    • E03C1/23—Outlet devices mounted in basins, baths, or sinks with mechanical closure mechanisms
    • E03C1/2302—Outlet devices mounted in basins, baths, or sinks with mechanical closure mechanisms the actuation force being transmitted to the plug via rigid elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Water Supply & Treatment (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Public Health (AREA)
  • Health & Medical Sciences (AREA)
  • Environmental & Geological Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Hydrology & Water Resources (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Element Separation (AREA)
  • Semiconductor Memories (AREA)

Description

1261877 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種製造半導體元件的方法；尤其是關 於一種使用凹槽通道陣列電晶體（RC AT)技術’製造半導體 的方法。 【先前技術】 由於半導體元件積體性和微小化的程度增加，所以要 求的製程能力和可靠度也增加。尤其，在動態隨機存取記 憶體（DRAM)的情形下，電晶體之特性幾乎是由淺溝隔離 (S TI )製程和形成閘極結構之製程決定。此電晶體之特性是 決定DRAM整體的穩定性最重要的因素。因此，應該要確 實改善STI製程和形成閘極結構之製程的穩定性，以增加 DRAM整體的可靠度。 S TI製程係半導體元件的元件隔離方法的其中之一。 換言之，先在矽基板上形成溝渠，然後再用絕緣材料，如 氧化矽層，塡滿溝渠內部。結果，即使在相同的隔離寬度 下，也可以延伸有效的隔離長度。因此，相較於藉由矽局 部氧化（LOCOS)製程之元件隔離，STI製程係一種可以得到 較小隔離區域之技術。 最近，有一'種凹槽通道陣列電晶體（R C A T)的技術被提 出，其可以改善在製造DRAM期間之再新特性。 第1A圖到第1C圖爲藉由使用RC AT技術製造半導體 元件之傳統方法的橫截面圖。 參照第1 A圖，許多具有S TI結構之元件隔離層1 2被 1261877 形成在基板1 1之上。之後’硬式遮罩氧化物層13和硬式 遮罩多晶砂層14 ’依序沉積在基板11的上部分之上。在 此，硬式遮罩氧化物層1 3和硬式遮罩多晶矽層1 4，係被 用以當作形成許多凹槽通道區域之硬式遮罩。 其次，將感光層沉積在硬式遮罩多晶矽層14之上，然 後藉由透過曝光和顯影製程，將感光層製作成圖案，形成 用以形成凹槽通道之遮罩1 5。 接著，藉由使用遮罩1 5當作蝕刻屏障，触刻硬式遮罩 多晶矽層1 4和硬式遮罩氧化物層1 3，因此曝露出在基板 1 1預定區域之許多凹槽通道區域。 參照第1 B圖，蝕刻預定厚度在預定區域之許多曝露的 凹槽通道區域，於是形成許多溝渠1 6。在形成許多溝渠1 6 時，遮罩1 5全部都用完，而剩下硬式遮罩氧化物層1 3和 硬式遮罩多晶矽層1 4。 參照第1 C圖，透過濕式蝕刻製程，移除硬式遮罩氧化 物層1 3和硬式遮罩多晶矽層1 4。 其次，以圍繞許多溝渠1 6的方式，形成許多閘極氧化 物層1 7。之後，沉積許多導電層在許多閘極氧化物層i 7 上，以塡滿許多溝渠1 6。接著，選擇性製作用於許多閘極 結構和許多閘極氧化物層1 7之導電層的圖案，於是形成許 多閘極結構1 8。此時，許多閘極結構1 8的每一個，都包 含埋在溝渠當中的下區域和突出超過基板1 1之上部分的 上區域。因此，藉由閘極結構的下區域，可以形成許多凹 槽通道區域。 1261877 其次，藉由執行離子佈値，在基板11上形成許多源極 /汲極區1 9。 但是，當移除用以形成許多溝渠1 6，其係用以形成凹 槽通道區域，之硬式遮罩，即硬式遮罩氧化物層1 3和硬式 遮罩多晶矽層1 4時，根據傳統方法，會在許多元件隔離層 1 2的許多上轉角邊緣產生許多濠溝Μ。 第2Α圖爲根據傳統方法，產生許多濠溝Μ的橫截面 圖，而第2 Β圖爲根據傳統方法，用以形成許多閘極結構之 剩餘層的橫截面圖。 參照第2 Α圖，在移除硬式遮罩氧化物層1 3之後’在 元件隔離層的許多上轉角邊緣處，有產生許多其表面'變$ 低於活性區表面之濛溝Μ。
當透過濕式蝕刻製程移除硬式遮覃氧化物層1 3日# S 於許多其爲氧化物層之元件隔離層1 2也會被濕式餓刻’所 以產生這些許多濠溝Μ。此外，在形成許多閘極氧化物層 之前，在執行淸洗製程時，會有因額外的濕式餽刻而丨吏許 多濠溝Μ的深度更深之問題。 參照第2 Β圖’當藉由蝕刻用以形成許多閘極結構之導 電層，形成許多_極結構時，要触刻掉存在許多濠溝Μ當 中的導電層1 8 Α就會變得恨困難。在此，若用以形成許多 閘極結構的導電層1 8 A殘留在許多濠溝μ之中時，在導電 圖案之間就會發生短路。 【發明內容】 因此，本發明之目的係要提供一種製造具有許多凹槽 -7- 1261877 通道區域之半導體元件的方法，其在凹槽通道陣列電晶體 (R C A T)製程期間，當移除硬式遮罩氧化物層時，能夠極小 化所產生之濠溝的深度。 根據本發明之一方向，本發明提供一種製造具有許多 凹槽通道區域之半導體元件的方法，其包含下列步驟：在 基板中形成許多元件隔離層；在元件隔離層和基板上，形 成硬式遮罩氮化物層、硬式遮罩氧化物層和硬式遮罩多晶 矽層，於是可以得到硬式遮罩圖案；藉由使用硬式遮罩圖 案以曝露許多凹槽通道區域，而在基板的預定區域形成許 多溝渠；選擇性移除硬式遮罩圖案；及在許多溝渠中，形 成許多閘極結構。 【實施方式】 下面將參考附圖，詳細說明根據本發明之較佳實施例 ，製造具有許多凹槽通道區域之半導體元件的方法。 第3A圖到第3E圖爲藉由使用根據本發明之凹槽通道 陣列電晶體（RCAT)技術，形成半導體元件之方法的橫截面 圖。 參照第3 A圖，先在基板2 1上形成用於許多溝渠2 2 之許多元件隔離層，然後在基板2 1上形成硬式遮罩氮化物 層23。 此時，形成之硬式遮罩氮化物層2 3係厚度範圍約爲 50A到2 00A之氮化矽（Si3N4)。 其次，在硬式遮罩氮化物層23上，依序沉積硬式遮罩 氧化物層2 4和硬式遮罩多晶矽層2 5。此處，硬式遮罩氧 1261877 化物層24係由二氧化矽（Si〇2)製成，而硬式遮罩氧化物層 24的厚度範圍約爲50 A到20 0A。硬式遮罩多晶矽層25係 使用製造半導體之典型製程形成之多晶矽層製成，而硬式 遮罩多晶矽層2 5較佳之厚度範圍約爲5 〇 〇 A到2，0 0 〇 A。 如上所述’用以形成根據本發明之凹槽通道區域的硬 式遮罩之結構，係藉由堆疊硬式遮罩氮化物層23、硬式遮 罩氧化物層2 4和硬式遮罩多晶矽層2 5所形成之三重層結 構。此處，硬式遮罩氮化物層2 3除了扮演用以形成凹槽通 道區域之硬式遮罩的角色之外，還用以當作鈾刻硬式遮罩 氧化物層24時的蝕刻停止層。 其次，在硬式遮罩多晶矽層25上形成感光層。然後， 透過曝光和顯影製程，將感光層製作成圖案，於是可以得 到遮罩2 6。 接著，藉由使用遮罩26當作蝕刻屏障，依序蝕刻硬式 遮罩多晶矽層25、硬式遮罩氧化物層24和硬式遮罩氮化 物層23，於是曝露出在基板21中之許多凹槽通道區域。 對於另外一種方式，藉由使用遮罩2 6當作蝕刻屏障， 先蝕刻硬式遮罩多晶矽層2 5。之後，移除遮罩2 6，然後， 藉由使用硬式遮罩多晶矽層2 5當作蝕刻屏障，蝕刻硬式遮 罩氧化物層24和硬式遮罩氮化物層23。 參照第3 B圖，藉由蝕刻預定厚度之許多曝露的凹槽通 道區域，形成許多溝渠2 7。在形成許多溝渠2 7期間，硬 式遮罩多晶矽層2 5和遮罩2 6可以全部都用完，而剩下硬 式遮罩氮化物層23和硬式遮罩興化物層24。 1261877 參照第3 C圖，藉由使用硬式遮罩氮化物層2 3當作蝕 刻停止層，濕式蝕刻蝕刻硬式遮罩氧化物層2 4。此時，採 用氫氟酸（HF)溶液濕式蝕刻硬式遮罩氧化物層24。HF溶液 具有不會蝕刻氮化物層之特性，所以硬式遮罩氮化物層23 可足以扮演蝕刻停止層之角色。 參照第3 D圖，濕式蝕刻硬式遮罩氮化物層23。此時 ，硬式遮罩氮化物層23係藉由使用磷酸（H3 P04)溶液作濕 式蝕刻。但是，因爲其爲氧化物層之許多元件隔離層22， 對H3P〇4溶液不具有選擇比率，所以許多元件隔離層22不 會被蝕刻。 另一方面，除了濕式蝕刻製程之外，硬式遮罩氮化物 層2 3也可以使用選擇性乾式蝕刻製程移除。此時，選擇性 乾式蝕刻製程係使用氯氣。 參照第3 E圖，以圍繞許多溝渠2 7的方式，形成許多 閘極氧化物層28。之後，沉積用於許多閘極結構之導電層 ’直到塡滿在許多閘極氧化物層28上之許多溝渠27。 其次，選擇性製作用於許多閘極結構之導電層和許多 閘極氧化物層2 8的圖案，於是形成許多閘極結構2 9。此 時’每一個閘極結構2 9都包含埋在溝渠當中之下區域和突 出超過基板2 1之上區域。因此，藉由閘極結構的下區域， 可以形成許多凹槽通道區域。 其次，藉由執行離子佈値，在基板2 1上形成許多源極 /汲極區3 0。 根據本發明之實施例，當硬式遮罩氧化物層24被濕式 -10- 1261877 蝕刻時，因爲硬式遮罩氮化物層2 3扮演蝕刻停止層的角色 ，所以可以防止許多元件隔離層2 2被蝕刻。因此，在許多 元件隔離層2 2的上轉角邊緣處不會產生許多溝渠。 藉由使用可以防止在許多元件隔離層的上轉角邊緣產 生濠溝之硬式遮罩氮化物層，本發明有助於對許多閘極結 構容易執行蝕刻製程而不會有任何殘留層，於是可以有效 改善元件特性。 本申請書包含2004年5月6日向韓國專利局申請之韓 國專利公報第KR2004-003 1 93 8號的相關內容，此處將所有 的內容都納入參考。 本發明已對特定實施例詳細說明，那些熟悉本項技術 人士所做之各種不同的變化例和修正例，明顯將不脫離本 發明在後面之申請專利範圍所界定的精神和範圍。 【圖式簡單說明】 根據下面參考相關附圖之較佳實施例的說明，本發明 上述的和其他的目的與特徵將會變得更清楚，其中： 第1 A圖到第1 C圖爲藉由使用凹槽通道陣列電晶體 (RC AT)技術製造半導體元件之傳統方法的橫截面圖； 第2A圖爲根據傳統方法，產生許多濠溝Μ的橫截面 圖； 第2 Β圖爲根據傳統方法，用以形成許多閘極結構之剩 餘層的橫截面圖；及 第3 Α圖到第3Ε圖爲藉由使用根據本發明之RC AT技 術’形成半導體元件之方法的橫截面圖。 -11- 1261877 【主要元件 11 12 13 14 15 16 17 18 19 2 1 22 23 24 25 26 27 28 29 30 符號說明】 基板 元件隔離層 硬式遮罩氧化物層 硬式遮罩多晶矽層 遮罩 溝渠 閘極氧化物層 閘極結構 源極/汲極區 基板 溝渠 硬式遮罩氮化物層 硬式遮罩氧化物層 硬式遮罩多晶矽層 遮罩 溝渠 閘極氧化物層 閘極結構 源極/汲極區
Μ 濠溝

Claims (1)

1261877 十、申請專利範圍： 1. 一種製造具有複數個凹槽通道區域之半導體元件的方法 ，包含下列步驟： 在基板中形成許多元件隔離層； 在元件隔離層和基板上，形成硬式遮罩氮化物層、 硬式遮罩氧化物層和硬式遮罩多晶矽層，於是可以得到 硬式遮罩圖案； 藉由使用硬式遮罩圖案以曝露許多凹槽通道區域， 而在基板的預定區域形成許多溝渠，以曝露許多凹槽通 道區域； 選擇性移除硬式遮罩圖案；及 在許多溝渠中，形成許多閘極結構。 2 ·如申請專利範圍第1項之方法，其中藉由使用硬式遮罩 氮化物層當作蝕刻停止層來選擇性蝕刻硬式遮罩氧化物 層’以移除硬式遮罩圖案；然後選擇性飩刻硬式遮罩氮 化物層。 3 .如申請專利範圍第2項之方法，其中藉由濕式蝕刻製程 來移除硬式遮罩氧化物層。 4 ·如申請專利範圍第3項之方法，其中用以移除硬式遮罩 氧化物層之濕式蝕刻製程係使用HF溶液執行。 5 ·如申請專利範圍第2項之方法，其中硬式遮罩氮化物層 係藉由濕式餽刻製程和乾式蝕刻製程其中之一移除。 6 .如申請專利範圍第5項之方法，其中用以移除硬式遮罩 氮化物層之濕式蝕刻製程係使用H3 P 04溶液執行。 -13- 1261877 7 .如申請專利範圍第1項之方法，其中硬式遮罩氮化物層 形成之厚度範圍係爲由約5 0 A到約2 0 0 A。 8 如申請專利範圍第1項之方法，其中硬式遮罩氧化物層 形成之厚度範圍係約爲5 Ο A到2 Ο Ο A。 9 .如申請專利範圍第1項之方法，其中在形成閘極結構圖 案的步驟之前，還有包含在溝渠上形成閘極氧化物層之 步驟。
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