JP4600834B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP4600834B2 JP4600834B2 JP2006192456A JP2006192456A JP4600834B2 JP 4600834 B2 JP4600834 B2 JP 4600834B2 JP 2006192456 A JP2006192456 A JP 2006192456A JP 2006192456 A JP2006192456 A JP 2006192456A JP 4600834 B2 JP4600834 B2 JP 4600834B2
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- gate trench
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- region
- oxide film
- silicon nitride
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- 239000004065 semiconductor Substances 0.000 title claims description 79
- 238000004519 manufacturing process Methods 0.000 title claims description 37
- 239000010408 film Substances 0.000 claims description 192
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 57
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 57
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 54
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 54
- 239000000758 substrate Substances 0.000 claims description 41
- 238000000034 method Methods 0.000 claims description 32
- 238000001312 dry etching Methods 0.000 claims description 17
- 238000001039 wet etching Methods 0.000 claims description 10
- 230000006870 function Effects 0.000 claims description 7
- 239000010409 thin film Substances 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims 1
- 238000009413 insulation Methods 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 description 13
- 238000005530 etching Methods 0.000 description 11
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/056—Making the transistor the transistor being a FinFET
Description
10t STI用トレンチ
11 活性領域
11s 活性領域の側面
12 ゲートトレンチ
12s ゲートトレンチの側面
13c チャネル領域
14 ソース領域
15 ドレイン領域
16 ゲート絶縁膜
17 厚い絶縁膜
18 ゲート電極
101 パッド酸化膜
102 シリコン窒化膜
104 シリコン酸化膜
104s シリコン酸化膜の肩状部分
105 シリコン窒化膜
106 シリコン酸化膜
108 犠牲酸化膜
109 シリコン酸化膜
110 DOPOS膜
111 W/WN膜
112 シリコン窒化膜
113 サイドウォール絶縁膜
115 コンタクトプラグ
200 STI領域
201 活性領域
200s STI領域の肩状部分
202 ゲートトレンチ
203 ゲート絶縁膜
204 厚い絶縁膜
205 ゲート電極
206 半導体基板
206c チャネル領域
207 パッド酸化膜
208 シリコン窒化膜
209 ゲートトレンチ
Claims (8)
- 半導体基板にSTI(Shallow Trench Isolation)領域及び前記STI領域に囲まれた横長状の活性領域を形成する工程であって、前記活性領域の長手方向を横切る方向において、前記STI領域を形成する第1のシリコン酸化膜の上端部が前記活性領域の上端部上に乗り上げるように且つ前記半導体基板表面に対し略垂直な肩状部分を持つように前記第1のシリコン酸化膜を形成する第1の工程と、
前記肩状部分を含む全面に第1のシリコン窒化膜及び第2のシリコン酸化膜をこの順で形成する第2の工程と、
前記第2のシリコン酸化膜上にゲートトレンチ形成時にハードマスクとなる第2のシリコン窒化膜を形成する第3の工程と、
前記第2のシリコン酸化膜をストッパとしてドライエッチングを行い前記第2のシリコン窒化膜に前記ゲートトレンチの幅に対応する開口を形成する第4の工程と、
前記開口下に露出した前記第2のシリコン酸化膜および前記第1のシリコン窒化膜をウェットエッチング法により順次除去する第5の工程と、
前記活性領域の長手方向と略平行な方向においては、前記第2のシリコン窒化膜をマスクとして、前記第2のシリコン窒化膜及び前記第1のシリコン酸化膜の両方に対して高い選択比を有するドライエッチング法により前記半導体基板にゲートトレンチを形成し、前記ゲートトレンチが延在する前記活性領域の長手方向と略垂直な方向においては、前記STI領域の前記肩状部分をマスクとして前記ゲートトレンチを形成するとともに、前記ゲートトレンチと前記STI領域との間に半導体基板の一部を薄膜状に残存させる第6の工程と
を含むことを特徴とする半導体装置の製造方法。 - 前記半導体基板の前記一部は、前記ゲートトレンチ側に前記半導体基板に対して略垂直な面を備えることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第6の工程に続いて、前記ゲートトレンチの底部に厚い絶縁膜を形成する第7の工程と、前記ゲートトレンチの側面にゲート絶縁膜を形成する第8の工程とを更に備えることを特徴とする請求項1又は2に記載の半導体装置の製造方法。
- 前記第7の工程は、HDP(High Density Plasma)−CVDにより少なくとも前記ゲートトレンチの前記側面及び前記底部に絶縁膜を堆積するステップと、ウェットエッチングにより前記ゲートトレンチの前記側面上に形成された絶縁膜を除去するステップとを含むことを特徴とする請求項3に記載の半導体装置の製造方法。
- 前記ゲートトレンチ底部の前記厚い絶縁膜の下はチャネル領域とならないことを特徴とする請求項3又は4に記載の半導体装置の製造方法。
- 前記第1の工程終了段階で、前記活性領域の上面の内、前記上端部以外の領域はパッド酸化膜で覆われていることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第5の工程の後、前記第6の工程の前に、前記パッド酸化膜をドライエッチング法により除去する工程を有することを特徴とする請求項6に記載の半導体装置の製造方法。
- 前記第8の工程の後、前記半導体基板の前記一部がチャネル領域として機能するように、前記活性領域内の長手方向で、前記ゲートトレンチを挟んで両側に位置する部分にソース領域及びドレイン領域を形成する第9の工程をさらに有することを特徴とする請求項3に記載の半導体装置の製造方法。
Priority Applications (2)
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JP2006192456A JP4600834B2 (ja) | 2006-07-13 | 2006-07-13 | 半導体装置の製造方法 |
US11/822,458 US7816208B2 (en) | 2006-07-13 | 2007-07-06 | Method of manufacturing semiconductor device having trench-gate transistor |
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JP2006192456A JP4600834B2 (ja) | 2006-07-13 | 2006-07-13 | 半導体装置の製造方法 |
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JP2008021828A JP2008021828A (ja) | 2008-01-31 |
JP4600834B2 true JP4600834B2 (ja) | 2010-12-22 |
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Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
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US8866254B2 (en) * | 2008-02-19 | 2014-10-21 | Micron Technology, Inc. | Devices including fin transistors robust to gate shorts and methods of making the same |
JP2011054629A (ja) | 2009-08-31 | 2011-03-17 | Elpida Memory Inc | 半導体装置及びその製造方法 |
CN102969280A (zh) * | 2012-11-30 | 2013-03-13 | 上海宏力半导体制造有限公司 | 提高半导体器件可微缩性的方法 |
KR102072410B1 (ko) | 2013-08-07 | 2020-02-03 | 삼성전자 주식회사 | 반도체 장치 및 그 제조 방법 |
CN107958871B (zh) * | 2016-10-17 | 2020-10-30 | 中芯国际集成电路制造(上海)有限公司 | 半导体装置及其制造方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0281472A (ja) * | 1988-09-16 | 1990-03-22 | Hitachi Ltd | 半導体記憶装置及びその製造方法 |
JPH06268174A (ja) * | 1993-03-15 | 1994-09-22 | Toshiba Corp | 半導体装置 |
JP2001210801A (ja) * | 2000-01-25 | 2001-08-03 | Hitachi Ltd | 半導体集積回路装置の製造方法および半導体集積回路装置 |
JP2005039270A (ja) * | 2003-07-14 | 2005-02-10 | Samsung Electronics Co Ltd | メモリ素子およびその製造方法 |
JP2005322880A (ja) * | 2004-05-06 | 2005-11-17 | Hynix Semiconductor Inc | リセスチャネル領域を備えた半導体素子の製造方法 |
JP2006295180A (ja) * | 2005-04-09 | 2006-10-26 | Samsung Electronics Co Ltd | 垂直方向のゲート電極を有する電界効果トランジスタ及びその製造方法 |
Family Cites Families (3)
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JPH08274277A (ja) | 1995-03-31 | 1996-10-18 | Toyota Central Res & Dev Lab Inc | 半導体記憶装置およびその製造方法 |
US7285466B2 (en) * | 2003-08-05 | 2007-10-23 | Samsung Electronics Co., Ltd. | Methods of forming metal oxide semiconductor (MOS) transistors having three dimensional channels |
US20060192249A1 (en) | 2004-09-20 | 2006-08-31 | Samsung Electronics Co., Ltd. | Field effect transistors with vertically oriented gate electrodes and methods for fabricating the same |
-
2006
- 2006-07-13 JP JP2006192456A patent/JP4600834B2/ja active Active
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- 2007-07-06 US US11/822,458 patent/US7816208B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0281472A (ja) * | 1988-09-16 | 1990-03-22 | Hitachi Ltd | 半導体記憶装置及びその製造方法 |
JPH06268174A (ja) * | 1993-03-15 | 1994-09-22 | Toshiba Corp | 半導体装置 |
JP2001210801A (ja) * | 2000-01-25 | 2001-08-03 | Hitachi Ltd | 半導体集積回路装置の製造方法および半導体集積回路装置 |
JP2005039270A (ja) * | 2003-07-14 | 2005-02-10 | Samsung Electronics Co Ltd | メモリ素子およびその製造方法 |
JP2005322880A (ja) * | 2004-05-06 | 2005-11-17 | Hynix Semiconductor Inc | リセスチャネル領域を備えた半導体素子の製造方法 |
JP2006295180A (ja) * | 2005-04-09 | 2006-10-26 | Samsung Electronics Co Ltd | 垂直方向のゲート電極を有する電界効果トランジスタ及びその製造方法 |
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US7816208B2 (en) | 2010-10-19 |
US20080012053A1 (en) | 2008-01-17 |
JP2008021828A (ja) | 2008-01-31 |
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