JP2008021828A - 半導体装置の製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 89
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 41
- 239000010408 film Substances 0.000 claims abstract description 204
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 56
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 56
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 51
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 47
- 239000010409 thin film Substances 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 29
- 238000001312 dry etching Methods 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 12
- 238000001039 wet etching Methods 0.000 claims description 9
- 230000006870 function Effects 0.000 claims description 7
- 230000001681 protective effect Effects 0.000 claims description 5
- 238000002955 isolation Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims 2
- 238000000151 deposition Methods 0.000 claims 1
- 238000009413 insulation Methods 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- 230000015572 biosynthetic process Effects 0.000 description 13
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
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- 238000009792 diffusion process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
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- 229910052751 metal Inorganic materials 0.000 description 1
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- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/056—Making the transistor the transistor being a FinFET
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- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Semiconductor Memories (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
【解決手段】ゲートトレンチの延在方向と水平な断面A−A'において、STI領域104の上端部を半導体基板13の上に乗り上げさせ且つその乗り上げた部分の端部を半導体基板13に対して垂直となるように形成し、全面にシリコン窒化膜105及びシリコン酸化膜106を積層する。シリコン酸化膜106上にシリコン窒化膜107を形成し、シリコン窒化膜107をマスク形状にパターニングするドライエッチングの際、STI領域104の上端部はシリコン酸化膜106及びシリコン窒化膜105により保護される。STI領域104の上端部がマスクとなり、ゲートトレンチとSTI領域104との間にゲートトレンチ側に基板と略垂直な面を持つチャネル領域が形成される。
【選択図】図10
Description
10t STI用トレンチ
11 活性領域
11s 活性領域の側面
12 ゲートトレンチ
12s ゲートトレンチの側面
13c チャネル領域
14 ソース領域
15 ドレイン領域
16 ゲート絶縁膜
17 厚い絶縁膜
18 ゲート電極
101 パッド酸化膜
102 シリコン窒化膜
104 シリコン酸化膜
104s シリコン酸化膜の肩状部分
105 シリコン窒化膜
106 シリコン酸化膜
108 犠牲酸化膜
109 シリコン酸化膜
110 DOPOS膜
111 W/WN膜
112 シリコン窒化膜
113 サイドウォール絶縁膜
115 コンタクトプラグ
200 STI領域
201 活性領域
200s STI領域の肩状部分
202 ゲートトレンチ
203 ゲート絶縁膜
204 厚い絶縁膜
205 ゲート電極
206 半導体基板
206c チャネル領域
207 パッド酸化膜
208 シリコン窒化膜
209 ゲートトレンチ
Claims (11)
- 半導体基板にSTI(Shallow Trench Isolation)領域及び前記STI領域に囲まれた活性領域を形成する工程であって、前記活性領域を横切る方向において、前記STI領域を形成する第1の絶縁膜の上端部が前記活性領域の上端部上に乗り上げるように且つ前記半導体基板に対し略垂直な肩状部分を持つように形成する第1の工程と、
前記肩状部分を含む全面に第2の絶縁膜及び第3の絶縁膜をこの順で形成する第2の工程と、
前記第3の絶縁膜上にゲートトレンチ形成時にハードマスクとなる第4の絶縁膜を形成する第3の工程と、
前記第3の絶縁膜をストッパとしてドライエッチングを行い前記第4の絶縁膜に前記ゲートトレンチの幅に対応する開口を形成する第4の工程と、
前記開口下に露出した前記第3の絶縁膜及び前記第2の絶縁膜を順次除去する第5の工程と、
前記活性領域と略平行な方向においては、前記第4の絶縁膜をマスクとして、前記半導体基板にゲートトレンチを形成し、前記ゲートトレンチの延在する方向においては、前記STI領域の前記肩状部分をマスクとして前記ゲートトレンチを形成するとともに、前記ゲートトレンチと前記STI領域との間に半導体基板の一部を薄膜状に残存させる第6の工程とを含むことを特徴とする半導体装置の製造方法。 - 前記半導体基板の前記一部は、前記ゲートトレンチ側に前記半導体基板に対して略垂直な面を備えることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第1及び第3の絶縁膜がシリコン酸化膜であり、前記第2及び第4の絶縁膜がシリコン窒化膜であることを特徴とする請求項1又は2に記載の半導体装置の製造方法。
- 前記第6の工程は、前記第4の絶縁膜及び前記第1の絶縁膜の両方に対して高い選択比を有するエッチングを用いることを含むことを特徴とする請求項1乃至3のいずれか一項に記載の半導体装置の製造方法。
- 前記第6の工程に続いて、前記ゲートトレンチの底部に厚い絶縁膜を形成する第7の工程と、前記ゲートトレンチの側面にゲート絶縁膜を形成する第8の工程とを更に備えることを特徴とする請求項1乃至4のいずれか一項に記載の半導体装置の製造方法。
- 前記第7の工程は、HDP(High Density Plasma)−CVDにより少なくとも前記ゲートトレンチの前記側面及び前記底部に絶縁膜を堆積するステップと、ウェットエッチングにより前記ゲートトレンチの前記側面上に形成された絶縁膜を除去するステップとを含むことを特徴とする請求項5に記載の半導体装置の製造方法。
- 前記ゲートトレンチ底部の前記厚い絶縁膜の下はチャネル領域とならないことを特徴とする請求項5又は6に記載の半導体装置の製造方法。
- 半導体基板にSTI領域及び前記STI領域に囲まれた活性領域を形成する第1の工程と、
前記活性領域と前記STI領域との境界における前記STI領域の肩状部分を保護する保護膜を形成する第2の工程と、
前記活性領域を横切るように一方向にゲートトレンチを形成すると同時に、前記STI領域の側面と前記ゲートトレンチの側面との間に前記半導体基板の一部を残存させる第3の工程と、
前記ゲートトレンチの側面にゲート絶縁膜を形成する第4の工程と、
少なくとも一部が前記ゲートトレンチ内に埋め込まれたゲート電極を形成する第5の工程と、
前記半導体基板の前記一部がチャネル領域として機能するように、前記活性領域内に存在する前記半導体基板のうち、前記ゲートトレンチの延在方向に対して両側に位置する部分にソース領域及びドレイン領域を形成する第6の工程とを備えることを特徴とする半導体装置の製造方法。 - 前記第2の工程を行った後、前記第3の工程を行う前に、前記ゲートトレンチが形成される部分における前記保護膜を除去することを特徴とする請求項8に記載の半導体装置の製造方法。
- 前記保護膜は、材料の異なる複数の絶縁膜によって構成されていることを特徴とする請求項8又は9に記載の半導体装置の製造方法。
- 前記保護膜に含まれる少なくとも一つの絶縁膜は、前記第3の工程において用いるマスクとは異なる材料によって構成されていることを特徴とする請求項10に記載の半導体装置の製造方法。
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US11/822,458 US7816208B2 (en) | 2006-07-13 | 2007-07-06 | Method of manufacturing semiconductor device having trench-gate transistor |
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Cited By (1)
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US8373226B2 (en) | 2009-08-31 | 2013-02-12 | Elpida Memory, Inc. | Semiconductor device including a Trench-Gate Fin-FET |
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US8866254B2 (en) * | 2008-02-19 | 2014-10-21 | Micron Technology, Inc. | Devices including fin transistors robust to gate shorts and methods of making the same |
CN102969280A (zh) * | 2012-11-30 | 2013-03-13 | 上海宏力半导体制造有限公司 | 提高半导体器件可微缩性的方法 |
KR102072410B1 (ko) | 2013-08-07 | 2020-02-03 | 삼성전자 주식회사 | 반도체 장치 및 그 제조 방법 |
CN107958871B (zh) * | 2016-10-17 | 2020-10-30 | 中芯国际集成电路制造(上海)有限公司 | 半导体装置及其制造方法 |
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JPH0281472A (ja) * | 1988-09-16 | 1990-03-22 | Hitachi Ltd | 半導体記憶装置及びその製造方法 |
JPH06268174A (ja) * | 1993-03-15 | 1994-09-22 | Toshiba Corp | 半導体装置 |
JP2001210801A (ja) * | 2000-01-25 | 2001-08-03 | Hitachi Ltd | 半導体集積回路装置の製造方法および半導体集積回路装置 |
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JP2006295180A (ja) * | 2005-04-09 | 2006-10-26 | Samsung Electronics Co Ltd | 垂直方向のゲート電極を有する電界効果トランジスタ及びその製造方法 |
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JPH08274277A (ja) | 1995-03-31 | 1996-10-18 | Toyota Central Res & Dev Lab Inc | 半導体記憶装置およびその製造方法 |
US7285466B2 (en) * | 2003-08-05 | 2007-10-23 | Samsung Electronics Co., Ltd. | Methods of forming metal oxide semiconductor (MOS) transistors having three dimensional channels |
US20060192249A1 (en) | 2004-09-20 | 2006-08-31 | Samsung Electronics Co., Ltd. | Field effect transistors with vertically oriented gate electrodes and methods for fabricating the same |
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Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0281472A (ja) * | 1988-09-16 | 1990-03-22 | Hitachi Ltd | 半導体記憶装置及びその製造方法 |
JPH06268174A (ja) * | 1993-03-15 | 1994-09-22 | Toshiba Corp | 半導体装置 |
JP2001210801A (ja) * | 2000-01-25 | 2001-08-03 | Hitachi Ltd | 半導体集積回路装置の製造方法および半導体集積回路装置 |
JP2005039270A (ja) * | 2003-07-14 | 2005-02-10 | Samsung Electronics Co Ltd | メモリ素子およびその製造方法 |
JP2005322880A (ja) * | 2004-05-06 | 2005-11-17 | Hynix Semiconductor Inc | リセスチャネル領域を備えた半導体素子の製造方法 |
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US8373226B2 (en) | 2009-08-31 | 2013-02-12 | Elpida Memory, Inc. | Semiconductor device including a Trench-Gate Fin-FET |
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