CN1694237A - 制造具有凹槽沟道区域的半导体装置的方法 - Google Patents
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Abstract
本发明是关于一种制造具有多个凹槽沟道区域的半导体装置的方法。此方法包含下列步骤:在衬底中形成多个装置隔离层;在装置隔离层和衬底上,形成硬掩模氮化物层、硬掩模氧化物层和硬掩模多晶硅层,于是可以得到硬掩模图案;使用硬掩模图案在衬底的预定区域中形成多个沟槽,以曝露多个凹槽沟道区域;选择性移除硬掩模图案;及在多个沟槽中,形成多个栅极结构。
Description
技术领域
本发明是关于一种制造半导体装置的方法;尤其是关于一种使用凹槽沟道阵列晶体管(RCAT)技术,制造半导体的方法。
背景技术
由于半导体装置集成和精密度的程度增加,所以要求的制程能力和可靠度也增加。尤其,在动态随机存取存储器(DRAM)的情形下,晶体管的特性几乎是由浅沟槽隔离(STI)制程和形成栅极结构的制程决定。此晶体管的特性是决定DRAM整体的稳定性最重要的因素。因此,应该要确实改善STI制程和形成栅极结构的制程的稳定性,以增加DRAM整体的可靠度。
STI制程是半导体装置的装置隔离方法的其中之一。换言之,先在硅衬底上形成沟槽,然后再用绝缘材料,如氧化硅层,填满沟槽内部。结果,即使在相同的隔离宽度下,也可以延伸有效的隔离长度。因此,相较于通过硅局部氧化(LOCOS)制程的装置隔离,STI制程是一种可以得到较小隔离区域的技术。
最近,有一种凹槽沟道阵列晶体管(RCAT)的技术被提出,其可以改善在制造DRAM期间的刷新特性。
图1A到图1C为通过使用RCAT技术制造半导体装置的传统方法的横截面图。
参照图1A,多个具有STI结构的装置隔离层12被形成在衬底11之上。之后,硬掩模氧化物层13和硬掩模多晶硅层14,依序沉积在衬底11的上部分之上。在此,硬掩模氧化物层13和硬掩模多晶硅层14,是被用以当作形成多个凹槽沟道区域的硬掩模。
其次,将感光层沉积在硬掩模多晶硅层14之上,然后通过透过曝光和显影制程,将感光层制作成图案,形成用以形成凹槽沟道的掩模15。
接着,通过使用掩模15当作蚀刻屏障,蚀刻硬掩模多晶硅层14和硬掩模氧化物层13,因此曝露出在衬底11预定区域的多个凹槽沟道区域。
参照图1B,在预定区域中的多个曝露的凹槽沟道区域被以预定的厚度蚀刻,于是形成多个沟槽16。在形成多个沟槽16时,掩模15全部都用完,而剩下硬掩模氧化物层13和硬掩模多晶硅层14。
参照图1C,透过湿式蚀刻制程,移除硬掩模氧化物层13和硬掩模多晶硅层14。
其次,以围绕多个沟槽16的方式,形成多个栅极氧化物层17。之后,沉积多个导电层在多个栅极氧化物层17上,以填满多个沟槽16。接着,选择性制作用于多个栅极结构和多个栅极氧化物层17的导电层的图案,于是形成多个栅极结构18。此时,多个栅极结构18的每一个,都包含埋在沟槽当中的下区域和突出超过衬底11的上部分的上区域。因此,通过栅极结构的下区域,可以形成多个凹槽沟道区域。
其次,通过执行离子植入(implantation),在衬底11上形成多个源极/漏极区19。
但是,当移除用以形成多个沟槽16,其是用以形成凹槽沟道区域,的硬掩模,即硬掩模氧化物层13和硬掩模多晶硅层14时,根据传统方法,会在多个装置隔离层12的多个顶角边缘产生多个沟(moat)M。
图2A为根据传统方法,产生多个沟M的横截面图,而图2B为根据传统方法,用以形成多个栅极结构的剩余层的横截面图。
参照图2A,在移除硬掩模氧化物层13之后,产生多个其表面变成低于在装置隔离层的多个顶角边缘处的活性区表面的沟M。
当透过湿式蚀刻制程移除硬掩模氧化物层13时,由于多个其为氧化物层的装置隔离层12也会被湿式蚀刻,所以产生这些多个沟M。此外,在形成多个栅极氧化物层之前,在执行清洗制程时,会有因额外的湿式蚀刻而使多个沟M的深度更深的问题。
参照图2B,当通过蚀刻用以形成多个栅极结构的导电层,形成多个栅极结构时,要蚀刻掉存在多个沟M当中的导电层18A就会变得佷困难。在此,若用以形成多个栅极结构的导电层18A残留在多个沟M之中时,在导电图案之间就会发生短路。
发明内容
因此,本发明的目的是要提供一种制造具有多个凹槽沟道区域的半导体装置的方法,其在凹槽沟道阵列晶体管(RCAT)制程期间,当移除硬掩模氧化物层时,能够极小化所产生的沟的深度。
根据本发明的一方向,本发明提供一种制造具有凹槽沟道区域的半导体装置的方法,其包含下列步骤:在衬底中形成多个装置隔离层;在装置隔离层和衬底上,形成硬掩模氮化物层、硬掩模氧化物层和硬掩模多晶硅层,于是可以得到硬掩模图案;在具有硬掩模图案的衬底的预定区域形成多个沟槽,以曝露多个凹槽沟道区域;选择性移除硬掩模图案;及在多个沟槽中,形成多个栅极结构。
附图说明
根据下面参考相关附图的较佳实施例的说明,本发明上述的和其他的目的与特征将会变得更清楚,其中:
图1A到图1C为通过仗用凹槽沟道阵列晶体管(RCAT)技术制造半导体装置的传统方法的横截面图;
图2A为根据传统方法,产生多个沟M的横截面图;
图2B为根据传统方法,用以形成多个栅极结构的剩余层的横截面图;及
图3A到图3E为通过使用根据本发明的RCAT技术,形成半导体装置的方法的横截面图。
具体实施方式
下面将参考附图,详细说明根据本发明的较佳实施例,制造具有多个凹槽沟道区域的半导体装置的方法。
图3A到图3E为通过使用根据本发明的凹槽沟道阵列晶体管(RCAT)技术,形成半导体装置的方法的横截面图。
参照图3A,用于多个沟槽的多个装置隔离层22被形成在衬底21上,然后在衬底21上形成硬掩模氮化物层23。
此时,硬掩模氮化物层23是以厚度范围从为约50到约200的氮化硅(Si3N4)来形成。
其次,硬掩模氧化物层24和硬掩模多晶硅层25被顺序地沉积在硬掩模氮化物层23上。此处,硬掩模氧化物层24是由二氧化硅(SiO2)制成,并且硬掩模氧化物层24的厚度范围为约50到约200。硬掩模多晶硅层25是使用制造半导体的典型制程形成的多晶硅层制成,并且硬掩模多晶硅层25较佳的厚度范围为约500到约2,000。
如上所述,用以形成根据本发明的凹槽沟道区域的硬掩模的结构,是通过堆叠硬掩模氮化物层23、硬掩模氧化物层24和硬掩模多晶硅层25所形成的三重层结构。此处,硬掩模氮化物层23除了扮演用以形成凹槽沟道区域的硬掩模的角色之外,还用以当作蚀刻硬掩模氧化物层24时的蚀刻停止层。
其次,在硬掩模多晶硅层25上形成感光层。然后,透过曝光和显影制程,将感光层制作成图案,于是可以得到掩模26。
接着,通过使用掩模26当作蚀刻屏障,依序蚀刻硬掩模多晶硅层25、硬掩模氧化物层24和硬掩模氮化物层23,于是曝露出在衬底21中的多个凹槽沟道区域。
对于另外一种方式,通过使用掩模26当作蚀刻屏障,先蚀刻硬掩模多晶硅层25。之后,移除掩模26,然后,通过使用硬掩模多晶硅层25当作蚀刻屏障,蚀刻硬掩模氧化物层24和硬掩模氮化物层23。
参照图3B,通过蚀刻预定厚度的多个曝露的凹槽沟道区域,形成多个沟槽27。在形成多个沟槽27期间,硬掩模多晶硅层25和掩模26可以全部都用完,而剩下硬掩模氮化物层23和硬掩模氧化物层24。
参照图3C,通过使用硬掩模氮化物层23当作蚀刻停止层,湿式蚀刻蚀刻硬掩模氧化物层24。此时,采用氟化氢(HF)溶液湿式蚀刻硬掩模氧化物层24。HF溶液具有不会蚀刻氮化物层的特性,所以硬掩模氮化物层23可足以扮演蚀刻停止层的角色。
参照图3D,湿式蚀刻硬掩模氮化物层23。此时,硬掩模氮化物层23是通过使用磷酸(H3PO4)溶液作湿式蚀刻。但是,因为其为氧化物层的多个装置隔离层22,对H3PO4溶液不具有选择比,所以多个装置隔离层22不会被蚀刻。
同时,除了湿式蚀刻制程之外,硬掩模氮化物层23也可以使用选择性干式蚀刻制程移除。此时,选择性干式蚀刻制程是使用氯气。
参照图3E,以围绕多个沟槽27的方式,形成多个栅极氧化物层28。之后,沉积用于多个栅极结构的导电层,直到填满在多个栅极氧化物层28上的多个沟槽27。
其次,用于多个栅极结构的导电层和多个栅极氧化物层28被选择性地图案化,于是形成多个栅极结构29。此时,每一个栅极结构29都包含埋在沟槽当中的下区域和突出超过衬底21的上区域。因此,通过栅极结构的下区域,可以形成多个凹槽沟道区域。
其次,通过执行离子植入,在衬底21上形成多个源极/漏极区30。
根据本发明的实施例,当硬掩模氧化物层24被湿式蚀刻时,因为硬掩模氮化物层23扮演蚀刻停止层的角色,所以可以防止多个装置隔离层22被蚀刻。因此,在多个装置隔离层22的顶角边缘处不会产生多个沟槽。
通过使用硬掩模氮化物层来防止多个装置隔离层的顶角边缘中沟的产生,本发明有助于对多个栅极结构容易地执行蚀刻制程而不会有任何残留层,从而提供了改善装置特性的效果。
本申请书包含2004年5月6日向韩国专利局申请的韩国专利公报第KR2004-0031938号的相关主题,此处将所有的内容都纳入参考。
本发明已对特定实施例详细说明,那些熟悉本项技术人士所做的各种不同的变化例和修正例,明显将不脱离本发明在后面的权利要求所界定的精神和范围。
主要元件符号说明
11 衬底
12 装置隔离层
13 硬掩模氧化物层
14 硬掩模多晶硅层
15 掩模
16 沟槽
17 栅极氧化物层
18 栅极结构
19 源极/漏极区
21 衬底
22 装置隔离层
23 硬掩模氮化物层
24 硬掩模氧化物层
25 硬掩模多晶硅层
26 掩模
27 沟槽
28 栅极氧化物层
29 栅极结构
30 源极/漏极区
M 沟
Claims (9)
1.一种制造具有凹槽沟道区域的半导体装置的方法,包含下列步骤:
在衬底中形成多个装置隔离层;
在装置隔离层和衬底上,形成硬掩模氮化物层、硬掩模氧化物层和硬掩模多晶硅层,于是得到硬掩模图案;
在具有硬掩模图案的衬底的预定区域形成多个沟槽,以曝露多个凹槽沟道区域;
选择性移除硬掩模图案;及
在多个沟槽中,形成多个栅极结构。
2.如权利要求第1项的方法,其中通过使用硬掩模氮化物层当作蚀刻停止层,选择性蚀刻硬掩模氧化物层,移除硬掩模图案;然后选择性蚀刻硬掩模氮化物层。
3.如权利要求第2项的方法,其中通过湿式蚀刻制程移除硬掩模氧化物层。
4.如权利要求第3项的方法,其中用以移除硬掩模氧化物层的湿式蚀刻制程是使用HF溶液执行。
5.如权利要求第2项的方法,其中硬掩模氮化物层是通过湿式蚀刻制程和干式蚀刻制程其中之一移除。
6.如权利要求第5项的方法,其中用以移除硬掩模氮化物层的湿式蚀刻制程是使用H3PO4溶液执行。
7.如权利要求第1项的方法,其中硬掩模氮化物层形成的厚度范围是为约50到约200。
8.如权利要求第1项的方法,其中硬掩模氧化物层形成的厚度范围是为约50到约200。
9.如权利要求第1项的方法,在形成栅极结构图案的步骤之前,还有包含在沟槽上形成栅极氧化物层的步骤。
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KR1020040031938A KR100615593B1 (ko) | 2004-05-06 | 2004-05-06 | 리세스채널을 구비한 반도체소자의 제조 방법 |
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JP (1) | JP4610323B2 (zh) |
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- 2004-12-20 JP JP2004368145A patent/JP4610323B2/ja not_active Expired - Fee Related
- 2004-12-22 US US11/030,438 patent/US7232727B2/en not_active Expired - Fee Related
- 2004-12-30 CN CNB2004101041664A patent/CN1316588C/zh not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
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TW200537609A (en) | 2005-11-16 |
CN1316588C (zh) | 2007-05-16 |
US7232727B2 (en) | 2007-06-19 |
TWI261877B (en) | 2006-09-11 |
JP4610323B2 (ja) | 2011-01-12 |
JP2005322880A (ja) | 2005-11-17 |
KR20050106878A (ko) | 2005-11-11 |
US20050250284A1 (en) | 2005-11-10 |
KR100615593B1 (ko) | 2006-08-25 |
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