TW571371B - Method for fabricating semiconductor package - Google Patents

Method for fabricating semiconductor package Download PDF

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Publication number
TW571371B
TW571371B TW091124149A TW91124149A TW571371B TW 571371 B TW571371 B TW 571371B TW 091124149 A TW091124149 A TW 091124149A TW 91124149 A TW91124149 A TW 91124149A TW 571371 B TW571371 B TW 571371B
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TW
Taiwan
Prior art keywords
copper
layer
forming
patent application
scope
Prior art date
Application number
TW091124149A
Other languages
English (en)
Inventor
Yong-Il Kim
Sung-Gue Lee
Yu-Seock Yang
Original Assignee
Lg Electronics Inc
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Filing date
Publication date
Application filed by Lg Electronics Inc filed Critical Lg Electronics Inc
Application granted granted Critical
Publication of TW571371B publication Critical patent/TW571371B/zh

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    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

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571371 玖、發明說明 【發明所屬之技術領域】 本發明係相關於一種半導體封裝製造方法，尤其相關 於一種能夠在基板係被疊層爲一多層體之時，省略機械處 理操作或是使用有機物質之光罩操作之製造半導體封裝的 方法。 【先前技術】 一種被使用於例如是PPGA封裝（塑料柵格陣列封裝 ;Plastic Pin Grid Assay Package)、PBGA 封裝（塑料球格 陣列封裝；Plastic Ball Grid Array Package)、PLGA 封裝（ 塑料焊盤柵格陣列封裝；Plastic Pin Land Grid Array Package )或類似封裝之半導體封裝中的多層基板係被形成爲使得 一個帶有一特定電路圖案之基板能夠被層疊至多層而處於 一絕緣狀態中，並且層疊基板係經由一穿孔而被電氣連接 於每一基板之電路圖案。 舉例而言，一種用於製造一層疊式多層基板以製造 PPGA封裝的方法係被揭示於日本專利公開第10-223800號 (美國專利第6,074,567號）之中。 在此一方法之中，一個內部電路板係將一開口形成在 一個中央部分中，並且一個連結部分係被形成在鄰近於該 開口處，用以附接至一個被連接至一半導體晶片的金線。 在一凹穴係藉由該開口而被形成並藉由堆疊諸個內部電路 板之後，一個外部電路板係被疊層在一最外層處，用以對 已疊層之內部電路板的凹穴進行密封。 571371 隨後，一個穿孔係被形成在如同上述般所製造之疊層 主體之中，一個未電鍍銅質鍍膜以及一個電解電鍍銅質鍍 膜係被形成在穿孔的內部側邊處，並且一個第一基板鎳質 鍍膜係被形成。在此時，由於內部電路板的連結部分係被 覆蓋有外部電路板，電鍍係無法被施行於其上。 在此一狀態之中，一個電路圖案形成程序係藉由對層 疊主體進行蝕刻而被施行，一防焊劑（solder resist; S/R) 係被塗層，外部電路板上相應於內部電路板之開口的一個 特定部分係藉由一個例如是路由器（router)之裝置而被移 去，用以暴露出凹穴以及連結部分。並且接著，一個已鍍 層之鎳/金鍍膜係被形成在連結部分處以及在穿孔處，從 而形成一個穿孔。 然而，此一製造方法所具有的問題係爲，其難以對外 部電路板進行機械處理，並且先前已形成之電路圖案係會 由於在製程期間所發生的撞擊或其他影響而損壞。 另外，已鍍層之鎳/金鍍層係被非必要地形成在穿孔 處。 在解決此等問題的努力之中，每一個基板係被疊層以 藉由使半導體封裝向上開啓而形成一個凹穴、一種有機物 質係被充塡在凹穴的內部、一個穿孔係被形成、電路圖案 化係被施行於其上、有機物質係被移去、並接著最下方的 基板係被處理，藉此形成了穿孔，而在同時並保護了在凹 穴內的焊墊。 然而，在此一方法之中，最下方的基板應藉由機械方 571371 法來進行處理，並且將凹穴中所充塡之有機物質完全移去 並不容易。因此，由於殘留在凹穴中之有機物質係於鎳/ 金鍍層被形成於連結部分之時作用爲一外來物質，其係會 降低半導體封裝之品質。 【發明內容】 因此，本發明之目的係爲提供一種用於製造半導體封 裝的方法，其係藉由使用一個最後被形成在焊墊中以作爲 銅鍍層之光罩的鎳/金覆層，而不需要於基板上被使用作 爲一個光罩之此等機械製程、以及有機物質移去製程。 爲了達成這些以及其他優點，並且根據本發明之目的 ，如同在本文中所體現及廣泛說明者，一種製造半導體封 裝之方法係被提供，此一方法係包括有以下步驟：形成一 個圖案於一個被形成在一絕緣基板之上方/下方表面處的 鍍銅之上、並且藉由移去其上被形成有鍍銅圖案之該絕緣 基板之一中央部分來形成一個開口，從而製造複數個形成 有圖案之板；形成一個焊墊在該等形成有圖案之板之至少 一個板的開口周圍、並且經由一種非銅之金屬材料來形成 一個第一覆層在焊墊圖案上；將該複數個形成有圖案之板 進行層疊以形成一個層疊主體；形成一個穿孔於該層疊主 體處，並且施行一個銅鍍層於該穿孔和該第一覆層之上， 以便形成一個銅覆層；以及將被形成於該第一覆層上之銅 覆層移去，並且經由一種非銅之金屬材料來形成一個第二 覆層於該第一覆層上，從而形成一個焊墊。 本發明之前述及其他目的、特點、觀念、以及優點將 571371 從本發明之以下詳細說明，並連同圖式而變爲更加顯明。 【實施方式】 現在將詳細參照本發明之較佳實施例，圖式中並有說 明該等實施例。 根據本發明而用於製造一半導體封裝之方法的特點係 在於：在製造高積體封裝之基板的疊層製程之中，一個第 一鎳-金鍍層係被施行於一個焊墊上以與一半導體晶片相連 接，而不需要一個機械式製程或是使用一有機物質之光罩 製程；一個銅鍍層係被同時施行於一穿孔及該焊墊之上； 形成在該焊墊上之銅鍍層係被選擇性地移去；並接著一個 第二鎳-鋁鍍層係被施行於該焊墊及焊球墊之上。藉此，如 同在習知技術中處理光罩製程所發生在製程中的困難性或 是由於外來物質所產生之缺陷的發生係可以被降低。 根據本發明一較佳實施例之半導體封裝的製造方法現 在將參照圖式來加以說明。 第一圖係爲一個顯示出根據本發明之形成有內部電路 圖案之板之製程的視圖。如同在第一圖中所顯示者，一個 鍍銅2係被形成在一個絕緣基板1之一表面處。而在此時 ，一個在絕緣基板1之上方表面及下方表面上被附接有一 銅涪的銅箱基板（copper clad laminate; CCL)係可以被使用 〇 隨後，爲了形成一個凹穴，絕緣基板1之中央部分係 被處理以形成一個開口 1 A，並且被形成在絕緣基板1之 下方表面處的鍍銅係藉由一般蝕刻操作而進行圖案化，用 571371 以形成一個鍍銅圖案3，從而製造出一個形成有鍍銅圖案 之板4。 開口 1 A係可以藉由在移去鍍銅2之後對絕緣基板1 進行處理而被移去，或者鍍銅2以及絕緣基板1係可以同 時被處理或移去。 另外，絕緣基板1係爲由一種具有一絕緣性質之樹脂 材料所製成，例如是玻璃、玻璃環氧樹脂、玻璃聚醯亞胺 、BT 樹脂（bismaleimide triazine resin )、或是類似材料。 形成有鍍銅圖案之板4之上方表面電路圖案係被稱之 爲第一層電路圖案，並且下方表面電路圖案係被稱之爲第 二層電路圖案。 第二圖係爲一個顯示出根據本發明之製造形成有內部 電路圖案之板1 0之製程的視圖。形成有內部電路圖案之 板10與形成有鍍銅圖案之板4係爲分別製造者。 如同在第二圖中所顯示者，在製造形成有內部電路圖 案之板1 0的製程中，鍍銅1 2係被覆層在絕緣基板1 1 的表面處，並且其上覆層有鍍銅之絕緣基板1 1的中央部 分係被處理以形成開口 1 1 A。另外，在施行一個銅鍍層 1 3於鍍銅的表面上之後，其係經由一般蝕刻程序來進行 圖案化，從而形成一個內部電路圖案1 4，而銅鍍層1 3 係被形成在鍍銅圖案之上。 形成有內部電路圖案之板1 〇的上方表面電路圖案係 被稱之爲第三層電路圖案，並且下方表面電路圖案係被稱 之爲第四層電路圖案。 11 571371 第三圖係爲一個顯示出在第二圖之形成有內部電路圖 案之板上之一第一鎳/金鍍層之製造程序的視圖。 如同在第三圖中所顯示者，一個防鍍之防焊劑2 1係 被塗敷在形成有內部電路圖案之板1 0之開口 1 1 A的內 側周圍表面處，並且在形成有內部電路圖案之板1 0之上 方表面和下方表面處，除了將被形成有焊墊2 3之開口 1 1 A的附近之外。 爲了改善在後續製程中之黏著作用力，一種熱固性防 焊劑係可以被塗敷在上方表面處，並且一種光硬化防焊劑 係可以被塗敷在形成有內部電路圖案之板10之下方表面 處。 隨後，一個第一鎳-金鍍層2 2係被形成在並未塗敷有 防焊劑的位置處，從而形成一個焊墊2 3。 第一鎳-金鑛層2 2係藉由無電式沉積鎳-金鍍層方式所 形成。在此時，鎳-金鍍層係僅被施行在暴露出來的鍍銅之 上，其並未被施行在一個所暴露出來之絕緣材料的表面上 以及在被塗敷有防焊劑的表面上。 另外，由於鎳-金鍍層係被形成以保護鍍銅，鎳-金鍍層 2 2係被形成爲儘可能地薄。 較佳的情況是，鎳-金鍍層係被形成爲0.3〜0.7//m的厚 度，並且金鍍層係被形成爲小於〇.3//m的厚度，如此無電 式沉積鎳-金鍍層係可以被施行成爲具有一個低於1 //m之 總厚度。 在本發明的較佳實施例之中，鎳-金鍍層係被形成，但 12 571371 非限制於此。亦即，任何金屬材料係可以被使用，只要銅 鍍層能夠被施行於其表面上，並且在銅鍍上施行蝕刻之時 不會被移去即可。 隨後，另一個基板係經由相同於形成有內部電路圖案 之板10之製程來加以製備及製造。並且如同在第四圖中 所顯示者，被塗敷在形成有內部電路圖案之板1 0之下側 處之防焊劑2 1係被移去，從而製造出一個形成有下方電 路圖案之板3 0。 在此時，可使用之方法爲，在熱固性防焊劑被塗敷於 形成有下方電路圖案之板3 0的上方表面處，並且一光硬 化防焊劑被塗敷在其下方表面處之後，僅僅移除光硬化防 焊劑。就此而言，形成有下方電路圖案之板3 0之上方表 面電路圖案係被稱之爲第五層電路圖案，並且下方表面電 路圖案係被稱之爲第六層電路圖案。 並且隨後，形成有鍍銅圖案之板4、形成有內部電路 圖案之板1 0、以及形成有下方電路圖案之板3 0係被相 繼地層疊，而使得每一開口 1 A、1 0 A、以及3 Ο A爲 相一致者。預浸料坯3 1之片體係被插入在該等板之間， 並且該等板係在對其提供熱量之時被加以壓迫。接著，當 預浸料坯3 1融化之時，固接每一個板以形成具有其內部 形成有凹穴（C)的疊層主體4 0。 在此實施例之中，被定位在板4、1 0、以及3 0之 間的防焊劑2 1係被層疊，而非被完全地移去。但可能的 狀況是，預浸料坯係被插入，以於防焊劑2 1移去後被加 13 571371 以層疊。另外，可使用一個黏著帶來取代預浸料坯，用以 使板4、1 0、以及3 0進行層疊。 在層疊主體4 0之中，形成有鍍銅圖案之板4、形成 有內部電路圖案之板1 〇、以及形成有下方電路圖案之板 30之開口ΙΑ、11A、以及30A係被形成爲具有不 同尺寸者。定位在上側之形成有鍍銅圖案之板4的開口係 爲最大者，並且定位在最下側之形成有下方電路圖案之板 3 0之開口 3 0 A係爲最小者。 一個垂直穿孔41係藉由使用一個鑽具而以機械方式 而形成。在此時，穿孔4 1係貫穿基板4、1 0、以及3 0之內部電路圖案。 當銅鍍層係施加於其中形成有穿孔4 1的層疊主體4 0上之時，銅鍍層4 2係形成在形成有鍍銅圖案之板4的 上方表面處、在形成有下方電路圖案之板3 0的下方表面 處、以及在穿孔4 1的內側周圍表面處。以此方式，穿孔 4 3係形成以經由電氣方式連接內部電路圖案1 4。 亦即，銅鍍層4 2係形成在第一層電路圖案處、在第 六層電路圖案處、在絕緣材料1於凹穴（C )中的表面處、在 鎳-金鍍層2 2的表面處、以及在穿孔4 3的內部。 並且隨後，穿孔4 3係被塡以例如是一導電漿料或-樹脂之充塡物44。隨後，相較於第六層電路圖案而言爲 突出者之充塡物4 4係藉由使用一個刷子而被移除。 第七圖係爲一個顯示出在第六圖之疊層主體上塗敷-防焊劑之製程的視圖。 14 571371 如同在第七圖中所顯示者，將一防焊劑5 1塗覆於層 疊主體4 0之上方表面的第一層電路圖案處，並且塗覆在 層疊主體4 0之下方表面的第六層電路圖案處。在此時， 爲了在隨後的蝕刻製程中移去在凹穴（C)內部的銅鍍層4 2 ，防焊劑5 1並未被塗敷在凹穴（C)的內部。 防焊劑5 1係從層疊主體4 0之下方表面（第六層電 路圖案）處被部分地移去，並且一個窗口 5 2係形成於其 上。在此一狀態之中，層疊主體4 0係被沉浸在一蝕刻溶 液之中。經過一段特定時間，在並未塗敷有防焊劑5 1之 部分處的銅鍍層4 2係被全部移去。 隨後，當移除防焊劑5 1之時，如同在第八圖中所顯 示者，一個連接至穿孔4 3之外部電路圖案6 1係形成在 層疊主體4 0的上方及下方表面處，並且鎳/金鍍層2 2 在凹穴（C)內部係暴露出來。 接下來，如同在第九圖中所顯示者，一個鍍金防止劑 6 3係塗敷在形成於層疊主體4 0之上方表面處的外部電 路圖案6 1之上，並且一個窗口 6 2係形成而暴露出外部 電路圖案6 1的一部份。在此時，窗口 6 2係轉變爲一個 焊球墊，用以形成一個在隨後被連接至至一分離之印刷電 路板的焊球。 一個熱固防止劑6 4係塗敷在層疊主體4 0的下方表 面處。熱固防止劑6 4係改善了在附接有一散熱件（將在 後續製程中予以描述）時之黏著性質。 並且如同在第十圖中所顯示者，施加鎳/金鍍層，用 15 571371 以在疊層主體4 0之上方表面處之窗口 6 2的一部份處、 在被形成有鎳/金鍍層2 2之焊墊2 3的表面處、以及在 凹穴（C)之內側周圍表面處形成一個第二鎳/金鍍層6 5。 並且隨後，如同在第十一圖中所顯示者，當被塗覆在 層疊主體4 0之表面處的鍍金防止劑6 3被移去之時，一 個使一焊球能夠在後續製程中被附接至其上的焊球墊71 係被形成，從而完成一種多層基板8 0。 第二鎳/金鍍層6 5係可以較第一鎳/金鍍層2 2爲 厚，或者可以根據在半導體封裝中所需鎳/金鍍層之厚度 來加以適當地調整。 關於如此製造之多層基板8 0，如同在第十二圖中所 顯示者，對於購買者依據不同狀況之要求，塗覆一光防焊 劑6 6，以保護在多層基板8 0之上方表面處的電路，一 個作爲用於連接外側之連接終端的焊球8 1係形成在焊墊 7 1的上方表面處，並且一個金屬板鏈散熱件8 3係藉由 使用一黏著劑8 2而被附接至多層基板8 0的下方表面處 ，以便被組裝至一個作爲用於組裝一封裝之一子組件的多 層基板1 0 0。 由於多層基板1 0 0對於購買者而言係作爲一個子組 件，如同在第十三圖中所顯示者，一個半導體晶片1 〇 1 係被附接至散熱件8 3於凹穴（C)內部的上方表面處，半導 體晶片1 0 1以及焊墊2 3係藉由一金線1 〇 2而連接， 並且凹穴（C)係被充塡以一充塡物，從而完成一個半導體封 裝（Ρ )。 571371 如以上所說明者，本發明之半導體封裝製造方法係具 有以下優點。 最後形成在焊墊處的鎳/金鍍層係被使用作爲在銅鍍 層中之一光罩，因此在習知技術中於基板上使用作爲一個 光罩之此等機械製程、以及有機物質移去製程係爲非必須 者。因此，在施行光罩製程時所發生在製程上的困難性或 者是由於外來物質之產生所造成的缺陷係可以被解決。 由於於不背離本發明精神及基本特徵之前提下，本發 明可以經由數種形式來實施，因此應爲吾人所了解者爲， 前述實施例係不受任何細節所限制，除非有特別指明，而 應被廣泛地架構於申請專利範圍所界定的精神與範疇之內 ，並因此，所有落入申請專利範圍之範疇與界線內的改變 樣式及修改樣式、或者是此等範疇與界線之均等物係因此 而藉由申請專利範圍所包含。 【圖式簡單說明】 (一）圖式部分 圖式係爲提供本發明更進一步之了解，並被合倂於此 且構成此說明書之一部份，該等圖式說明了本發明之實施 例，並且連同說明內容一起用以解釋本發明之原理。該等 圖式係爲： 第一圖係爲顯示出根據本發明、用以製造形成有銅覆 圖案之板之製程視圖； 第一圖係爲一個顯示出根據本發明、用以製造形成有 17 571371 內部電路圖案之板之製程的視圖； 第三圖係爲一個顯示出在第二圖之形成有內部電路圖 案之板上製造一第一^鎳/金鍍層之製程的視圖； 第四圖係爲一個顯示出根據本發明、用以製造形成有 下方電路圖案之板之製程的視圖； 第五圖係爲一個顯示出根據本發明、用以形成一層疊 主體之製程的視圖； 第六圖係爲一個顯示出根據本發明、用以在一層疊主 體中形成一穿孔之製程的視圖； 第七圖係爲一個顯示出在第六圖之疊層主體上塗覆一 防焊劑之製程的視圖； 第八圖係爲一個顯示出根據本發明、用以移去銅覆層 之製程的視圖； 第九圖係爲一個顯示出根據本發明、用以形成一窗口 之製程的視圖； 第十圖係爲一個顯示出根據本發明之一第二鎳/金覆 層之製程的視圖； 第十一圖係爲一個顯示出根據本發明、用以形成一焊 球墊之製程的視圖； 第十二圖係爲一個顯示出根據本發明、用以塗覆一防 焊劑之製程以及用以附接一個散熱件之製程的視圖；以及 第十三圖係爲根據本發明之製造程序所完成之一半導 體封裝的截面圖。 571371 (二）元件代表符號 1 絕緣基板 1 A 開口 2 鑛銅 3 鍍銅圖案 4 形成有鍍銅圖案之板 10 形成有內部電路圖案之板 11 絕緣基板 1 1 A 開口 12 鍍銅 13 銅鍍層 14 內部電路圖案 2 1 防焊劑 2 2 第一鎳-金鍍層 2 3 焊墊 30 形成有下方電路圖案之板 3 0 A 開口 31 預浸料坯 4 0 疊層主體 4 1 穿孔 4 2 銅鍍層 4 3 穿孔 4 4 充塡物 5 1 防焊劑 19 571371 5 2 窗口 6 1 外部電路圖案 6 2 窗口 6 3 鍍金防止劑 6 4 熱固防止劑 65 第二鎳/金鍍層 66 光防焊劑 7 1 焊墊 7 4 焊球墊 8 0 多層基板 8 1 焊球 8 2 黏著劑 83 金屬板鏈散熱件 1 0 0多層基板 1 0 1半導體晶片 1 0 2金線 C 凹穴 P 半導體封裝

Claims (1)

  1. 571371 拾、申請專利範圍 1、一種用於製造半導體封裝之方法’該半導體封裝 係包括有複數個絕緣基板之疊層，而該等絕緣基板係具有 一個凹穴以容納一半導體元件，該方法係包括有以下步驟 形成一個圖案於一個被形成在一絕緣基板之上方/下 方表面處的鍍銅之上，並且藉由移去其上被形成有鍍銅圖 案之該絕緣基板之一中央部分來形成一個開口，從而製造 複數個形成有圖案之板； 形成一個焊墊圖案在該等形成有圖案之板其中至少一 個板的開口周圍，並且經由一種非銅之金屬材料來形成一 個第一鍍層在該焊墊圖案上； 將該等複數個形成有圖案之板進行層疊以形成一個層 疊主體； 形成一個穿孔於該層疊主體處，並且施行一個銅鍍層 於該穿孔和該第一覆層之上，以便形成一個銅覆層；以及 將被形成於該第一覆層上之銅覆層移去，並且經由一 種非銅之金屬材料來形成一個第二覆層，以作爲將其連接 至位於該第一覆層上之一半導體層的連接線，從而形成一 個焊墊。 2 '根據申請專利範圍第1項所述之方法，其中，該 絕緣基板係爲由玻璃環氧樹脂、玻璃聚醯亞胺、以及BT樹 脂之一所製成者。 3、根據申請專利範圍第1項所述之方法，其中，該 21 571371 複數個形成有圖案之板係分別具有不同尺寸之開口。 4、 根據申請專利範圍第1項所述之方法，其中，該 第一覆層係爲一個鎳/金鍍層。 5、 根據申請專利範圍第4項所述之方法，其中，該 鎳/金鍍層係被形成爲具有一個小於1 // m的厚度。 6、 根據申請專利範圍第1項所述之方法，其中，該 層疊主體係被形成而使得個別形成有圖案之板的開口爲在 其向上時爲較大者。 7、 根據申請專利範圍第1項所述之方法，其中，該春 穿孔係被充塡有一導電漿料或一樹脂材料。 8、 根據申請專利範圍第1項所述之方法，其中，該 第二覆層係爲由一鎳/金鍍層所構成者。 拾壹、圖式 如次頁。
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