CN1428829A - 制造半导体组件的方法 - Google Patents

制造半导体组件的方法 Download PDF

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CN1428829A
CN1428829A CN02157496A CN02157496A CN1428829A CN 1428829 A CN1428829 A CN 1428829A CN 02157496 A CN02157496 A CN 02157496A CN 02157496 A CN02157496 A CN 02157496A CN 1428829 A CN1428829 A CN 1428829A
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coating
forms
plate
copper
pattern
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CN1327499C (zh
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金容一
李聖揆
梁有皙
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LG Innotek Co Ltd
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Abstract

揭示了一种制造半导体组件的方法，其中，在键合片上形成第一Ni－Au镀层以便与半导体芯片进行连接，不需要机械加工或使用有机基片的掩模操作，在通孔和键合片上同时制成铜镀层，形成于键合片上的铜镀层被选择性地除去，随后在键合片和球状焊片上形成了第二Ni－Au电镀。这样，如传统工艺中进行掩模加工而发生的困难或由于产生外部材料而引起的缺陷都可减少。

Description

制造半导体组件的方法
技术领域
本发明涉及半导体组件制造的方法，特别涉及当基片被层叠成多层时使用有机基片能够省略机械加工操作或掩模操作的半导体组件的制造方法。
背景技术
用于诸如PPGA PKG(塑料引线网格验定包装)、PBGA PKG(塑料球网格阵列包装)、PLGA PKG(塑料引线连接盘网格阵列包装)等之类半导体组件的多层基片是这样形成的，它使带有特定电路图案的基片被层叠成绝缘状态的多层，且层叠的基片通过一通孔在每个基片的电路图案之间电气连接。
比如，在日本专利公开第10-223800号(美国专利第6,074,567)中披露了为了制造PPGA PKG的制造层叠的多层基片的方法。
在该方法中，在中央部分形成了带开口的内部电路板，在开口附近形成键合部分以与连接半导体芯片的金线相连。在由通过定住内部电路板的开口形成了空腔之后，在最外层层叠外部电路板以密封层叠的内部电路板的空腔。
在其后，在以上述方法制造的层叠体中间形成了通膛，在通膛的内侧形成了非电镀的铜涂层膜和电解电镀铜涂层膜，还形成了第一电镀镍涂层膜。此时，由于内部电路板的键合部分被外部电路板覆盖，所以在其上未完成电镀。
在该状态下，形成电路图案的工艺通过蚀刻层叠体来完成，涂覆阻焊剂，通过诸如路由器之类的设备除去对应于内部电路板开口的外部电路板的某个部分，以裸露空腔和连接部分。随后，在键合部分和通膛处形成电镀镍/金的涂层膜，由此形成通孔。
然而，这种制造方法有难以机械处理外部电路板的问题，且由于在处理过程中发生的冲击和其它影响使先前产生的电路图案被破坏了。
另外，在通孔处不必要地形成了电镀的镍/金涂层。
在解决这种问题的努力中，层叠每个基片以通过向上打开半导体组件而形成空腔，有机的基片被装入到空腔内，形成通孔，在其上形成图案，除去有机的基片，且随后处理最底层的基片，由此形成通孔，同时在空腔内的键合片受到保护。
然而，同样在该方法中，最底层的基片应该通过机械方法进行处理，而且将装在空腔内的有机基片完整地除去是不容易的。因此，由于残留在空腔内的有机基片，当在键合部分形成镍/金涂层的时候起到外部材料的作用，所以该有机基片破坏了半导体组件的质量。
发明内容
因此，本发明的一个目的是提供一种用于制造半导体组件的方法，该方法不需要对基片进行机械加工或有机基片的除去处理，该基片通过使用最终在键合片上形成作为在电镀铜上掩模的镍/金涂层而被用作掩模。
为了实现本发明的这些和其它优点，并根据本发明的目的，如这里包含并广泛描述的，提供一种制造半导体组件的方法，它包括下列步骤：在绝缘基片上/下表面形成的电镀铜上形成图案，并通过去除在其上形成电镀铜图案的绝缘基片的中央部分形成开口，从而制造多个形成图案的板；在至少一个形成图案的板的开口周围形成键合垫片图案，并在键合片图案上用非铜的金属材料形成第一涂层；层叠多个形成图案的板以形成层叠体；在该层叠体上形成一通镗并在通镗上和第一涂层上完成铜涂层，从而形成一铜涂层；除去在第一涂层上形成的铜涂层，且在第一涂层上用非铜的金属材料形成第二涂层，从而形成键合片。
当结合附图，本发明的上述的和其它的目的、特征、方面和优点从以下的详细描述中变得更加明显。
附图说明
为了进一步理解本发明被包含在内并且构成本说明书一部分的附图，描绘了本发明的实施例，并且与说明书一起起到解释本发明原理的作用。
在图中：
图1是显示根据本发明的铜涂层图案形成板的制造工艺的图；
图2是显示根据本发明的内部电路图案形成板的制造工艺的图；
图3是显示在图2的内部电路图案形成板上第一电镀镍/金的制造工艺的图；
图4是显示根据本发明下层电路图案形成板的制造工艺的图；
图5是显示根据本发明形成层叠体工艺的图；
图6是显示根据本发明在层叠体中形成通孔的工艺的图；
图7是显示在图6的层叠体上涂覆阻焊剂的工艺的图；
图8是显示根据本发明除去铜涂层工艺的图；
图9是显示根据本发明形成窗口工艺的图；
图10是显示根据本发明的第二镍/金涂层工艺的图；
图儿是显示根据本发明形成球垫片工艺的图；
图12是显示根据本发明的涂覆阻焊剂工艺以及加上散热片工艺的图；
图13是根据本发明制造工艺所完成的半导体组件的横截面图。
具体实施方式
现在将详细说明在附图中所描述的本发明的较佳实施例。
根据本发明制造半导体组件的方法，其特征在于，在制造高集成包装中层叠基片的工艺中，在键合片上形成第一Ni-Au镀层以连接半导体芯片，不需要机械操作或使用有机基片的掩模操作，在通孔和键合片上同时形成了铜镀层，在键合片上形成的铜电镀层被选择性地除去，并随后在键合片和球状片上形成第二Ni-Au镀层。通过这样的工艺，如同在传统工艺中一样在先前的掩模加工中出现的工艺上的困难或由于产生外部材料而带来的缺陷可被减小。
现在将参考附图对根据本发明较佳实施例制造半导体组件的方法进行描述。
图1是显示根据本发明的铜涂层图案形成板的制造工艺的图。
如图1所示，首先，在绝缘基片1的表面形成铜镀层2。此时，可使用粘附在绝缘基片1上表面和下表面上的覆盖铜的铜箔层(CCL)。
此后，为了形成空腔，加工绝缘基片1的中央部分以形成开口1A，且通过形成铜镀层图案3的普通蚀刻操作在绝缘基片1下表面形成的铜镀层上形成图案，从而制造了铜镀层图案形成板4。
可通过在除去镀铜层2之后加工绝缘基片1来除去开口1A，或者镀铜层2和绝缘基片1可被同时加工和除去。
另外，绝缘基片1由带电绝缘特性的树脂材料制成，诸如玻璃、玻璃环氧树脂、玻璃聚酰亚胺、双马来酰亚胺三嗪树脂等。
铜镀层图案形成板4的上表面电路图案被称为第一层电路图案，而下表面电路图案则被称为第二层电路图案。
图2是显示根据本发明的内部电路图案形成板的制造工艺的图。内部电路图案形成板10与铜镀层图案形成板4分开制造。
如图2所示，在制造内部电路图案形成板10的工艺中，在绝缘基片11的表面涂覆电镀铜，且其上涂覆电镀铜的绝缘基片11的中央部分被加工以形成开口11A。另外，在铜镀层的表面形成铜镀层之后，通过普通蚀刻工艺形成图案，从而形成内部电路图案14，在该图案中，在镀铜层图案13上形成铜电镀层13。
内部电路图案形成板10的上表面电路被称为第三层电路图案，而下表面电路图案被称为第四层电路图案。
图3是显示在图2的内部电路图案形成板上第一镍/金电镀制造工艺的图。
如图3所示，在内部电路图案板10的开口11A的内圆周表面以及内部电路图案形成板10的上下表面，除形成键合片23的开口11A附近区域外涂覆电镀防护阻焊剂21。
为了提高随后工艺中的粘合力，可在内部电路图案形成板10的上表面涂覆热固性阻焊剂，在内部电路图案形成板10的下表面涂层可光致阻焊剂。
此后，在还未涂覆阻焊剂的部分形成第一Ni-Au镀层22，从而形成键合片23。
通过非电学沉积Ni-Au镀层来形成第一Ni-Au镀层22。此时，只在裸露的镀层铜上形成了Ni-Au镀层，而在裸露的绝缘材料的表面和还未涂覆阻焊剂的表面上未形成Ni-Au镀层。
另外，由于Ni-Au镀层的形成是为了保护铜镀层，所以Ni-Au镀层22应尽量薄。
较佳地，形成厚度为0.3～0.7um的Ni-Au镀层，且形成厚度低于0.3um的金镀层，从而可完成总厚度低于1um的非电沉积Ni-Au镀层。
在本发明的较佳实施例中，形成的是Ni-Au镀层，但不仅限于此。也就是说，可使用任何金属材料，只要在其表面能完成铜镀层以及当在铜镀上形成蚀刻时它不会被除去即可。
此后，备置另一基片且通过与内部电路图案形成板10相同的工艺来制造。而且，如图4所示，除去在内部电路图案形成板10的下侧涂层的阻焊剂21，从而制造下电路图案形成板30。
在此时，可使用这样的方法，其中，在下电路图案形成板30的上表面涂覆了热固性阻焊剂且在其下表面涂覆了光致固化阻焊剂之后，只除去了光致固化阻焊剂。在这一方法中，下电路图案形成板30的上表面电路图案被称为第五层电路图案，而其下表面电路图案被称为第六层电路图案。
随后，镀铜图案形成板4、内部电路图案形成板10以及下电路图案形成板30被依次层叠，使每个开口1A、10A和30A的中心都对准的状态。当对其加热时受压的板之间插入预浸处理片31。随后，当预浸处理片熔化的时候，每一个片被粘合以形成在其内部形成空腔(C)的层叠体40。
在该实施例中，位于板4、10和30之间的阻焊剂21被层叠，而不是被完整地除去。但预浸处理可以在除去阻焊剂21之后被插入以层叠。另外，为了层叠板4、10和30，可使用胶带来代替预浸处理。
在层叠体40中，形成的镀铜图案形成板4、内部电路图案形成板10以及下电路图案形成板30的开口1A、11A和30A的大小是不同的：形成的位于上侧的镀铜图案形成板4的开口最大，而形成的位于最下面的下电路图案形成板30的开口30A最小。
通过使用钻子可机械地形成垂直的通镗41。在此时，穿过形成板4、10和30的内电路图案形成了通镗41。
当用形成于其中的通镗41在层叠体40上形成铜极板时，在镀铜图案形成板4的上表面、下电路图案形成板30的下表面以及通孔41的内圆周表面上形成铜镀层42。以这种方法，形成通孔43以与内部电路图案14实现电连接。
也就是说，在第一层电路图案、第六层电路图案、空腔(C)内绝缘材料1的表面、Ni-Au镀层22的表面以及通孔43内形成铜层42。
随后，通孔43被充入诸如导电胶或树脂之类的填料。此后，相对第一层电路图案伸出的填料44用刷子除去。
图7是显示在图6的层叠体上涂覆阻焊剂工艺的图。
如图7所示，在层叠体40上表面的第一层电路图案以及层叠体40下表面的第六层电路图案涂覆阻焊剂51。此时，为了除去在随后蚀刻工艺中在空腔(C)内的铜镀层42，在空腔(C)内不涂覆阻焊剂51。
从层叠体40的下表面(第六层电路图案)除去部分的阻焊剂51，并且在其上形成窗口52。在该状态下，层叠体40被浸入蚀刻溶剂中。过了一段时间，在还未涂覆阻焊剂51的地方铜镀层42被统统除去。
此后，如图8所示，当除去阻焊剂51时，在层叠体40的上表面和下表面都形成了连接于通孔43的外部电路图案51，且镍/金镀层22裸露在空腔(C)内。
下一步，如图9所示，在形成于层叠体40上表面的外部电路图案61上涂覆金电镀抗蚀剂63，且形成窗口62使外电路图案61的一部分裸露出来。此时，窗口62被转变成球形焊片以便后面形成连接单独印刷电路板的焊接球。
在层叠体40的下表面涂覆热固性抗蚀剂64。当粘附散热片时(在随后的工艺中将描述)热固性抗蚀剂64可改进粘附特性。
如图10所示，形成镍/金镀层以便在层叠体40上表面形成的窗口62的位置以及在与空腔(C)内圆周表面上第一镍/金电镀层22一起形成的键合片23的表面上，形成第二镍/金镀层65。
随后，如图11所示，当除去涂覆在层叠体40表面上的金电镀抗蚀剂63时，形成了在随后工艺中与焊球粘附的球形焊片71，从而形成多层基片80。
第二镍/金镀层65可厚于第一镍/金电镀层22，或者可以根据半导体组件中对镍/金镀层所需要的厚度适当调节。
关于这样制造如图12所示的多层基片80，如图12所示，为了根据情况满足购买者的需要，涂覆光致阻焊剂66以保护在多层基片80上表面的电路，在球形焊片71的上表面形成起到与外部连接终端作用的焊球81，且通过使用粘合剂82在多层基片80的下表面粘合金属板链散热片83，从而被装配成多层基片100作为装配组件的子组件。
随着多层基片100如图13所示地作为子组件供应给购买者，在空腔(C)内散热片83的上表面粘合半导体芯片101，半导体芯片101与键合片23通过金线102连接，而空腔(C)被装入填料，从而完成半导体组件(P)。
至今所描述的本发明的制造半导体组件的方法具有以下的优点。
这就是，最终在键合片上形成镍/金镀层被用作铜镀层中的掩模，因此在这种如传统工艺中的用作掩模的基片上的机械加工和除去有机基片的工艺就不是必须的了。因此，在形成掩模工艺时发生的工艺困难或由于产生外部材料而引起的缺陷都可被解决。
因为本发明可在不脱离其精神和本质特征的前提下可以以多种形式实施，所以应该理解，上述的实施例，除非有特别说明，否则不受任何上述描述中细节的限制，而应该在由所附权利要求定义的精神和范围内被广泛地解释，并因此，处于权利要求的要求和范围以及这种要求和范围的等效形式内的所有变化和修改都可被所附的权利要求所包含。

Claims (8)

1.一种制造半导体组件的方法，该半导体组件包含具有空腔的多个绝缘基片，该空腔可容纳半导体元件，其特征在于，所述的方法包括步骤：
在绝缘基片上/下表面形成的铜镀层上形成图案，并通过除去在其上形成铜镀层图案的绝缘基片的中央部分来形成开口，从而制造多个图案形成板；
在至少一个图案形成板的开口周围形成键合片图案，并用非铜的金属材料在键合片图案上形成第一涂层；
层叠多个图案形成板以形成层叠体；
在层叠体上形成通镗并在通镗和第一涂层上形成铜镀层，从而形成铜镀层；以及
除去形成在第一涂层上的铜涂层，并用非铜的金属材料形成第二涂层，作为它与第一涂层上半导体层连接的连接线，从而形成键合片。
2.如权利要求1所述的方法，其特征在于，所述的绝缘基片是由玻璃环氧树脂、玻璃聚酰亚胺以及BT树脂中的一种制成。
3.如权利要求1所述的方法，其特征在于，多个图案形成板分别具有不同尺寸的开口。
4.如权利要求1所述的方法，其特征在于，第一涂层是镍/金镀层。
5.如权利要求4所述的方法，其特征在于，形成的镍/金镀层的厚度低于1um。
6.如权利要求1所述的方法，其特征在于，层叠体的形成是各个形成板的开口随着它向上而越来越大。
7.如权利要求1所述的方法，其特征在于，所述的通孔被装入导电胶或树脂材料。
8.如权利要求1所述的方法，其特征在于，第二涂层是由镍/金镀层制成的。
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