TW540169B - Monolithic series/parallel LED arrays formed on highly resistive substrates - Google Patents

Monolithic series/parallel LED arrays formed on highly resistive substrates Download PDF

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TW540169B
TW540169B TW091105902A TW91105902A TW540169B TW 540169 B TW540169 B TW 540169B TW 091105902 A TW091105902 A TW 091105902A TW 91105902 A TW91105902 A TW 91105902A TW 540169 B TW540169 B TW 540169B
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substrate
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William David Collins Iii
Jerome Chandra Bhat
Daniel Steigerwald
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Lumileds Lighting Llc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/08—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/50—Wavelength conversion elements
    • H01L33/508—Wavelength conversion elements having a non-uniform spatial arrangement or non-uniform concentration, e.g. patterned wavelength conversion layer, wavelength conversion layer with a concentration gradient of the wavelength conversion material

Description

540169 A7 __________ B7 五、發明説明（ ） 1 發明背景 相關技藝說明 ¥用的I光一極體（LED)材料’例如GaAs，其在以單片製 ^時’可允許僅單一接面或多重並聯接面裝置的架構。圖1A 所不為一典型的多重並聯接面LED陣列1〇。數個p型區域13成 長在一共用n型區域18之上。N接點11連接到η型區域18，而數 個Ρ接點14連接到ρ型區域13。該裝置係以在一基板12上形成η 型區域18來製造，然後形成一連續ρ型層在該η型區域之上。 該ρ型層即藉由機械式地鋸開或化學蝕刻溝渠15在ρ型區域13 之間來分割成分散的區域。圖1Β所示為另一個多重並聯接面 LED陣列16。除了機械式鋸開或化學蝕刻之外，ρ型區域13彼 此藉由擴散而電性隔離。圖认及1Β中所示的單片陣列係限 於圖2所示的並聯架構’因為在該裝置的相對側上的接點使 -用會需要一共用導電層，即η或ρ層。 發明概要 根據本發明，一串聯或並聯LED陣列形成在一絕緣或高電 阻性基板上，使得該陣列的？及n接點皆位在該陣列的相同側 上。該個別LED係藉由溝渠或離子植入而彼此電性隔離。沉 積在該陣列上的内連線連接該陣列中個別LED的接點。在一 些具體實施例中，該LED為形成在一藍寶石基板上的III族氮 化物裝置。在一具體實施例中，該ΙΠ族氮化物裝置係形成在 高電阻性SiC或III族氮化物基板上。在一具體實施例中，形成 在一單一基板上的兩個LED係反並聯連接來形成一單片靜電 放電保護電路。在一具體實施例中，形成在一單一基板上的 ----— _ -4-___ 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 540169 A7 B7 五、發明説明（ ） 2 多個LED係串聯連接。該串聯陣列係運作在一較高的電壓， 其高於相同區域的單一 LED，藉此簡化電源供應設計。在一 具體實施例中，形成在一單一基板上的多個LED係並聯連接 。在此具體實施例中，多個p型區域係形成在一單一 η型區域 上，使得該η型區域環繞每個該ρ型區域，並介於該ρ型區域 中。在一些具體實施例中，一磷質層覆蓋該基板的一部份， 其上形成一或多個個別的LED。 圖式簡單說明 圖1A及1B所示為典型的多重並聯接面LED陣列。 圖2所示為一並聯LED陣列的電路圖。 圖3-6所示為根據本發明在不同製造階段中一串聯LED陣列 的具體實施例。 圖7A及7B所示為兩個串聯LED陣列的具體實施例。 圖8A所示為一串聯LED陣列的具體實施例之平面圖。 圖8B所示為一串聯LED陣列的電路圖。 圖9A所示為一串聯/並聯LED陣列的平面圖。 圖9B所示為一串聯/並聯LED陣列的電路圖。 圖10所示為一對反並聯LED的電路圖。 圖11所示為一單片ESD保護結構之具體實施例的平面圖。 圖12所示為圖11所示之結構的橫截面圖。 圖13所示為一並聯LED陣列的橫截面圖。 圖14所示為圖13所示之結構的平面圖。 圖15所示為具有磷來覆蓋該個別LED之一的一單片LED陣 列。 -5- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 裝
540169 A7 B7 五、發明説明（ ） 具體實施例之詳細說明 目前在製造高亮度發光二極體（LED)中有興趣的材料系統 而能夠運作在橫跨該可見頻譜者，為第III-V族半導體，特別 是鎵、鋁、銦及氮的二元、三元及四元合金，其亦稱之為III 族氮化物材料。此處所指的該III族氮化物半導體層為該通式 AlxGaylr^.yN (〇£χ$ 1，1，〇Sx+yS 1)所代表的化合物，其可 進一步包含第III族元素，例如硼及鉈，而其中一些氮可由磷 、砷或銻所取代。基本上，III族氮化物裝置可藉由金屬有機 化學汽相沉積（MOCVD)，分子束磊晶（MBE)，或其它磊晶技 術來蟲晶地成長在藍寶石、破化X夕或氮化鎵的基板上。藍 寶石基板因為其可廣泛地取得及易於使用，而經常使用。藍 寶石為一絕緣體。由Krames等人在1999年12月22曰所提出的專 利申請序號09/469,657中，其名為「具有增進的光線產生能力 之III族氮化物發光裝置」，其在此引用做為參考，其中揭示 該種在高折射係數基板上成長的III族氮化物發光裝置，其具 有低光學吸收率。這些基板可為SiC或III族氮化物材料，並由 於低雜質含量而具有高電阻。成長在絕緣或高電阻性基板 上的III族氮化物裝置，必須同時具有正極及負極電性接點到 位在該裝置之相同側上的該蠢晶成長的半導體。相反地，成 長在導電基板上的半導體裝置，例如圖1A及1B所示，其基本 上製造為使得在該磊晶成長材料之上形成一電性接點，而 在該基板上形成另一電性接點。 藉由使用絕緣或高電阻性基板，III族氮化物單片LED陣列 可由在該個別LED之間形成溝渠或離子植入區域來製造，以 --—___-—- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 裝
540169
4 電性隔離該個別的LED。圖3-7所示為根據本發明一具體實施 例所製造的一 ΙΠ族氮化物單片LED陣列。在圖3中，一 n型層22 ，其例如為GaN摻雜有Si、GbtO，其係形成覆蓋高電阻性基 板20。一例如為InGaNw活性層23 ,即接著形成覆蓋n型層22， 而最後為一 ρ型層24，例如為AiGaN摻雜有Zn、Mg、Be、以或
Cd其係形成覆盖該活性層。實際上疊層u、Μ及％可包含 數個不同、组成及摻雜物濃度的次疊層，其為了清楚起見而
省略。舉例而言，η型層22可包含一成核層，一高電阻性QaN 層（例如未經過刻意摻雜的GaN層），及一輕微11型掺雜層，然 後是一更為重摻雜n型層。活性層23例如可為一多重量子井 結構。 在圖4中，该η型層22，該活性層23及ρ型層24的一部份被蚀 刻掉而形成一溝渠26。所使用的蝕、刻例如可為一反應離子蝕 刻，而利用一含氯的蝕刻劑氣體，例如BCb。溝渠26係足夠 寬，可以電性隔離在該溝渠兩側上的半導體層。溝渠％被蝕 刻下到該基板，或下到在n型層22之下的一高電阻性層，例 如未刻意摻雜的GaN層。類似地，該相鄰LED可使用一離子 植入製私來電性隔離，其可產生成為高電阻性的中介材料。 P型層24及活性層23的一部份中，每個皆殘留了半導體材料 的島，其即被蝕刻掉，如圖5所示，其係使用例如反應離子 蝕刻。該第二蝕刻曝露了 n型層22上的突出部28，其為n型接 點最終形成之處。 現在請參考圖6，n接點形成的突出物可由沉積一介電材料 0在涘裝置之上來電性隔離。然後該介電層即被圖樣化，並
540169 A7 B7 五、發明説明（5 ) 在η型層22及p型層24上被移除來打開接點洞，例如介電層30 即留在該基板上的個別LED之間的溝渠26中，以及在每個 LED的曝露之p型層及η型層之間的平台壁上。介電層30例如 可為氧化石夕、氮化碎、氮氧化碎、氧化銘或任何其它適當 的介電材料。 圖7Α及7Β所示為兩個完成的串聯LED陣列的範例。圖7Α所 示為一種裝置，其中在該陣列中的LED係由溝渠所隔開。圖 7B所示為一種裝置，其中在該陣列中的LED係由離子植入區 域301所隔開。電極材料係以沉積及圖樣化來形成p及η接點32 。典型的接點材料對於η接點為Α1或Ti-AL·對於ρ接點則為Ag 、Au、Ni、Pt或其合金。接點32可為透明，例如光線可通過 該磊晶層的表面取出之裝置，或反射式，例如光線係經由該 基板取出的覆晶裝置。在沉積及圖樣化該接點之後，一未連 接的發光二極體的陣列即已形成在一單一基板上。其它處 理流程可用來發展相同的最終結構。然後該LED可連接在許 多不同的架構中。 用於連接在該裝置上的個別LED之内連線34，接著被沉積 。内連線34可為例如Al、Cu、Au、Ag或像是AlSiCu的合金。ρ 及η接點32為形成與該半導體層之歐姆接點之最佳材料，其 中内連線34為一厚的，及高導電性材料，其為承載電流的最 佳材料。如果光線經由透明接點而由該裝置取出，内連線34 即沉積為儘可能不要阻隔該接點，用以最小化在該内連接 中所吸收的光線量。圖7Α及7Β中所示的兩個LED係以串聯連 接，其將該LED B的η接點連接到LED A的ρ接點。顯而易見地 -8 ~ 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 裝
540169 A7 B7 五、發明説明（ ） 6 ，金屬内連線34可沉積來在許多不同的架構中連接一單片陣 列的LED。 在一具體實施例中，例如圖8A及8B所示，一四個LED的串 聯陣列係串聯連接在一平衡的正方形陣列中。圖8B所示為一 四個LED串聯連接在一正方形陣列中的電路圖。圖8A所示為 圖8B之具體實施例的平面圖。其需要來最小化該LED陣列的 最大尺寸，因為在製造之後，該陣列係在一光學儀器中被封 裝，並由該封裝的陣列中導引出光線。這個光學儀器通常配 合光源以幾何學方式成長。 圖8A中的陣列具有四個串聯連接的LED，其係經由蝕刻來 電性隔離，以移除III族氮化物材料，而在該個別LED之間形 成一溝渠80，如以上在圖3-7A中所述。該I虫刻進行到至少一 高電阻性III族氮化物層，例如一非刻意摻雜的GaN層。該電 性内連線係由金屬化跡線81所提供。所得到的裝置可由圖8B 所示的電子電路來代表。因此此裝置之運作，相較於在該相 同活性範圍區域之單一 LED，其電壓為4倍，而電流為1/4倍。 舉例而言，一 1 mm2的III族氮化物LED可運作在3.0 V及350 mA 。此相同活性接面區域，分割成四個串聯内連線的LED，如 圖8A所示，其提供一裝置而運作在12.0 V及87.5 mA。此較高 電壓及較低電流的運作，對於該LED陣列的電子驅動器電路 的需求較低。事實上，該電子驅動器電路可在較高的電壓下 以較高的效率來運行，而可改善該LED發光系統的整體效率 。根據此具體實施例的一單片裝置，其比_聯地附著個別的 LED晶粒的習用方式要較佳。在該習用方式中，該LED晶粒 ___ 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 裝
線 540169 A7
7 ::占用刪面積會因為該晶粒附著機器所需要的公差而 ♦、此4+必要地增力口了該整體LED的光學源極尺寸，並 為要增加該LED系統中後缋的氺與w 舍 、，的光學儀备尺寸。在該較佳具體 貝把例中’該二極體可儘可能地靠近而隔開，如同在該溝渠 姓刻或離子植入之電性隔_ ,, 隔離所允终。孩溝渠或離子植入區 度可小到數微米，所以在該具體實施例 裝密度可以非常地高。 根據本發明，LED的單片串聯陣列可提供一些好處。首先 ’單片陣列減少了連接到外部電路的數目，例如_次黏著。 如果該裝置形成使得光線係經由透明接點來由該裝置的蟲 曰曰W取出貝！減 > 連接到外部電路之數目即代表光線可由 ㈣置的更多面積上取得。在這種裝置中，基本上該係 藉由打.泉接a來連接到外部電路，其會部份地阻礙了通常 是由該LED晶粒所取出的光、線。内連線基本上使得此取出光 線的阻礙能降到最低的程度。如果該裝置為一覆晶，較少的 接點到該次黏著代表了該裝置可具有更多的活性區域來產 生光線。其次，如上所述，單片率聯陣列之運作電壓高於一 個別的LED。一較南的運作電壓可簡化一電源供應的設計來 驅動該LED陣列。 圖9A及9B所示為一平衡的正方形串聯/並聯LED陣列。圖9B 所不為一四個led之電路圖，其中兩個串聯連接的LED連接； 成兩個並聯的一列。圖9A所示為圖9B的一具體實施例的平 面圖。這種串聯/並聯陣列之形成可參考以上圖3_7a所述。 圖10所示為一靜電放電（ESD)保護電路，其中兩個二極體 ———_ — -本紙張尺度適用中國國家標準(CNS) A4規格(210X297公着） 裝 訂
540169 A7 B7 五、發明説明（ 係以一反並聯架構來連接。該第一 LED箝制在該第二LED中 的反向崩潰。圖11及12所示為一單片ESD保護電路的一具體 貫施例40。結構A及B係形成在一高電阻性基板2〇上。一結構 A係連接成一 LED來產生光線，而另一結構B係用來箝制LED A中的反向崩潰。p型層仙及仙覆蓋了活性區域物及桃，其 係形成在η型層42a及42此±。一溝渠43形成在裝置八及B之間 。在η型層42a及42b上接點形成的突出部之曝露使得該n電極 45a及45b為彼此相對的溝渠43。一介電js ^ 屬47電性隔離該p型層 及η型層。p電極44a及η電極45b係由内連崎^ %或46a所連接，使得該 LED A的p接點係連接到該箝制裝置B的 1 n接點。在該内連線 46a所沉積的區域中，該LED A的η接點伤p， %精由介電層47來與 内連線46a隔離，如圖12所示。在圖11中郎：一 尸斤不，該LED A的p接 點與該箝制裝置B的η接點之間的内連畤# 、 果係形成在該裝置的 一側上，而該LED Α的η接點與該箝制裝奢 i夏β的p接點之間的内 連線係形成在該裝置的另-側上。然後該結構可藉由坪料 凸塊或打線接合48來連接到-次黏著或其它結構(未示出）。 圖11及12所示為該箝制裝置與該LEDa 4 ^為相同尺寸的結構。 因為該箝制裝置在正常運作情況下連不 +攻射光線，該箝制 裝置的尺寸可相對於該led而降低。在〜a & 伐具體實施例中，該 '具體實施例中，該 I該裝置可用一交 箝制裝置的Μ接面可形成在-焊料凸_打線接合48之下， 使得其不會損失有用的發光區域。在另_ 兩個反並聯二極體的尺寸大致上相等， 流電源來運作。 圖13及14所示 並聯LED陣列也可形成在高電阻性基板i -11 本紙張尺度適用中國國家標準(CNS) A4規格(210χ 297公釐） 540169 A7 B7 五、發明説明（ ） 9 為這種陣列的一具體實施例。三個p型區域90、91及92係彼此 藉由介在該p型區域之單一連續η型區域93來隔離。沉積在p 型層24上的ρ接點32b及沉積在η型層22上的η接點32a係由焊料 凸塊95來連接到一次黏著（未示出）。該次黏著可包含控制電 路或適當的連接來獨立地定址每個p型區域。在這種具體實 施例中，每個LED可彼此獨立運作。 一種單一 LED，該η型區域介入一單一 p型區域的部份，其 係描述於Krames等人於1999年12月22日所提出的專利臨時申 請序號09/469,657中，其名為「具有增進的光線產生能力之III 族氮化物發光裝置」。該Krames等人所提出的裝置缺少了在 η接點93的上方水平部份96，及該η接點的上方兩個焊料凸塊 ，如圖14所示。因此，來自該兩個下方η接點焊料凸塊的電流 不會立即分散到該η接點93的垂直臂97之最上方部份。事實 上，該η接點材料的電致遷移會切斷電流流動到這種裝置的 該η接點之垂直部份。相反地，圖14所示的該對稱性並聯接 面裝置提供了更多的電流流動路徑，而增加了冗餘性。該η 接點的上方水平臂96可消除在該垂直臂97上方的「無效端 點」，因此電流會立即分散到該η接點93的所有部份。 在一 LED的串聯或並聯單片陣列中的一或多個個別的LED ，其可用一磷來覆蓋，以改變由該LED所產生的光線色彩， 如圖15所示。在一覆晶裝置中，一磷質被覆100係印在該基板 的一部份之底面上，其上形成該陣列中一單一 LED。施加該 磷質被覆到該覆晶裝置的基板之一種方法係更為詳細描述 於Lowery所提出的專利臨時申請序號09/688,053，其名為「發 -12 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 裝
540169 A7 B7 五、發明説明（ ） 10 光二極體上的模印磷質層」，其於2000年10月13日立案，在 此引用做為參考。藉由施加一磷質被覆在一單片陣列中的 一些LED之上，LED陣列可同時產生不同顏色的光線。這種 陣列可用來混合色彩，藉以形成白色光。對於一 LED陣列加 入有獨立定址的並聯LED耦合於選擇性的磷質配置，其可產 生一可調色彩的LED陣列。 當本發明的特殊具體實施例已經顯示及說明時，熟習此 項技藝者將可瞭解到在不背離本發明之廣義角度之下可以 進行變化及修正，因此，所附申請專利範圍係要在其範圍内 來涵蓋在此發明中真實精神及範圍内的所有這種變化及修 正° ____-13- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐）

Claims (1)

  1. 540169 A8 B8 C8 D8 六、申請專利範圍 1. 一種形成於高電阻性基板上之發光裝置之陣列，該陣列 包含= -一第一發光裝置，其包含： -一第一 η型層覆蓋該基板的一第一部份； -一第一活性區域覆蓋該第一 η型層； -一第一 ρ型層覆蓋該第一活性區域； -一第一 η接點連接於該第一 η型層； -一第一 ρ接點連接於該第一 ρ型層，其中該第一 η接點 與該第一 ρ接點係形成在該裝置的相同側上； -一第二發光裝置，其包含： -一第二η型層覆蓋該基板的一第二部份； -一第二活性區域覆蓋該第二η型層； -一第二ρ型層覆蓋該第二活性區域； -一第二η接點連接於該第二η型層； -一第二ρ接點連接於該第二ρ型層，其中該第二η接點 與該第二ρ接點係形成在該裝置的相同側上； -一溝渠與一離子植入區域其中之一係區隔該第一發 光裝置及該第二發光裝置；及 -一第一内連線連接該第一 η接點及第一 ρ接點之一到 該第二η接點及第二ρ接點之一。 2. 如申請專利範圍第1項之陣列，其中該第一及第二η型層 ，該第一及第二活性區域，及該第一及第二ρ型層包含III 族氮化物層。 3. 如申請專利範圍第1項之陣列，其中該基板係由藍寶石、 -14- 本紙張尺度適用中國國家標準(CNS) Α4規格(210 X 297公釐) 540169
    Sic及III族氮化物材料所構成的群組中選出。 4·如申請專利範圍第1項之陣列，其中該第一内連線連接該 第一 P接點到該第二η接點，該陣列進一步包含一第二内 連線連接該第二ρ接點到該第一 η接點。 5. 如申請專利範圍第4項之陣列，進一步包含一介電材料層 ，其位在該第一及第二内連線之一部份之下。 6. 如申請專利範圍第1項之陣列，其中該第一發光裝置及該 第二發光裝置係串聯連接。 7·如申請專利範圍第1項之陣列，其中該第一發光裝置及該 第二發光裝置係並聯連接。 8. 如申請專利範圍第1項之陣列，進一步包含一磷質層，其 塗佈了相對於該第一 η型層的該基板之第一部份的一表 面0 9. 如申請專利範圍第1項之陣列，、進一步包含在該第一 η型 層及該第二η型層之下的一高電阻性層，其中該高電阻性 層形成該溝渠的底部。 10. 如申請專利範圍第1項之陣列，進一步包含： '•一第三發光裝置，其包含： -一第三η型層覆蓋該基板的一第三部份； -一第三活性區域覆蓋該第三η型層； -一第三ρ型層覆蓋該第三活性區域； -一第三η接點連接於該第三η型層； -一第三ρ接點連接於該第三ρ型層，其中該第三η接點 與該第三ρ接點係形成在該裝置的相同側上； -15- 本紙張尺度適用中國國家標準(CNS) Α4規格(210X297公釐) 六、申請專利範圍 -一第四發光裝置，其包含·· -一第四η型層覆蓋該基板的一第四部份；. -一第四活性區域覆蓋該第四η型層； -一第四ρ型層覆蓋該第四活性區域； -一第四η接點連接於該第四η型層； -一第四ρ接點連接於該第四ρ型層，其中該第四η接點 與該第四ρ接點係形成在該裝置的相同側上； -一第二内連線連接該第一 η接點到該第三ρ接點； -一第三内連線連接該第二η接點到該第四ρ接點；及 -一第四内連線連接該第三η接點到該第四η接點； -其中該一溝渠與一離子植入區域之一區隔了每個第 一、第二、第三及第四發光裝置彼此之間；及 -其中該第一内連線連接該第一 ρ接點到該第二ρ接點。 U· —種形成於高電阻性基板上之ΠΙ族氮化物發光裝置的陣 列，該陣列包含： -一第一導電形式的疊層覆蓋該基板； -複數個活性區域覆蓋該第一導電形式疊層，使得在兮 複數個活性區域中的每一個之下的一區域係由該第一 導電形式疊層的一部份所環繞，而該第一導電形式叠 層的部份係介於在該複數個活性區域中每個活性區域 之下的區域； -複數個第一導電形式®層，其覆蓋該複數個活性區域 -一第一接點連接到該第一導電形式疊層；及 -複數個第二接點連接到該複數個第二導電形式疊層 -16- 540169
    12·如申請專利範圍第.丨丨項之陣列，其中該第一接點環繞在 遠複數個活性區域中每個活性區域之下的一區域。 以如申請專利範圍第u項之陣列，其中該第一導電形式疊 層包含摻雜Si的GaN。 U.如申請專利範圍第丨丨項之陣列，其中該複數個第二導電 形式疊層包含摻雜Mg的AlGaN。 b·如申請專利範圍第Π項之陣列，其中該複數個第二接點 包含銀。 W如申請專利範圍第丨丨項之陣列，其中該第一接點包含A1。 R如申請專利範圍第1丨項之陣列，其中該第一接點包含Ag。 W如申請專利範圍第丨丨項之陣列，其中該基板係由藍寶石 、SiC，及III族氮化物材料所構成的群組中選出。 19.如申請專利範圍第丨丨項之陣列，進一步包含一磷質層， 其塗佈了該複數個活性區域之二之下的該基板之表面的 一部份，該表面係相對於該第一導電形式疊層。 20· —種在一高電阻性基板上形成一發光裝置陣列之方法， 该方法包含： -形成一 η型層覆蓋該基板； -形成一活性區域覆蓋該η型層； -形成一 ρ型層覆蓋該活性區域； -触刻掉該η型層的一部份，該活性區域，及該ρ型層， 以形成一溝渠來區隔一第一裝置與一第二裝置； -蝕刻掉該ρ型層的一部份，與在每個該第一及第二裝置 之上的該活性區域，以曝露該η型層的一部份； -17- 本紙張尺度適用中國國家標準(CNS) Α4規格(210 X 297公釐) 裝
    540169 8 8 8 8 ABCD ~、申請專利範圍 -在該第一及第二裝置的該P型層上形成第一及第二P接 點； > -在該第一及第二裝置的該η型層上形成第一及第二η接 點； -沉積一内連線連接該第一 η接點及該第一 ρ接點之一到 該弟二π接點及遠弟《— ρ接點之 。 -18- 本紙張尺度適用中國國家標準(CNS) Α4規格(210 X 297公釐）
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US6547249B2 (en) 2003-04-15
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US20020139987A1 (en) 2002-10-03
JP2002359402A (ja) 2002-12-13

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