TW462125B - Semiconductor device and manufacturing method therefor - Google Patents

Semiconductor device and manufacturing method therefor Download PDF

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Publication number
TW462125B
TW462125B TW89106465A TW89106465A TW462125B TW 462125 B TW462125 B TW 462125B TW 89106465 A TW89106465 A TW 89106465A TW 89106465 A TW89106465 A TW 89106465A TW 462125 B TW462125 B TW 462125B
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TW
Taiwan
Prior art keywords
layer
semiconductor
wire
hole
substrate
Prior art date
Application number
TW89106465A
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English (en)
Inventor
Tadatomo Suga
Original Assignee
Oki Electric Ind Co Ltd
Sanyo Electric Co
Sony Corp
Nippon Electric Co
Sharp Kabushiki Kaisha &
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Application filed by Oki Electric Ind Co Ltd, Sanyo Electric Co, Sony Corp, Nippon Electric Co, Sharp Kabushiki Kaisha & filed Critical Oki Electric Ind Co Ltd
Application granted granted Critical
Publication of TW462125B publication Critical patent/TW462125B/zh

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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

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經濟部智慧財產局員工消t合作社印製 6 2 12 5 A7 _B7 五、發明說明（1 ) 發明背景： 發明領域： 本發明係關於一種半導體裝置及其製造方法，其中半 導體基體上之多層膜及電線層使用固態接合技術被接合在 一起。特別是，關於減小輻射雜訊。 習知技藝之敘述： 在半導體裝置之領域中，已知一種用於消除雜訊之電 磁雜訊遮蔽，其中導電材料以包住方式施加至半導體基體 上之電線層的周圍，例如日本公開專利Η - 5 _ 47767所揭示。 由日本公開專利Η- 5 — 4 7 9 4 3可知類比/數位 混合半導體裝置中之此構造，其中在交叉點遮蔽線擺設於 易遭受雜訊的高頻數位信號線與類比信號線之間，且遮蔽 線擺設作爲上與下層，且擺設在類比信號線之側面上。 在上述習知技術中，相同半導體基體上之電線經由具 有導電材料之絕緣體被包住，以避免輻射雜訊之效果。此 構造可有效避免在相同半導體基體上發生輻射雜訊。 然而，如果欲避免發生多層半導體基體上之輻射雜訊 ，不可直接使用上述構造。 特別是，使用多層半導體基體，需要多層膜形成處理 。使用增加數目層的多層膜，多層膜之表面變得不規則增 加，使得喪失平面平滑性。如果層之數目進一步增加，膜 表面變得更不規則，導致在處理的過程中易發生線破裂。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公« ) I I I I I I — — — — — — — ^ ills — — — — — — — — <請先閲讀背面之注意Ϋ項再ΐ,^本頁) ~ 4 - 462125 A7 B7 經濟部智慧財產局負工消費合作社印製 五、發明說明（2 ) 此表示在形成上述遮蔽時會遭遇困難。 如果欲在半導體裝置中達成較高的操作速度，需要減 小電線之長度（以增加密度）並使用較接近直電線之電線 。亦即，由於隨著操作速度增加，輻射程度較高，需要採 取措施以對抗輻射雜訊，減小電線之長度（以增加密度） 並使用較接近直電線之電線。 這是關於半導體基體之裝置構造，需要考慮包圍裝置 構造之接地層、電源層與電線層，嚐試增加半導體基體之 操作速度。 發明節要： 所以，本發明之目的在於提供一種新穎半導體裝置及 用於製造新穎半導體裝置之方法，其中可減小接線之長度 ，使用較接近直電線之電線，採取措施對抗輻射雜訊。 在一觀點中，本發明提供一種半導體裝置，半導體裝 置中各載有半導體元件之許多半導體基體被接合在一起， 其中絕緣層置於各半導體基體上，形成一連接層通過絕緣 層以連接至半導體元件上之電線層，且其中導電材料之導 電層藉對齊連接線而成型以形成開口，導電層形成在至少 一個半導體基體之接面表面上。半導體基體被接合在一起 ’以相互連接各半導體基體上所形成的連接電線。 在另一觀點中，本發明提供一種用於製造半導體裝置 之方法，半導體裝置中各載有半導體元件之許多半導體基 體被接合在一起，此方法包含以下步驟：沈積一絕緣層於 本紙張尺度適用中國國家標準<CNS)A4規格（210 X 297公釐） 11 -- ----1111 —— — — — — — --11---"5^ (請先閱讀背面之注意事項#-垓寫本頁> -5- 經濟部智慧財產局員工消费合作社印製 6 2 1 2 5 A7 __B7 五、發明說明（3 ) 半導體基體上並形成一連接電線連接至絕緣層中半導體元 件的電線層；形成導電材料的導電層，具有藉對齊連接電 線之成型而形成的開口，在至少一許多半導體基體的接面 表面上：平滑各半導體基體之接面表面；及從彼此放置的 半導體基體之兩側施加一壓縮負載，以相互連接半導體基 體及相互連接各半導體基體中所形成之連接電線。 依據本發明，電線電極與接地電極被提供在載有半導 體元件之各半導體基體上。絕緣層與作爲導電層之接地層 依此順序設置於各半導體基體之表面上。一開口被鑽口在 絕緣層及接地層中，且接地層電極與接地層經由充入開口 中的導電材料而彼此電氣連接。由多層形成的半導體基體 之表面被平面化及平滑化。兩個半導體基體之平面化表面 被放置成相向且彼此對齊。如此對齊的半導體基體藉施加 負載而彼此接合。 藉此技術，亦即形成一接地層於兩個基體之間，由半 導體基體上之各別元件所產生的輻射雜訊被接地層吸收， 而由相對側半導體基體上各元件所產生的輻射雜訊類似地 被接地層吸收，使得接地層可消除在半導體基體上之半導 體元件上的往復效果。由於共同的接地層被提供於兩個基 體之間，可經由開口而作用三維的接地連接，以減小接地 電線長度。 另一種方式，接地層與電源層，共同至兩個半導體基 體，被提供在兩個半導體基體之間。亦即，電線電極、接 地電極與電源電極被提供在載有半導體元件之半導體基體 本紙張尺度適用中0國家標準（CNS)A4規格（210 X 297公* ) --------------裝--------訂---------線 (锖先Μ讀背面之注意事項再资寫本頁) -6 - A7 B7 五'發明說明（4 ) (請先閱讀背面之注意事項再莩寫本頁) 上 ' 絕緣層、接地層與絕緣層依序形成在半導體基體之表 面上’且開口形成在絕緣層、接地層與絕緣層中。導電構 件放置於開口中。接地層被電氣連接至接地電極。其中一 個開口中的導電構件被連接至電源電極，而其餘開口中的 導電構件被連接至電線電極。接地電線層、電源電線層與 通孔電線被一絕緣體電氣絕緣，接著被表面拋光= 在載有半導體元件之相對側半導體基體上，提供一電 線電極、一接地電極及一電源電極，而一絕緣層與一電源 層依序形成在基體表面上。形成開口在絕緣層與電源層中 ’且導電構件放置於開口中。接地層被電氣連接至接地電 極。其中一個開口中的導電構件被電氣連接至電源電線， 而其餘開口中的導電構件被連接至電線電極。接地電線層 、電源電線層與通孔電線被一絕緣體電氣絕緣，接著被表 面拋光。兩個基體以彼此面向且對齊的方式放置，使得電 線層、接地層與電源電線彼此對齊，且從基體的兩個施加 負載。 經濟部智慧財產局員工消f合作社印製 由於用於接地之接地層及作爲兩個基體的各別元件之 電源的電源層被提供於基體之間，可有效地減小電線長度 ，而可藉接地層來吸收由其中一個半導體基體所產生的_ 射雜訊。 本發明於是提供一種配置，其中接地層與電源層被夾 在兩個基體之間，當基體被接合在一起。於是，提供機構 用於減小電線且禁止來自兩個基體之輻射雜訊的往復干擾 本紙張尺度適用中囲S家標準（CNS)A4規格<210 X 297公釐） -7- 462125 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（5 ) 依據如上所述之本發明，由於導電層（接地層）被提 供在各載有半導體元件的第一與第二基體之間，來自第一 基體上的半導體元件之輻射雜訊可被遮蔽，而不會影響第 二基體上的半導體元件。而且，第一與第二基體之間的信 號傳輸，可藉著提供在夾於第一與第二基體之間的接地層 中之連接電線（通孔電線）而實現。 如果作爲用電源層之導體層，被提供在平行於導體層 延伸的各第一與第二基體上，操作爲一接地層，這些導體 層可作用爲經過通孔之第一與第二基體的電源，於是改善 效率。 而且，在依據本發明的製造方法中，來自分開的處理 ，載有半導體元件之第一與第二基體，藉固態接合技術被 接合在一起》於是，包含具有不同功能的半導體基體之多 層基體可被簡單地製造，於是確保有效率的製造。 圖形之簡要敘述： 圖1是一剖面圖，指出依據本發明的半導體裝置之實 施例，且特別地指出在統一連接之前的狀態。 圖2是一剖面圖，指出圖1之半導體裝置連接與統一 的狀態。 圖3是一剖面圖，指出依據本發明的半導體裝置之另 一個實施例，且特別地指出在統一連接之前的狀態。 圖4是一剖面圖|指出圖3之半導體裝置連接與統一 的狀態。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----1!!_ 裝 ------- 訂·! •線 (請先閲讀背面之注意事項再壎寫本頁) -8- 462125 A7 B7五、發明說明（ό ) 圖5是一剖面圖，指出依據本發明的半導體裝置之另 外一個實施例，且特別地指出在統一連接之前的狀態。 圖6是一剖面圖，指出圖5之半導體裝置連接與統一 的狀態。 圖7是一圖形，指出對一外部驅動電路的連接構造。 圖8是一圖形，指出對一外部驅動電路的另一連接構 造。 圖9 A至9 G是剖面圖，一步步地指出固態接合之製 造處理。 圖1 0A至10 I是剖面圖，一步步地指出固態接合 之另一製造處理。 圖1 1是一圖形，指出作爲應用的平坦面板電腦。 圖1 2是一圖形，指出藉晶片上晶片（chip-on-chip ) ，相互連接不同規格之L S I的系統L S I相互連接處理 — — ill.------裝---II---訂 --------線 (請先閱讀背面之注項再婕寫本頁) 經濟部智慧財產局員工消费合作社印製 主要元件符號說明： 1 半導體基體 2 半導體基體 3 電線層 4 電線層 5 連接電線 6 連接電線 7 絕緣層 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公|ί ) -9- 經濟部智慧財產局員工消費合作社印製 6212 5 五、發明說明（7 ) 8 絕緣 層 9 接地 電 線 層 1 0 接 地 電 線 層 1 1 絕 緣 層 1 2 絕 緣 材 料 1 3 絕 緣 材 料 1 4 通 孔 1 5 通 孔 1 6 通 孔 1 7 通 孔 1 8 通 孔 1 9 通 孔 2 0 電 源 電 線 層 2 1 第 一 半 導 體基體 21a 矽基底 2 1b 蝕刻停止層 21c 裝置層 22 第二半導體基體 31 虛擬基體 較佳實施例之敘述： 參見圖形，將詳細說明依據本發明之半導體裝置的構 造與其製造方法之較佳實施例。 圖1與2指出實施本發明之半導體裝置的特徵。在本 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --^--J- — I ----i I --------訂-----1 (請先閱讀背面之注意事項再ir寫本頁) -10- 經濟部智慧財產局員工消費合作社印製 4 6 2 12 5 A7 _____B7 五、發明說明（8 ) 實施例中’一對各載有半導體元件之半導體基體1，2被 彼此連接。 在基體1 ，2上形成電線層3，4，分別作爲半導體 元件相互連接。在這裡稱爲通孔的開口中，擺設稱爲通孔 電線之連接電線5，6 °通孔電線5，6亦稱爲插頭，經 由擺設於孔中的導電構件而非所謂的通孔電線，可確保電 氣連接。 在基體1 ’ 2上設置絕緣層7，8。通孔電線5，6 是藉著充電分別形成於這些絕緣層7，8中的通孔1 4， 1 5中的導電材料而形成的。 在絕緣層7，8上設置接地電線層9，1 0，分別由 導電金屬材料做成。 接地電線層9，1 0各做成連續不間斷的圖案，除了 分別連接至形成於絕緣層7，8中的通孔1 4 * 1 5之通 孔1 6 ’ 1 7被鑽成大致分別對齊通孔電線5，6 同時，通孔16，17之直徑稍大於通孔14 , 15 ’以相對於通孔7，8形成間隙°在此間隙中嵌入絕緣材 料12 ’ 13以確保接地電線層9，10與通孔電線5， 6之間的絕緣。所以’通孔1 6，1 7之尺寸最好做成不 引起絕緣材料1 2，1 3之介電崩潰，此絕緣材料1 2， 1 3嵌入於接地電線層9，1 0與通孔電線5，6之間的 間隙中。 在上述造形中，通孔1 4首先藉著光石印處理、薄膜 形成處理與去除處理被鑽孔於基體中。在通孔1 4中形成 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） — I-裝 ------ - 訂 ----I ---線 (請先閱讀背面之注意事項再璩寫本頁) -11 - 經濟部智慧財產局員工消費合作社印製 6212 5 A7 -------B7 _ 五、發明說明（9 ) 通孔電線5 ’如圖1所示用光石印處理與去除處理.然後 具有通孔16之接地電線層9形成於絕緣層7上，且通孔 電線5亦形成於通孔16中。 然後絕緣材料12形成於接地電線層9與通孔電線5 之間，接著表面拋光。 在基體2上，類似地形成絕緣層8、接地電線層1 0 '通孔1 5、絕緣材料1 3與通孔電線6，接著表面拋光 基體1 ，2被放置成彼此對齊，使得接地電線層9， 1 〇彼此面對。然後從基體1 ，2的兩側放置負載。 藉著放置的負載，基體1 ，2彼此連接，通孔電線5 ’ 6與接地電線層9，10彼此接合。在連接之後，確保 通孔電線5，6之間與接地電線層9，1 0之間的電氣連 接。同時，接地電線層9，10分別被電氣連接至基體1 之未示的接地電極，且電氣連接至基體2之未示的接地電 極。 在本實施例中，矽氧化物膜被使用作爲絕緣層7，8 ，而銅被使用作爲接地電線層9，10與通孔電線5，6 。而且，矽氧化物膜被使用作爲絕緣材料1 2，1 3。亦 可使用鋁氧化物膜或矽氮化物，用於絕緣層7，8及用於 絕緣材料1且可使用金或錯用於接地電線層9 ，1 0及用 於通孔電線5，6。 圖3與4指出一造形，其中接地電線層只形成於各載 有半導體元件之成對的基體1，2之基體1上。 本紙張尺度適用中國國家標準（CNS〉A4規格（210 X 297公釐） 11--- - - - - - --- - ^ illl — Ι— — — — m — (請先閱讀背面之注意事項再€κ本頁) -12- 4 經濟部智慧財產局員工消費合作社印製 6 2 12 5 A7 ______B7 五、發明說明) 在基體1 ，2上形成電線層3，4作爲半導體裝置之 相互連接。形成於通孔中的通孔電線5，6分別被電氣連 接至這些電線層3，4，如同先前的實施例。 在基體1與2上分別形成絕緣層7，8。藉著充電分 別形成於這些絕緣層7，8中的通孔1 4，1 5中之導電 材料’而形成通孔電線5，6 = 只在基體1上，藉著在絕緣層7上做成一層，形成例 如由導電金屬材料做成的接地電線層9。接地電線層9大 致做成連續的圖案，除了連接至形成於絕緣層7中的通孔 1 4之開口（通孔）1 6，被鑽孔成與通孔電線5對齊。 同時，形成通孔1 6稍大於通孔1 4。絕緣材料1 2 埋藏於通孔電線5與通孔1 6的外周之間的間隙中，以確 保接地電線層9與通孔電線5之間的絕緣。 在上述造形中，首先通孔1 4形成於基體1中，使用 光石印處理、薄膜形成處理與去除處理。然後通孔電線5 形成於通孔1 4中’如圖3所示使用光石印處理與去除處 理。然後在絕緣層7上，形成具有通孔1 6之接地電線層 9，其中亦形成通孔電線5 = 在接地電線層9與通孔電線5之間形成絕緣材料，接 著表面拋光。 絕緣層8、通孔1 5與通孔電線6被類似地形成，接 著表面拋光。 所製成的基體1 ’ 2被放置成彼此對齊，使得接地電 線層9與絕緣層8將彼此面對，且從基體1 ，2的兩側放 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） — II--: — 丨 — — ------I 11111 訂 *lllf 111 · *5^ (請先《讀背面之注意事項再壎寫本頁) -13- 4 6212 5 A7 -- -B7__ 五、發明說明（11 ) 置一負載。 藉著放置的負載，基體1 ，2彼此連接，通孔電線5 ’ 6與接地電線層9，10彼此接合。在連接之後，確保 通孔電線5，6之間的電氣連接。同時，接地電線層9被 電氣連接至基體1之未示的接地電極。 在本實施例中，矽氧化物膜、銅、矽氧化物膜與銅分 別被使用作爲絕緣層7，8、接地電線層9、通孔電線5 ’ 6與絕緣材料1 2。亦可使用鋁氧化物膜及矽氮化物用 於絕緣層7，8及用於絕緣材料1 2，且可使用金或鋁用 於接地電極層9及_用於通孔電線5，6 » 圖5與6指出一造形，其中一電源電線層形成於載有 半導體元件之成對的基體1，2之基體1上，且其中接地 電線層形成於相對側基體2上。 在基體1，2上形成電線層3，4分別作爲半導體裝 置之相互連接。形成於通孔1 4，1 5中的通孔電線5， 6分別被電氣連接至這些電線層3，4，如同先前的實施 例。 在基體1與2上放置絕緣層7，8。藉著充電分別形 成於這些絕緣層7，8中的通孔1 4，1 5中之導電材料 ，而形成通孔電線5，6。 只在基體2上，藉著在絕緣層8上做成一層’形成例 如由導電金屬材料做成的接地電線層1 0 « 接地電線層1 0大致做成連續的圖案，除了連接至形 成於絕緣層8中的通孔1 5之開口（通孔）1 7 ’形成與 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） !-'11!11 48^ I I ! 11 I 訂 11 ! I I — - <請先閱讀背面之注意事項再f本頁) 經濟部智慧財產局員工消费合作社印製 -14- 12 5 A7 B7 五、發明說明（〗2 ) 通孔電線6對齊。 同時，形成通孔17稍大於通孔15。絕緣材料13 埋藏於通孔電線6與通孔1 7的外周之間的間隙中，以確 保接地電線層1 0與通孔電線6之間的絕緣。 至於相對側基體1 ，絕緣層被做成多層’且〜電源電 線層2 0被擺設於絕緣層7，1 1之間。 — 在電源電線層2 0與絕緣層1 1中’分別形成通孔 18，19。通孔電線5通過這些通孔18 ’ 19。絕緣 材料1 2被嵌入於間隙中，以確保電源電線層2 0與通孔 電線5之間的電氣絕緣。 在上述造形中，首先通孔1 4形成於基體1中，使用 光石印處理、薄膜形成處理與去除處理。然後通孔電線5 形成於通孔1 4中，如圖5所示使用光石印處理與去除處 理。然後在絕緣層7上，形成具有通孔1 8之電源電線層 2 0，及具有通孔1 9之絕緣層1 1。在通孔1 8，. 1 9 中，亦形成通孔電線5。 在電源電線層2 0與通孔電線5之間形成絕緣材料 1 2，接著表面拋光。 絕緣層8、通孔1 5與通孔電線6被類似地形成，接 著表面抛光。 所製成的基體1 ，2被放置成彼此對齊，使得接地電 線層1 0與絕緣層1 1將彼此面對，且從基體1，2的兩 側放置一負載。 藉著放置的負載，基體1，2彼此連接，通孔電線5 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 請 先 閲 讀 背 面 之 注 意 事 項 再 4 · I裝 頁 訂 經濟部智慧財產局貝工消t合作社印製 -15- 經濟部智慧財產局員工消費合作社印製 462125 A7 -—-__B7 五、發明說明（13 ) ’ 6彼此接合，且絕緣層1 1與接地電線層1 〇亦類似地 彼此接合。 在上述各造形中，可使用例行地使用於半導體裝置中 用於連接至一外部驅動電路之適當的方法。 例如’在指出包含半導體晶片A與半導體晶片B結合 在一起的半導體裝置的圖7中，滿足半導體晶片卢之外尺 寸4S定爲大於半導體晶片b之外尺寸，且連接電線w被電 線接合至暴露在半導體晶片A之接面表面的連接墊P。須 注意圖7所示之半導體裝置之構造表示於圖2，4與6中 ’且半導體晶片A.與B各包含半導體基體，如上所述其上 形成絕緣層與可變的電線層。 另一種方式，半導體晶片A與B可以是相同尺寸*且 連接電線W可被接合至形成在半導體晶片B之背側上的連 接墊P。在此情形中，墊P需經一通孔電線被電氣地連接 至半導體晶片B之預置電線層，或電氣地連接至暴露於半 導體晶片A之接面表面的電線層。 以下說明上述構造的半導體裝置之製造方法。 製造方法利用固態接合。所使用的處理舉例爲圖9所 示之處理及圖1 0所示之處理= 圖9指出藉不均勻裝置基體之固態接合的製造方法。 在此製造方法中，例如SO I基體之第一半導體基體2 1 被製備爲如圖9 A所示。 藉著在矽基底2 1 a上形成一蝕刻停止層2 1 b與裝 置層21c而做成此半導體基體21。裝置層21c被蝕 本紙張尺度適用中國國家標準<CNS)A4規格（210 X 297公釐） I ^---T —-------裝·----— I I 訂---— III — <請先《讀背面之注意事項再坩寫本頁) -16- 462125 A7 B7 經濟部智慧財產局員工消费合作社印製 五、發明說明（Μ ) 刻成如圖9 B所示的半導體晶片。 然後，例如載有電線之電線基體或不均勻裝置基體之 半導體基體，藉固態接合被接合在裝置層2 1 c上，如圖 9 C所示。 固態接合利用一現象，其中如果兩個晶圓表面彼此靠 近，穩定的陣列凹陷以產原子間吸力，且其中如果到達某 v 一距離，吸力等於在塊狀中之吸力最後導致接合。固態接 合具有一優點，不需要使用黏著劑或加熱。 在金屬之情形藉由氧化，或藉由有機材料之吸收，實 際固體材料的表面被穩定化。於是，單純的接觸不足以產 生連接。然而，如果藉例如氬原子之惰性原子來移除穩定 的表面層以暴露不穩定且活性的表面，可以實現完全符合 接合之原理的固態接合。 所以，在上述固態接合中，平滑接面表面與表面活性 化是不可缺少的。 圖9 D指出一狀態，其中第二半導體基體2 2被接合 至第一半導體基體2 1。第一半導體基體2 1之矽基底 2 1 a被蝕刻掉，如圖9 E所示。然後蝕刻停止層2 1 b 被蝕刻掉如圖9 F所示1以完成三維積體電路。 最後，三維積體電路被切割而做成半導體晶片，形成 預定尺寸之半導體裝置。 圖1 0指出使用虛擬基體之方法。此方法是與圖9之 處理相同，直到裝置層21c之蝕刻（圖10B)。 在此方法中’裝置層2 1 c是藉由蝕刻而形成’且一 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） — — — — PI — — — — ——^aJ1— — — — —— — — (請先閲讀背面之注f項再埔寫本頁) -17- 經濟部智慧財產局員工消費合作社印製 ^6212 5 at ___ B7 五、發明說明（15 ) 虛擬基體3 1放置於其上且接合於位置中（圖1 〇 C至 10D)。第一半導體基體2 1上之矽基底2 la被蝕刻 掉（圖10E)。然後蝕刻停止層21b被蝕刻掉，如圖 1 0 F所示。 以此方式’只有裝置層2 1 c留在虛擬基體上。然後 所得到的組件以固態接合被接合在第二半導體基體2 2上 ’例如一電線基體或一不均勻裝置基體。藉此步驟，裝置 層2 1 c被形成在第二半導體基體2 2上。 最後，虛擬基體3 1被剝落，如圖1 Ο Η所示，且在 虛線的位置被切割’以完成如圖10I示的三維積體電路 〇 前述是一粗略的製造方法。以下說明製造具有接地電 線層之半導體裝置的製造方法。 製造方法的特例1 在本實施例中，兩個各載有半導體元件之半導體基體 ，藉以下處理步驟彼此連接： (1 ) 一步驟’事先提供一電線電極於第一半導體基體上 y (2 ) —步驟，依序放置一絕緣層與一接地層於第一基體 上，且鑽出通孔，此通孔連接至絕緣層與接地層中之電線 電極； (3 )—步驟，在通孔中形成一通孔電線，用於電氣連接 至電線電極； 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） — — — — — — — ^ — — — — — — —--^ I, {請先閱讀背面之沒意事項再硪寫本頁) -18- ^62125 A7 B7 五 、發明說明（16 (4 ) 之間， 一步驟 形成一 —步驟 一步驟 ，在接地層與接地層中的通孔中之通孔電線 絕緣體； ，平滑第一基體的主要表面； T事先取出第二半導體基體上之電線電極； (7 ) 體基體 之電線 (8 ) 電氣連 (9 ) 之間， (10 (11 與第二 (12 (13 地層。 一步驟，依序放置一絕緣層與一接地層於第二半導 上’且形成通孔，此通孔連接至絕緣層與/接地層中 電極； 一步驟，形成通孔中之通孔電線，用於電線電極之 接； —步驟，在接地層與接地層中的通孔中之通孔電線 形成一絕緣體； )一步驟，平滑第二半導體基體之表面； )一步驟，放置第一與第二半導體基體，使得第一 半導體基體之接地層與通孔電線彼此面對； )從基體之兩側施加壓縮負載；及 )在壓縮負載下電氣地且機械地連接通孔電線與接 — — — — — — *1111111 — I <請先閱讀背面之注意事項Λν-填寫本頁> 經濟部智慧財產局員工消費合作社印繫 製造方法的特例2 在本實施例中，兩個各載有半導體元件之半導體基體 ，藉以下處理步驟彼此連接： (1 ) 一步驟，事先提供一電線電極於第一半導體基體上 f (2 ) —步驟，依序放置一絕緣層與一接地層於第一基體 本紙張尺度適用t國國家標準（CNS)A4規格（210 X 297公i ) -19- Λα 經濟部智慧財產局貝工消费合作社印製 6212 5 A7 ____B7 五、發明說明（17 ) 上，且鑽出通孔，此通孔連接至絕緣層與接地層中之電線 電極； (3 ) —步驟，在通孔中形成一通孔電線，用於電氣連接 至電線電極： (4 )—步驟，在接地層與接地層中的通孔中之通孔電線 之間，形成一絕緣體； (5 ) —步驟，平滑第一基體的主要表面； (6 ) —步驟，事先提供第二半導體基體上之電線電極； (7 ) —步驟，放置一絕緣層於第二半導體基體上，且形 成通孔，此通孔連接至絕緣層中之電線電極； (8 ) —步驟，形成通孔中之通孔電線，用於電氣連接至 電線電極： (9 ) 一步驟，平滑第二半導體基體之表面： (1 0 ) —步驟，放置第一與第二半導體基體，使得第一 與第二半導體基體之通孔電線彼此面對，且使得第一基體 之接地層將面向第二基體之絕緣層； (1 1 )從兩個基體之兩側施加壓縮負載；及 (1 2 )在壓縮負載下，電氣地連接通孔電線在一起，且 彼此機械地連接第一基體的絕緣層與第二基體的絕緣層。 製造方法的特例3 在本實施例中，兩個各載有半導體元件之半導體基體 ，藉以下處理步驟彼此連接： (1 ) 一步驟，事先取出第一半導體基體上之電線電極； 本紙張尺度適用中國國家標準（CNS)A4規格（210 * 297公釐） — — — — ^ — — — 1 — — — — i I 111 — I ^ ·1111111 — <請先閱讀背面之注意事項寫本買) -20- 4 62 1 2 5 經濟部智慧財產局員工消费合作社印製 A7 B7 五、發明說明（ΐδ ) (2 ) —步驟，依序放置一絕緣層、—接地層與另一絕緣 層於第一基體上，且鑽出通孔，此通孔連接至絕緣層、接 地層與另—絕緣層中之電線電極； (3 ) ~步驟，在通孔中形成一通孔電線，用於電氣連接 至電線電極； (4 ) ~步驟，在接地層與接地層中的通孔中之通孔電線 之間，形成一絕緣體； (5 ) —步驟，平滑第一基體的主要表面： (6 ) ~步驟，事先取出第二半導體基體上之電線電極； (7 ) —步驟，依序放置一絕緣層與一電源層於第二半導 體基體上，且形成通孔，此通孔連接至絕緣層與電源層中 之電線電極； (8 ) —步驟，在通孔中形成通孔電線，用於電氣連接至 電線電極； (9 ) 一步驟，在電源層與電源層中的通孔電線之間，形 成一絕緣體； (1 0 )平滑第二半導體基體之表面； (1 1 ) 一步驟，放置第一與第二半導體基體彼此對齊， 使得第一與第二半導體基體中之通孔電線彼此面對，且第 一與第二半導體基體之絕緣層與電源層彼此面對： (1 2 )從基體之兩側施加壓縮負載；及 (1 3 )在壓縮負載下，電氣地連接通孔電線，且機械地 連接絕緣層與電源層。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐〉 - ----;1!!11裝！| 訂-！ !1!線 (請先Μ讀背面之注意事項再填寫本頁> -21 - 4 62 彳 2 5 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（19 ) 製造方法的特例4 在本實施例中，兩個各載有半導體元件之半導體基體 ，藉以下處理步驟彼此連接： (1 ) 一步驟，取出第一基體上之電線電極與接地電極： (2 )依序放置一絕緣層與一接地層於第一基體上，且形 成通孔 '此通孔連接至絕緣層中之接地電極； (3 )在通孔中形成一通孔接地電線，電氣連接至接地電 極； (4)平滑第一基體的表面； (5 )事先取出第二半導體基體上之接地電極； (6 )依序放置一絕緣層與一接地層於第二半導體基體上 ，且形成通孔，此通孔連接至絕緣層中之接地電極； (7 )在通孔中形成通孔接地電線，電氣地連接至接地電 極； (8 )平滑另一半導體基體之表面： (9 )放置第一與第二半導體基體彼此對齊，使得第一與 第二半導體基體之接地層彼此面對： (1 0 )從基體之兩側施加壓縮負載：及 (1 1 )在壓縮負載下電氣地且機械地連接接地層。 製造方法的特例5 在本實施例中，兩個各載有半導體元件之半導體基體 ，藉以下處理步驟彼此連接： (1 )—步驟，事先取出第一半導體基體上之接地電極； 本紙張尺度適用中國Β家標準（CNS)A4規格（210 X 297公釐〉 11 I I ( I ! — ！ SilJ * I I ! ! t ·! — 11! *^^ (請先閱讀背面之注意Ϋ項再壙寫本頁) -22- 經濟部智慧財產局具工消費合作社印製 62125 A7 __B7 五、發明說明（20 ) (2 ) —步驟，依序放置一絕緣層與一接地層於第一基體 上，且鑽出通孔，此通孔連接至絕緣層中之接地電極： (3 ) —步驟，在通孔中形成一通孔接地電線，用於電氣 連接至接地電極； (4 ) 一步驟，平滑第一基體的表面； (5 )—步驟，事先取出第二半導體基體上之接_地電極； (6 ) —步驟，在第二基體上形成一絕緣層，且形成通孔 ，此通孔連接至絕緣層中之接地電極； (7 )—步驟，在通孔中形成通孔接地電線，電氣連接至 接地電極； (8 ) —步驟，平滑第二半導體基體之表面； (9放置第一與第二半導體基體，使得第一與第二半導體 基體之接地層與通孔接地電線彼此面對： (1 0 )從基體之兩側施加壓縮負載；及 (1 1 )在壓縮負載下電氣地連接接地層與通孔接地電線 ，且機械地連接第一基體之接地層與第二基體之絕緣層。 製造方法的特例6 在本實施例中，兩個各載有半導體元件之半導體基體 ，藉以下處理步驟彼此連接： (1 ) 一步驟，事先取出第一半導體基體上之接地電極； (2 ) —步驟，依序放置一絕緣層與一接地層於第一基體 上，且鑽出通孔，此通孔連接至絕緣層中之接地電極： (3 ) —步驟，在通孔中形成一通孔接地電線，用於電氣 本紙張尺度適用中國國家標準（CNS>A4規格（210 X 297公釐） --------------裝-----— II 訂--------線 (請先閱讀背面之注意事項*趄寫本頁) -23- A7 4621 25 B7_ 五、發明說明（21 ) 連接至接地電極； (4 ) 一步驟，平滑第一基體的表面： (5 ) —步驟，放置另一絕緣層於接地層上： (6 )平滑第一基體之表面： (7 )取出第二半導體基體上之電源電極； (8 )放置一絕緣層於第二半導體基體上，且形成通孔， 此通孔連接至絕緣層中之電源電極； (9 ) 一步驟，在通孔中形成通孔電源電線，用於電氣連 接至電源電極； (1 0 ) —步驟，·平滑第二半導體基體之表面； (1 1 )放置一電源層，用於電氣連接至第二半導體基體 上之通孔電源電線； (1 2 )放置第一與第二半導體基體彼此對齊，使得第一 與第二半導體基體之絕緣層與電源層彼此面對： (1 3 )從基體之兩側施加壓縮負載；及 (1 4 )在壓縮負載下機械地連接絕緣層與電源層。 製造方法的特例7 在本實施例中，兩個各載有半導體元件之半導體基體 ，藉以下處理步驟彼此連接： (1 )事先取出第一半導體基體上之電線電極、接地電極 與電源電極； (2 )依序放置一絕緣層 ' —接地層與另一絕緣層於第一 基體上，且形成通孔，此通孔連接至絕緣層、接地層與另 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） — — — — — — — — — —---裝------ 訂-！I!-線 (請先《讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 -24- 經濟部智慧財產局員工消費合作社印製 Α7 Β7__ 五、發明說明（22 ) 一絕緣層中之電源電極； (3 )在通孔中形成一通孔電源電線，用於電氣連接至電 源電極； (4 )—步驟，在通孔電源電線與絕緣層、接地層及另一 絕緣層中的通孔之周壁之間，形成一絕緣體； (5)—步驟，平滑第一基體的表面； — (6 ) —步驟，取出第二半導體基體上之電源電極； (7 )依序放置一絕緣層與一接地層於第二半導體基體上 ，且形成通孔，此通孔連接至絕緣層與電源層中之電源電 極； (8 )在該通孔中形成通孔電源電線，電氣連接至電源電 極； (9 ) 一步驟，平滑第二半導體基體之表面； (1 0 ) —步驟，放置第一與第二半導體基體彼此對齊， 使得第一與第二半導體基體上之通孔電源電線彼此面對， 且使得第一與第二半導體基體上之絕緣層與電源層彼此面 對； (1 1 )從兩個基體之兩側施加壓縮負載；及 (1 2 )在壓縮負載下電氣地連接通孔電源電線’且機械 地連接絕緣層與電源層。 製造方法的特例8 在特例1的製造方法中’與取出電線之步驟平行，執 行以下步驟： 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公笼） 丨^---------|_裝------訂--------線 (請先閲讀背面之注意事項再填寫本買) -25- 經濟部智慧財產局員工消費合作社印製 4 6 2 1 2 5 A7 ___B7___ 五、發明說明（23 ) (1 ) 一步驟，事先取出第一半導體基體上之接地電極： (2 ) —步驟，放置一絕緣層於第一基體上，且形成通孔 ’此通孔連接至絕緣層中之接地電極； (3 ) —步驟，在通孔中形成一通孔接地電線，電氣地連 接接地電極； (4 ) 一步驟，形成一接地層*電氣地連接至絕緣層上之 通孔接地電線： (5 ) —步驟，平滑其中一個基體的表面； (6 ) —步驟，事先取出第二半導體基體上之接地電極； (7 )—步驟，放置一絕緣層於第二半導體基體上，且形 成通孔，此通孔連接至絕緣層中之接地電極； (8 )形成通孔接地電線，電氣地連接至第二基體中之通 孔中的接地電極； (9 )形成一接地層，電氣地連接至絕緣層上的通孔接地 電線。 雖然以上已說明製造方法的某些特定例子，應注意這 些特例只是用於說明，在本發明之範圍內可做成許多不同 的修改。 現在說明本發明之應用的一個例子。 使用本發明之半導體裝置，可實現高度集積的三維積 體電路，其可用於達成以下優點： a )電線層與裝置層被擺設成兩個分開的層，以藉著電線 層的分開而實現產量的提昇； b )由於藉多層結合在一起而實現裝置層，實現類比/數 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） IT"-------I I ^ — — — — — —---111^. (請先閲讀背面之注意事項再域寫本頁) -26- 經濟部智慧財產局員工消费合作社印製 62125 A7 ____B7_ 五、發明說明（24 ) 位分開及導致加速； C )由於放置兩個裝置層，可實現類比/數位分開及導致 高操作速度； d )由於光學裝置元件被接合至一矽基體，一光學裝置可 被安裝至一電子基體； e )藉著接合至半導體基體，可實現化合物基體/ 藉固態接合之半導體裝置的造形可被球形地分類1視 做成使用晶圓印模（晶片）接合之型式的連接造形，與做 成使用晶圓對晶圓接合之型式的連接造形而定。 前者之例子爲例如圖1 1所示之平坦面板電腦。 在此平坦面板電腦中，負載在印刷電路板上之可變 L S I被直接接合至玻璃基體，以平坦面板本身作爲一可 攜式電腦。 在圖1 1所示的實施例中，顯示單元42、CPU 43、記憶體（RAM) 44、記憶體（ROM) 45與 輸入/輸出L S I 4 6直接被接合至一玻璃基體4 1。 圖1 2指出藉晶片上晶片方式接合l S I之例子， L S I晶片5 2被分開地接合在一晶圓5 1上。本實施例 指出一藉L S I之系統L S I實施技術。以本例子，不需 要置於中間的基體’使得可改善性能，藉著不使用L S I 上之緩衝器。 後者之例子爲晶圓位準的三維多層裝置，電線層接合 L S I ’取得在接合電線層部份上，藉系統l s I而相互 連接功能區塊（SOC) ’接合封裝部份在晶圓位準上的 本紙張尺度適用中國國家標準（CNS>A4規格（210 X 297公釐） II - - — — — — 1— ιί — ·1111111 ·1111!111 (請先閱讀背面之注意ί項再螻寫本頁) -27- 462125 A7 _B7 五、發明說明（25 ) L S I上之構造，及新穎高密度模組基體，能減小基體與 L S I之間的間隙。 在此兩種情形中，可實現高功能的L S I ，使得可實 .現三維積體電路，超過平面細微技術的臨界。 -----Ί 1------裝---ill 訂---I!-線 (請先閲讀背面之注意事項再壤寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -28-

Claims (1)

  1. 4 6 2 1 2 5 A8 BS C8 D8 六、申請專利範圍 i 、一種半導體裝置，各載有半導體元件之許多半導 體基體被接合在一起，其中： ---------等 (請先閲讀背面之注意事項再填声 一絕緣層被放置在各半導體基體上，形成一連接電線 通過該絕緣層，用於連接至該半導體元件上之電線層；且 其中： 由導電材料製成的導電層'藉著與該連接電線對齊而 成型以具有一開口，被形成在至少一個半導體基體之接面 表面上； 該半導體基體被接合在一起，以相互連接在各半導體 基體上所形成之連接電線。 訂 2、 如申請專利範圍第1項之半導體裝置，其中： 該半導體基體藉固態接合技術被接合在一起。 3、 如申請專利範圍第1項之半導體裝置，其中： 一導電層形成在欲被接合在一起的成對半導體基體之 接面表面上，且其中： 線 金屬材料構成被接合在一起之這些導電層。 經濟部智慧財產局R工消費合作社印製 4、 如申請專利範圍第1項之半導體裝置，其中： 一導電層形成於欲被接合在一起的成對半導體基體的 其中之一之接面表面上，且其中： 被接合在一起之相對側半導體基體是導電層與絕緣層 0 5、 如申請專利範圍第4項之半導體裝置，其中： 導電層放置於兩個絕綠層之間。 6、 如申請專利範圍第1項之半導體裝置，其中： 本紙張尺度逋用中國國家標準（CNS ) A4規格（210X297公釐） -29- 經濟部智慧財產局員工消費合作社印製 Α8 B8 C8 D8 々、申請專利範圍 該導電層操作爲一接地層。 7、 如申請專利範圍第1項之半導體裝置，其中： 該導電層操作爲一電源層= 8、 如申請專利範圍第1項之半導體裝置，其中： 該導電層被電氣地連接至半導體元件。 9、 如申請專利範圍第1項之半導體裝置\其中： 形成於該導電層中的開口之內直徑大於形成在該絕緣 層中的開口之內直徑。 1 〇、如申請專利範圍第9項之半導體裝置'，其中： 接面表面上彼此連接的連接電線與導電層絕緣，藉著 將絕緣材料嵌入於該導電層中的開口中。 1 1 ' 一種製造半導體裝置之方法，在此半導體裝置 中各載有半導體元件之許多半導體基體被接合在一起，此 方法包含以下步驟： 放置一絕緣層於一半導體基體上，且形成一連接電線 ，連接至該絕緣層中之半導體元件的電線層； 形成導電材料製成的導電層，在許多半導體基體的至 少其中之一之接面表面上具有一開口，藉對齊該連接電線 之成型而形成； 平滑各半導體基體之接面表面；及 從彼此放置的半導體基體之兩側施加一壓縮負載，以 相互連接半導體基體及相互連接形成於各半導體基體中的 連接電線。 本紙張尺度適用中國國家揉率（CNS ) A4規格（210X297公釐） ---------^------1T------0 (請先閱讀背面之注意事項再填¢.,¾ ) -30-
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102544034A (zh) * 2010-10-27 2012-07-04 索尼公司 固态摄像器件和半导体器件及其制造方法以及电子装置

Families Citing this family (326)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2773261B1 (fr) 1997-12-30 2000-01-28 Commissariat Energie Atomique Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions
US6956348B2 (en) 2004-01-28 2005-10-18 Irobot Corporation Debris sensor for cleaning apparatus
JP3440057B2 (ja) * 2000-07-05 2003-08-25 唯知 須賀 半導体装置およびその製造方法
US7298031B1 (en) * 2000-08-09 2007-11-20 Micron Technology, Inc. Multiple substrate microelectronic devices and methods of manufacture
US6607937B1 (en) 2000-08-23 2003-08-19 Micron Technology, Inc. Stacked microelectronic dies and methods for stacking microelectronic dies
US6690134B1 (en) 2001-01-24 2004-02-10 Irobot Corporation Method and system for robot localization and confinement
US20020163072A1 (en) * 2001-05-01 2002-11-07 Subhash Gupta Method for bonding wafers to produce stacked integrated circuits
US7064447B2 (en) * 2001-08-10 2006-06-20 Micron Technology, Inc. Bond pad structure comprising multiple bond pads with metal overlap
JP4572054B2 (ja) * 2002-01-24 2010-10-27 寛治 大塚 回路構造及び半導体集積回路
US6864118B2 (en) * 2002-01-28 2005-03-08 Hewlett-Packard Development Company, L.P. Electronic devices containing organic semiconductor materials
TW542454U (en) * 2002-06-21 2003-07-11 Molex Inc Electrical connector
FR2848336B1 (fr) 2002-12-09 2005-10-28 Commissariat Energie Atomique Procede de realisation d'une structure contrainte destinee a etre dissociee
AU2003297542A1 (en) 2002-12-31 2004-07-29 Massachusetts Institute Of Technology Method of forming a multi-layer semiconductor structure incorporating a processing handle member
US7064055B2 (en) * 2002-12-31 2006-06-20 Massachusetts Institute Of Technology Method of forming a multi-layer semiconductor structure having a seamless bonding interface
JP3981026B2 (ja) * 2003-01-30 2007-09-26 株式会社東芝 多層配線層を有する半導体装置およびその製造方法
US6962835B2 (en) 2003-02-07 2005-11-08 Ziptronix, Inc. Method for room temperature metal direct bonding
US6803649B1 (en) * 2003-05-16 2004-10-12 Intel Corporation Electronic assembly
US7109092B2 (en) 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding
FR2856844B1 (fr) * 2003-06-24 2006-02-17 Commissariat Energie Atomique Circuit integre sur puce de hautes performances
JP2005123362A (ja) * 2003-10-16 2005-05-12 Hitachi Ltd 接続用取付基板及びディスクアレイ制御装置の接続用取付基板
FR2861497B1 (fr) 2003-10-28 2006-02-10 Soitec Silicon On Insulator Procede de transfert catastrophique d'une couche fine apres co-implantation
FR2864336B1 (fr) * 2003-12-23 2006-04-28 Commissariat Energie Atomique Procede de scellement de deux plaques avec formation d'un contact ohmique entre celles-ci
FR2869455B1 (fr) * 2004-04-27 2006-07-14 Soitec Silicon On Insulator Procede de fabrication de puces et support associe
FR2872627B1 (fr) * 2004-06-30 2006-08-18 Commissariat Energie Atomique Assemblage par adhesion moleculaire de deux substrats
DE102004037826B4 (de) * 2004-08-04 2006-06-14 Infineon Technologies Ag Halbleitervorrichtung mit miteinander verbundenen Halbleiterbauelementen
TWI246175B (en) * 2004-10-11 2005-12-21 Ind Tech Res Inst Bonding structure of device packaging
JP2006196668A (ja) * 2005-01-13 2006-07-27 Toshiba Corp 半導体装置及びその製造方法
US7620476B2 (en) 2005-02-18 2009-11-17 Irobot Corporation Autonomous surface cleaning robot for dry cleaning
JP4885211B2 (ja) 2005-05-18 2012-02-29 コロ テクノロジーズ インコーポレイテッド 微細電子機械変換器
CN101223633A (zh) * 2005-05-18 2008-07-16 科隆科技公司 穿过晶片的互连
WO2006134580A2 (en) * 2005-06-17 2006-12-21 Kolo Technologies, Inc. Micro-electro-mechanical transducer having an insulation extension
US7526739B2 (en) * 2005-07-26 2009-04-28 R3 Logic, Inc. Methods and systems for computer aided design of 3D integrated circuits
US7880565B2 (en) 2005-08-03 2011-02-01 Kolo Technologies, Inc. Micro-electro-mechanical transducer having a surface plate
US7485968B2 (en) 2005-08-11 2009-02-03 Ziptronix, Inc. 3D IC method and device
FR2889887B1 (fr) 2005-08-16 2007-11-09 Commissariat Energie Atomique Procede de report d'une couche mince sur un support
FR2891281B1 (fr) * 2005-09-28 2007-12-28 Commissariat Energie Atomique Procede de fabrication d'un element en couches minces.
US7528494B2 (en) * 2005-11-03 2009-05-05 International Business Machines Corporation Accessible chip stack and process of manufacturing thereof
WO2007056808A1 (en) * 2005-11-18 2007-05-24 Ewise Systems Pty Ltd A method and apparatus for facilitating a secure transaction
EP1953814B1 (en) * 2005-11-25 2017-09-06 Panasonic Intellectual Property Management Co., Ltd. Wafer level package structure and method for manufacturing same
TW200730826A (en) * 2005-11-25 2007-08-16 Matsushita Electric Works Ltd Sensor device and method for manufacturing same
EP1953817B1 (en) * 2005-11-25 2012-10-31 Panasonic Corporation Sensor device and method for manufacturing same
EP1953816A4 (en) 2005-11-25 2011-07-27 Panasonic Elec Works Co Ltd SENSOR ARRANGEMENT AND PROCESS FOR THEIR MANUFACTURE
US8067769B2 (en) 2005-11-25 2011-11-29 Panasonic Electric Works Co., Ltd. Wafer level package structure, and sensor device obtained from the same package structure
JP4682028B2 (ja) * 2005-11-28 2011-05-11 Ｈｏｙａ株式会社 導電層の製造方法、導電層、及び、信号伝送基板
JP2007311990A (ja) * 2006-05-17 2007-11-29 Pentax Corp 通信装置
US7446017B2 (en) * 2006-05-31 2008-11-04 Freescale Semiconductor, Inc. Methods and apparatus for RF shielding in vertically-integrated semiconductor devices
US8021981B2 (en) * 2006-08-30 2011-09-20 Micron Technology, Inc. Redistribution layers for microfeature workpieces, and associated systems and methods
US7829438B2 (en) * 2006-10-10 2010-11-09 Tessera, Inc. Edge connect wafer level stacking
US7901989B2 (en) * 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
US8513789B2 (en) 2006-10-10 2013-08-20 Tessera, Inc. Edge connect wafer level stacking with leads extending along edges
FR2910179B1 (fr) 2006-12-19 2009-03-13 Commissariat Energie Atomique PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART
US7952195B2 (en) * 2006-12-28 2011-05-31 Tessera, Inc. Stacked packages with bridging traces
US7827519B2 (en) * 2006-12-29 2010-11-02 Cadence Design Systems, Inc. Method, system, and computer program product for preparing multiple layers of semiconductor substrates for electronic designs
FR2913145B1 (fr) * 2007-02-22 2009-05-15 Stmicroelectronics Crolles Sas Assemblage de deux parties de circuit electronique integre
US7494846B2 (en) * 2007-03-09 2009-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. Design techniques for stacking identical memory dies
US7528492B2 (en) 2007-05-24 2009-05-05 Taiwan Semiconductor Manufacturing Company, Ltd. Test patterns for detecting misalignment of through-wafer vias
US8476735B2 (en) 2007-05-29 2013-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Programmable semiconductor interposer for electronic package and method of forming
US7939941B2 (en) * 2007-06-27 2011-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of through via before contact processing
JP5302522B2 (ja) * 2007-07-02 2013-10-02 スパンション エルエルシー 半導体装置及びその製造方法
US7825517B2 (en) 2007-07-16 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for packaging semiconductor dies having through-silicon vias
EP2186134A2 (en) 2007-07-27 2010-05-19 Tessera, Inc. Reconstituted wafer stack packaging with after-applied pad extensions
US8551815B2 (en) 2007-08-03 2013-10-08 Tessera, Inc. Stack packages using reconstituted wafers
US8043895B2 (en) * 2007-08-09 2011-10-25 Tessera, Inc. Method of fabricating stacked assembly including plurality of stacked microelectronic elements
US7973413B2 (en) 2007-08-24 2011-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate via for semiconductor device
US8044497B2 (en) * 2007-09-10 2011-10-25 Intel Corporation Stacked die package
US8350382B2 (en) * 2007-09-21 2013-01-08 Infineon Technologies Ag Semiconductor device including electronic component coupled to a backside of a chip
US8476769B2 (en) * 2007-10-17 2013-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon vias and methods for forming the same
US8227902B2 (en) * 2007-11-26 2012-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Structures for preventing cross-talk between through-silicon vias and integrated circuits
US7588993B2 (en) 2007-12-06 2009-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Alignment for backside illumination sensor
US7843064B2 (en) 2007-12-21 2010-11-30 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and process for the formation of TSVs
US8671476B2 (en) * 2008-02-05 2014-03-18 Standard Textile Co., Inc. Woven contoured bed sheet with elastomeric yarns
US8853830B2 (en) * 2008-05-14 2014-10-07 Taiwan Semiconductor Manufacturing Company, Ltd. System, structure, and method of manufacturing a semiconductor substrate stack
EP2308087B1 (en) * 2008-06-16 2020-08-12 Tessera, Inc. Stacking of wafer-level chip scale packages having edge contacts
WO2010013728A1 (ja) 2008-07-31 2010-02-04 日本電気株式会社 半導体装置及びその製造方法
US8288872B2 (en) 2008-08-05 2012-10-16 Taiwan Semiconductor Manufacturing Company, Ltd. Through silicon via layout
US8399273B2 (en) * 2008-08-18 2013-03-19 Tsmc Solid State Lighting Ltd. Light-emitting diode with current-spreading region
US20100062693A1 (en) * 2008-09-05 2010-03-11 Taiwan Semiconductor Manufacturing Co., Ltd. Two step method and apparatus for polishing metal and other films in semiconductor manufacturing
US8278152B2 (en) * 2008-09-08 2012-10-02 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding process for CMOS image sensor
US9524945B2 (en) 2010-05-18 2016-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with L-shaped non-metal sidewall protection structure
US8653648B2 (en) * 2008-10-03 2014-02-18 Taiwan Semiconductor Manufacturing Company, Ltd. Zigzag pattern for TSV copper adhesion
US7928534B2 (en) 2008-10-09 2011-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Bond pad connection to redistribution lines having tapered profiles
US8030780B2 (en) 2008-10-16 2011-10-04 Micron Technology, Inc. Semiconductor substrates with unitary vias and via terminals, and associated systems and methods
KR20100048610A (ko) 2008-10-31 2010-05-11 삼성전자주식회사 반도체 패키지 및 그 형성 방법
US8624360B2 (en) 2008-11-13 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Cooling channels in 3DIC stacks
DE102009007625A1 (de) * 2008-11-14 2010-05-20 Osram Opto Semiconductors Gmbh Verbundsubstrat für einen Halbleiterchip
US8158456B2 (en) * 2008-12-05 2012-04-17 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming stacked dies
US7989318B2 (en) 2008-12-08 2011-08-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for stacking semiconductor dies
US8513119B2 (en) 2008-12-10 2013-08-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming bump structure having tapered sidewalls for stacked dies
US8736050B2 (en) 2009-09-03 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. Front side copper post joint structure for temporary bond in TSV application
US7943428B2 (en) * 2008-12-24 2011-05-17 International Business Machines Corporation Bonded semiconductor substrate including a cooling mechanism
US8264077B2 (en) * 2008-12-29 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Backside metal of redistribution line with silicide layer on through-silicon via of semiconductor chips
US7910473B2 (en) * 2008-12-31 2011-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon via with air gap
US20100171197A1 (en) * 2009-01-05 2010-07-08 Hung-Pin Chang Isolation Structure for Stacked Dies
US8749027B2 (en) * 2009-01-07 2014-06-10 Taiwan Semiconductor Manufacturing Company, Ltd. Robust TSV structure
US8399354B2 (en) 2009-01-13 2013-03-19 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon via with low-K dielectric liner
US8501587B2 (en) 2009-01-13 2013-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked integrated chips and methods of fabrication thereof
US8314483B2 (en) 2009-01-26 2012-11-20 Taiwan Semiconductor Manufacturing Company, Ltd. On-chip heat spreader
US8168529B2 (en) * 2009-01-26 2012-05-01 Taiwan Semiconductor Manufacturing Company, Ltd. Forming seal ring in an integrated circuit die
US8820728B2 (en) * 2009-02-02 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor wafer carrier
US8704375B2 (en) * 2009-02-04 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Barrier structures and methods for through substrate vias
US9142586B2 (en) 2009-02-24 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for backside illuminated image sensor
US8531565B2 (en) * 2009-02-24 2013-09-10 Taiwan Semiconductor Manufacturing Company, Ltd. Front side implanted guard ring structure for backside illuminated image sensor
US7932608B2 (en) * 2009-02-24 2011-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon via formed with a post passivation interconnect structure
US8643149B2 (en) * 2009-03-03 2014-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Stress barrier structures for semiconductor chips
US8487444B2 (en) * 2009-03-06 2013-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional system-in-package architecture
WO2010104610A2 (en) * 2009-03-13 2010-09-16 Tessera Technologies Hungary Kft. Stacked microelectronic assemblies having vias extending through bond pads
US8344513B2 (en) 2009-03-23 2013-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Barrier for through-silicon via
US8232140B2 (en) * 2009-03-27 2012-07-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method for ultra thin wafer handling and processing
US8329578B2 (en) 2009-03-27 2012-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. Via structure and via etching process of forming the same
US8552563B2 (en) 2009-04-07 2013-10-08 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional semiconductor architecture
US8691664B2 (en) * 2009-04-20 2014-04-08 Taiwan Semiconductor Manufacturing Company, Ltd. Backside process for a substrate
US8759949B2 (en) * 2009-04-30 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer backside structures having copper pillars
US8432038B2 (en) * 2009-06-12 2013-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon via structure and a process for forming the same
FR2947098A1 (fr) 2009-06-18 2010-12-24 Commissariat Energie Atomique Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince
US8158489B2 (en) * 2009-06-26 2012-04-17 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of TSV backside interconnects by modifying carrier wafers
US9305769B2 (en) 2009-06-30 2016-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. Thin wafer handling method
US8871609B2 (en) * 2009-06-30 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. Thin wafer handling structure and method
US8247906B2 (en) 2009-07-06 2012-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. Supplying power to integrated circuits using a grid matrix formed of through-silicon vias
US8264066B2 (en) 2009-07-08 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Liner formation in 3DIC structures
US8841766B2 (en) 2009-07-30 2014-09-23 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall protection structure
US8377816B2 (en) * 2009-07-30 2013-02-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming electrical connections
US8859424B2 (en) 2009-08-14 2014-10-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor wafer carrier and method of manufacturing
US8324738B2 (en) 2009-09-01 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned protection layer for copper post structure
US8252665B2 (en) 2009-09-14 2012-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Protection layer for adhesive material at wafer edge
US8791549B2 (en) 2009-09-22 2014-07-29 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer backside interconnect structure connected to TSVs
CN102033877A (zh) * 2009-09-27 2011-04-27 阿里巴巴集团控股有限公司 检索方法和装置
US8647925B2 (en) * 2009-10-01 2014-02-11 Taiwan Semiconductor Manufacturing Company, Ltd. Surface modification for handling wafer thinning process
US8264067B2 (en) * 2009-10-09 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Through silicon via (TSV) wire bond architecture
US7969013B2 (en) * 2009-10-22 2011-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Through silicon via with dummy structure and method for forming the same
US8659155B2 (en) * 2009-11-05 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming copper pillar bumps
US8283745B2 (en) 2009-11-06 2012-10-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating backside-illuminated image sensor
US8405201B2 (en) 2009-11-09 2013-03-26 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon via structure
US10297550B2 (en) 2010-02-05 2019-05-21 Taiwan Semiconductor Manufacturing Company, Ltd. 3D IC architecture with interposer and interconnect structure for bonding dies
US8610270B2 (en) * 2010-02-09 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and semiconductor assembly with lead-free solder
US8252682B2 (en) * 2010-02-12 2012-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method for thinning a wafer
US8390009B2 (en) 2010-02-16 2013-03-05 Taiwan Semiconductor Manufacturing Company, Ltd. Light-emitting diode (LED) package systems
US8237272B2 (en) * 2010-02-16 2012-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive pillar structure for semiconductor substrate and method of manufacture
US8466059B2 (en) 2010-03-30 2013-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-layer interconnect structure for stacked dies
US8222139B2 (en) 2010-03-30 2012-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. Chemical mechanical polishing (CMP) processing of through-silicon via (TSV) and contact plug simultaneously
US8507940B2 (en) 2010-04-05 2013-08-13 Taiwan Semiconductor Manufacturing Company, Ltd. Heat dissipation by through silicon plugs
US8174124B2 (en) 2010-04-08 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Dummy pattern in wafer backside routing
US8455995B2 (en) 2010-04-16 2013-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. TSVs with different sizes in interposers for bonding dies
US8519538B2 (en) 2010-04-28 2013-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. Laser etch via formation
US9293366B2 (en) 2010-04-28 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate vias with improved connections
US8441124B2 (en) 2010-04-29 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall protection structure
US8866301B2 (en) 2010-05-18 2014-10-21 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers with interconnection structures
FI123860B (fi) * 2010-05-18 2013-11-29 Corelase Oy Menetelmä substraattien tiivistämiseksi ja kontaktoimiseksi laservalon avulla ja elektroniikkamoduli
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US9059026B2 (en) 2010-06-01 2015-06-16 Taiwan Semiconductor Manufacturing Company, Ltd. 3-D inductor and transformer
US8471358B2 (en) 2010-06-01 2013-06-25 Taiwan Semiconductor Manufacturing Company, Ltd. 3D inductor and transformer
US9018758B2 (en) 2010-06-02 2015-04-28 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall spacer and metal top cap
US8362591B2 (en) 2010-06-08 2013-01-29 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuits and methods of forming the same
US8411459B2 (en) 2010-06-10 2013-04-02 Taiwan Semiconductor Manufacturing Company, Ltd Interposer-on-glass package structures
US8500182B2 (en) 2010-06-17 2013-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. Vacuum wafer carriers for strengthening thin wafers
JP6342033B2 (ja) * 2010-06-30 2018-06-13 キヤノン株式会社 固体撮像装置
US8896136B2 (en) 2010-06-30 2014-11-25 Taiwan Semiconductor Manufacturing Company, Ltd. Alignment mark and method of formation
JP2012033894A (ja) 2010-06-30 2012-02-16 Canon Inc 固体撮像装置
US8319336B2 (en) 2010-07-08 2012-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Reduction of etch microloading for through silicon vias
US8338939B2 (en) 2010-07-12 2012-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. TSV formation processes using TSV-last approach
US8999179B2 (en) 2010-07-13 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive vias in a substrate
US8722540B2 (en) 2010-07-22 2014-05-13 Taiwan Semiconductor Manufacturing Company, Ltd. Controlling defects in thin wafer handling
US9299594B2 (en) 2010-07-27 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate bonding system and method of modifying the same
US8674510B2 (en) 2010-07-29 2014-03-18 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional integrated circuit structure having improved power and thermal management
JP5601079B2 (ja) * 2010-08-09 2014-10-08 三菱電機株式会社 半導体装置、半導体回路基板および半導体回路基板の製造方法
US8846499B2 (en) 2010-08-17 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Composite carrier structure
US8546254B2 (en) 2010-08-19 2013-10-01 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming copper pillar bumps using patterned anodes
US8507358B2 (en) 2010-08-27 2013-08-13 Taiwan Semiconductor Manufacturing Company, Ltd. Composite wafer semiconductor
US8693163B2 (en) 2010-09-01 2014-04-08 Taiwan Semiconductor Manufacturing Company, Ltd. Cylindrical embedded capacitors
US8928159B2 (en) 2010-09-02 2015-01-06 Taiwan Semiconductor Manufacturing & Company, Ltd. Alignment marks in substrate having through-substrate via (TSV)
US8502338B2 (en) 2010-09-09 2013-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate via waveguides
US8928127B2 (en) 2010-09-24 2015-01-06 Taiwan Semiconductor Manufacturing Company, Ltd. Noise decoupling structure with through-substrate vias
US8525343B2 (en) 2010-09-28 2013-09-03 Taiwan Semiconductor Manufacturing Company, Ltd. Device with through-silicon via (TSV) and method of forming the same
US8580682B2 (en) 2010-09-30 2013-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Cost-effective TSV formation
US9190325B2 (en) 2010-09-30 2015-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. TSV formation
CN103109350A (zh) * 2010-09-30 2013-05-15 飞思卡尔半导体公司 处理半导体晶片的方法、半导体晶片以及半导体器件
US8836116B2 (en) 2010-10-21 2014-09-16 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level packaging of micro-electro-mechanical systems (MEMS) and complementary metal-oxide-semiconductor (CMOS) substrates
US8519409B2 (en) 2010-11-15 2013-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. Light emitting diode components integrated with thermoelectric devices
US8567837B2 (en) 2010-11-24 2013-10-29 Taiwan Semiconductor Manufacturing Company, Ltd. Reconfigurable guide pin design for centering wafers having different sizes
US9153462B2 (en) 2010-12-09 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Spin chuck for thin wafer cleaning
US8773866B2 (en) 2010-12-10 2014-07-08 Taiwan Semiconductor Manufacturing Company, Ltd. Radio-frequency packaging with reduced RF loss
TWI458072B (zh) * 2010-12-16 2014-10-21 Soitec Silicon On Insulator 將半導體構造直接黏附在一起之方法以及應用此等方法所形成之黏附半導體構造
US8778773B2 (en) 2010-12-16 2014-07-15 Soitec Methods for directly bonding together semiconductor structures, and bonded semiconductor structures formed using such methods
US8236584B1 (en) 2011-02-11 2012-08-07 Tsmc Solid State Lighting Ltd. Method of forming a light emitting diode emitter substrate with highly reflective metal bonding
US9059262B2 (en) 2011-02-24 2015-06-16 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuits including conductive structures through a substrate and methods of making the same
US8487410B2 (en) 2011-04-13 2013-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon vias for semicondcutor substrate and method of manufacture
US8716128B2 (en) 2011-04-14 2014-05-06 Tsmc Solid State Lighting Ltd. Methods of forming through silicon via openings
US8546235B2 (en) 2011-05-05 2013-10-01 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuits including metal-insulator-metal capacitors and methods of forming the same
EP4047647A3 (en) 2011-05-24 2023-03-08 Sony Group Corporation Semiconductor device
US8674883B2 (en) 2011-05-24 2014-03-18 Taiwan Semiconductor Manufacturing Company, Ltd. Antenna using through-silicon via
US8900994B2 (en) 2011-06-09 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for producing a protective structure
US8552485B2 (en) 2011-06-15 2013-10-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure having metal-insulator-metal capacitor structure
US8587127B2 (en) 2011-06-15 2013-11-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structures and methods of forming the same
US8766409B2 (en) 2011-06-24 2014-07-01 Taiwan Semiconductor Manufacturing Co., Ltd. Method and structure for through-silicon via (TSV) with diffused isolation well
US8531035B2 (en) 2011-07-01 2013-09-10 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect barrier structure and method
TWI495041B (zh) 2011-07-05 2015-08-01 Sony Corp 半導體裝置、用於半導體裝置之製造方法及電子設備
US8896125B2 (en) 2011-07-05 2014-11-25 Sony Corporation Semiconductor device, fabrication method for a semiconductor device and electronic apparatus
US8872345B2 (en) 2011-07-07 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. Forming grounded through-silicon vias in a semiconductor substrate
US8604491B2 (en) 2011-07-21 2013-12-10 Tsmc Solid State Lighting Ltd. Wafer level photonic device die structure and method of making the same
US8445296B2 (en) 2011-07-22 2013-05-21 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and methods for end point determination in reactive ion etching
US8809073B2 (en) 2011-08-03 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and methods for de-embedding through substrate vias
US9159907B2 (en) 2011-08-04 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid film for protecting MTJ stacks of MRAM
US8748284B2 (en) 2011-08-12 2014-06-10 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing decoupling MIM capacitor designs for interposers
US8525278B2 (en) 2011-08-19 2013-09-03 Taiwan Semiconductor Manufacturing Company, Ltd. MEMS device having chip scale packaging
US8546886B2 (en) 2011-08-24 2013-10-01 Taiwan Semiconductor Manufacturing Company, Ltd. Controlling the device performance by forming a stressed backside dielectric layer
US8604619B2 (en) 2011-08-31 2013-12-10 Taiwan Semiconductor Manufacturing Company, Ltd. Through silicon via keep out zone formation along different crystal orientations
US8803322B2 (en) 2011-10-13 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Through substrate via structures and methods of forming the same
US8659126B2 (en) 2011-12-07 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit ground shielding structure
US8610247B2 (en) 2011-12-30 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for a transformer with magnetic features
US9087838B2 (en) 2011-10-25 2015-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for a high-K transformer with capacitive coupling
US8896089B2 (en) 2011-11-09 2014-11-25 Taiwan Semiconductor Manufacturing Company, Ltd. Interposers for semiconductor devices and methods of manufacture thereof
US9390949B2 (en) 2011-11-29 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer debonding and cleaning apparatus and method of use
US11264262B2 (en) 2011-11-29 2022-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer debonding and cleaning apparatus
US10381254B2 (en) 2011-11-29 2019-08-13 Taiwan Semiconductor Manufacturing Co., Ltd. Wafer debonding and cleaning apparatus and method
US8803316B2 (en) 2011-12-06 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. TSV structures and methods for forming the same
US8546953B2 (en) 2011-12-13 2013-10-01 Taiwan Semiconductor Manufacturing Co., Ltd. Through silicon via (TSV) isolation structures for noise reduction in 3D integrated circuit
US8890293B2 (en) 2011-12-16 2014-11-18 Taiwan Semiconductor Manufacturing Company, Ltd. Guard ring for through vias
US8580647B2 (en) 2011-12-19 2013-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Inductors with through VIAS
US8618631B2 (en) 2012-02-14 2013-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. On-chip ferrite bead inductor
US9618712B2 (en) 2012-02-23 2017-04-11 Taiwan Semiconductor Manufacturing Company, Ltd. Optical bench on substrate and method of making the same
US10180547B2 (en) 2012-02-23 2019-01-15 Taiwan Semiconductor Manufacturing Company, Ltd. Optical bench on substrate
US8860114B2 (en) 2012-03-02 2014-10-14 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for a fishbone differential capacitor
US9293521B2 (en) 2012-03-02 2016-03-22 Taiwan Semiconductor Manufacturing Co., Ltd. Concentric capacitor structure
US9312432B2 (en) 2012-03-13 2016-04-12 Tsmc Solid State Lighting Ltd. Growing an improved P-GaN layer of an LED through pressure ramping
US9139420B2 (en) 2012-04-18 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. MEMS device structure and methods of forming same
US9583365B2 (en) 2012-05-25 2017-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming interconnects for three dimensional integrated circuit
US8735219B2 (en) 2012-08-30 2014-05-27 Ziptronix, Inc. Heterogeneous annealing method and device
US9484211B2 (en) 2013-01-24 2016-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Etchant and etching process
US9490133B2 (en) 2013-01-24 2016-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Etching apparatus
US9041152B2 (en) 2013-03-14 2015-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Inductor with magnetic material
US9356066B2 (en) 2013-03-15 2016-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for stacked device and method
US10096515B2 (en) 2013-03-15 2018-10-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for stacked device
JP5939184B2 (ja) 2013-03-22 2016-06-22 ソニー株式会社 半導体装置の製造方法
US9640510B2 (en) * 2013-07-05 2017-05-02 Ev Group E. Thallner Gmbh Method for bonding metallic contact areas with solution of a sacrificial layer applied on one of the contact areas
US9293392B2 (en) 2013-09-06 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC interconnect apparatus and method
JP6212720B2 (ja) * 2013-09-20 2017-10-18 パナソニックＩｐマネジメント株式会社 半導体装置及びその製造方法
US9437572B2 (en) * 2013-12-18 2016-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive pad structure for hybrid bonding and methods of forming same
US20150262902A1 (en) 2014-03-12 2015-09-17 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
US9786613B2 (en) 2014-08-07 2017-10-10 Qualcomm Incorporated EMI shield for high frequency layer transferred devices
TWI747805B (zh) * 2014-10-08 2021-12-01 日商索尼半導體解決方案公司 攝像裝置及製造方法、以及電子機器
US11069734B2 (en) 2014-12-11 2021-07-20 Invensas Corporation Image sensor device
KR102492854B1 (ko) 2015-03-03 2023-01-31 소니그룹주식회사 반도체 장치 및 전자 기기
US9741620B2 (en) 2015-06-24 2017-08-22 Invensas Corporation Structures and methods for reliable packages
US10886250B2 (en) 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US9953941B2 (en) 2015-08-25 2018-04-24 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
US9852988B2 (en) 2015-12-18 2017-12-26 Invensas Bonding Technologies, Inc. Increased contact alignment tolerance for direct bonding
JP2017117828A (ja) 2015-12-21 2017-06-29 ソニー株式会社 固体撮像素子および電子装置
US10446532B2 (en) 2016-01-13 2019-10-15 Invensas Bonding Technologies, Inc. Systems and methods for efficient transfer of semiconductor elements
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
KR102555408B1 (ko) * 2016-06-30 2023-07-13 엘지디스플레이 주식회사 비표시 영역으로 연장하는 신호 배선들을 포함하는 디스플레이 장치
US10446487B2 (en) 2016-09-30 2019-10-15 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US10580735B2 (en) 2016-10-07 2020-03-03 Xcelsis Corporation Stacked IC structure with system level wiring on multiple sides of the IC die
TW202414634A (zh) 2016-10-27 2024-04-01 美商艾德亞半導體科技有限責任公司 用於低溫接合的結構和方法
US10002844B1 (en) 2016-12-21 2018-06-19 Invensas Bonding Technologies, Inc. Bonded structures
US10796936B2 (en) 2016-12-22 2020-10-06 Invensas Bonding Technologies, Inc. Die tray with channels
US20180182665A1 (en) 2016-12-28 2018-06-28 Invensas Bonding Technologies, Inc. Processed Substrate
CN110178212B (zh) 2016-12-28 2024-01-09 艾德亚半导体接合科技有限公司 堆栈基板的处理
JP2020503692A (ja) 2016-12-29 2020-01-30 インヴェンサス ボンディング テクノロジーズ インコーポレイテッド 集積された受動部品を有する接合構造物
JP7030825B2 (ja) 2017-02-09 2022-03-07 インヴェンサス ボンディング テクノロジーズ インコーポレイテッド 接合構造物
WO2018169968A1 (en) 2017-03-16 2018-09-20 Invensas Corporation Direct-bonded led arrays and applications
US10515913B2 (en) 2017-03-17 2019-12-24 Invensas Bonding Technologies, Inc. Multi-metal contact structure
US10508030B2 (en) 2017-03-21 2019-12-17 Invensas Bonding Technologies, Inc. Seal for microelectronic assembly
JP2018163970A (ja) 2017-03-24 2018-10-18 東芝メモリ株式会社 半導体装置及びその製造方法
US10784191B2 (en) 2017-03-31 2020-09-22 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US10269756B2 (en) 2017-04-21 2019-04-23 Invensas Bonding Technologies, Inc. Die processing
US10879212B2 (en) 2017-05-11 2020-12-29 Invensas Bonding Technologies, Inc. Processed stacked dies
US10529634B2 (en) 2017-05-11 2020-01-07 Invensas Bonding Technologies, Inc. Probe methodology for ultrafine pitch interconnects
IT201700053902A1 (it) 2017-05-18 2018-11-18 Lfoundry Srl Metodo di bonding ibrido per wafer a semiconduttore e relativo dispositivo integrato tridimensionale
US10446441B2 (en) 2017-06-05 2019-10-15 Invensas Corporation Flat metal features for microelectronics applications
US10217720B2 (en) 2017-06-15 2019-02-26 Invensas Corporation Multi-chip modules formed using wafer-level processing of a reconstitute wafer
US10840205B2 (en) 2017-09-24 2020-11-17 Invensas Bonding Technologies, Inc. Chemical mechanical polishing for hybrid bonding
US11195748B2 (en) 2017-09-27 2021-12-07 Invensas Corporation Interconnect structures and methods for forming same
US11031285B2 (en) 2017-10-06 2021-06-08 Invensas Bonding Technologies, Inc. Diffusion barrier collar for interconnects
US10658313B2 (en) 2017-12-11 2020-05-19 Invensas Bonding Technologies, Inc. Selective recess
CN109911839B (zh) * 2017-12-12 2023-10-13 中国科学院半导体研究所 能抑制光噪声的微电极、采用其的电路及其制备方法
US11011503B2 (en) 2017-12-15 2021-05-18 Invensas Bonding Technologies, Inc. Direct-bonded optoelectronic interconnect for high-density integrated photonics
US10923408B2 (en) 2017-12-22 2021-02-16 Invensas Bonding Technologies, Inc. Cavity packages
US11380597B2 (en) 2017-12-22 2022-07-05 Invensas Bonding Technologies, Inc. Bonded structures
US10727219B2 (en) 2018-02-15 2020-07-28 Invensas Bonding Technologies, Inc. Techniques for processing devices
US11169326B2 (en) 2018-02-26 2021-11-09 Invensas Bonding Technologies, Inc. Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects
US11256004B2 (en) 2018-03-20 2022-02-22 Invensas Bonding Technologies, Inc. Direct-bonded lamination for improved image clarity in optical devices
US11056348B2 (en) 2018-04-05 2021-07-06 Invensas Bonding Technologies, Inc. Bonding surfaces for microelectronics
US11244916B2 (en) 2018-04-11 2022-02-08 Invensas Bonding Technologies, Inc. Low temperature bonded structures
US10790262B2 (en) 2018-04-11 2020-09-29 Invensas Bonding Technologies, Inc. Low temperature bonded structures
US10964664B2 (en) 2018-04-20 2021-03-30 Invensas Bonding Technologies, Inc. DBI to Si bonding for simplified handle wafer
US11004757B2 (en) 2018-05-14 2021-05-11 Invensas Bonding Technologies, Inc. Bonded structures
US11276676B2 (en) 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
US10923413B2 (en) 2018-05-30 2021-02-16 Xcelsis Corporation Hard IP blocks with physically bidirectional passageways
US11171117B2 (en) 2018-06-12 2021-11-09 Invensas Bonding Technologies, Inc. Interlayer connection of stacked microelectronic components
US11749645B2 (en) 2018-06-13 2023-09-05 Adeia Semiconductor Bonding Technologies Inc. TSV as pad
US11393779B2 (en) 2018-06-13 2022-07-19 Invensas Bonding Technologies, Inc. Large metal pads over TSV
FR3082656B1 (fr) 2018-06-18 2022-02-04 Commissariat Energie Atomique Circuit integre comprenant des macros et son procede de fabrication
US10910344B2 (en) 2018-06-22 2021-02-02 Xcelsis Corporation Systems and methods for releveled bump planes for chiplets
WO2020010056A1 (en) 2018-07-03 2020-01-09 Invensas Bonding Technologies, Inc. Techniques for joining dissimilar materials in microelectronics
WO2020010136A1 (en) 2018-07-06 2020-01-09 Invensas Bonding Technologies, Inc. Molded direct bonded and interconnected stack
WO2020010265A1 (en) 2018-07-06 2020-01-09 Invensas Bonding Technologies, Inc. Microelectronic assemblies
US11515291B2 (en) 2018-08-28 2022-11-29 Adeia Semiconductor Inc. Integrated voltage regulator and passive components
US20200075533A1 (en) 2018-08-29 2020-03-05 Invensas Bonding Technologies, Inc. Bond enhancement in microelectronics by trapping contaminants and arresting cracks during direct-bonding processes
US11011494B2 (en) 2018-08-31 2021-05-18 Invensas Bonding Technologies, Inc. Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics
US11158573B2 (en) 2018-10-22 2021-10-26 Invensas Bonding Technologies, Inc. Interconnect structures
US11244920B2 (en) 2018-12-18 2022-02-08 Invensas Bonding Technologies, Inc. Method and structures for low temperature device bonding
WO2020150159A1 (en) 2019-01-14 2020-07-23 Invensas Bonding Technologies, Inc. Bonded structures
US11901281B2 (en) 2019-03-11 2024-02-13 Adeia Semiconductor Bonding Technologies Inc. Bonded structures with integrated passive component
JP2020150079A (ja) * 2019-03-12 2020-09-17 キオクシア株式会社 半導体記憶装置およびその製造方法
US10854578B2 (en) 2019-03-29 2020-12-01 Invensas Corporation Diffused bitline replacement in stacked wafer memory
US11205625B2 (en) 2019-04-12 2021-12-21 Invensas Bonding Technologies, Inc. Wafer-level bonding of obstructive elements
US11373963B2 (en) 2019-04-12 2022-06-28 Invensas Bonding Technologies, Inc. Protective elements for bonded structures
US11610846B2 (en) 2019-04-12 2023-03-21 Adeia Semiconductor Bonding Technologies Inc. Protective elements for bonded structures including an obstructive element
US11355404B2 (en) 2019-04-22 2022-06-07 Invensas Bonding Technologies, Inc. Mitigating surface damage of probe pads in preparation for direct bonding of a substrate
US11385278B2 (en) 2019-05-23 2022-07-12 Invensas Bonding Technologies, Inc. Security circuitry for bonded structures
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US12080672B2 (en) 2019-09-26 2024-09-03 Adeia Semiconductor Bonding Technologies Inc. Direct gang bonding methods including directly bonding first element to second element to form bonded structure without adhesive
US12113054B2 (en) 2019-10-21 2024-10-08 Adeia Semiconductor Technologies Llc Non-volatile dynamic random access memory
US11862602B2 (en) 2019-11-07 2024-01-02 Adeia Semiconductor Technologies Llc Scalable architecture for reduced cycles across SOC
US11762200B2 (en) 2019-12-17 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded optical devices
US11876076B2 (en) 2019-12-20 2024-01-16 Adeia Semiconductor Technologies Llc Apparatus for non-volatile random access memory stacks
US11721653B2 (en) 2019-12-23 2023-08-08 Adeia Semiconductor Bonding Technologies Inc. Circuitry for electrical redundancy in bonded structures
US11842894B2 (en) 2019-12-23 2023-12-12 Adeia Semiconductor Bonding Technologies Inc. Electrical redundancy for bonded structures
CN115943489A (zh) 2020-03-19 2023-04-07 隔热半导体粘合技术公司 用于直接键合结构的尺寸补偿控制
US11742314B2 (en) 2020-03-31 2023-08-29 Adeia Semiconductor Bonding Technologies Inc. Reliable hybrid bonded apparatus
WO2021236361A1 (en) 2020-05-19 2021-11-25 Invensas Bonding Technologies, Inc. Laterally unconfined structure
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US20220093492A1 (en) * 2020-09-18 2022-03-24 Intel Corporation Direct bonding in microelectronic assemblies
US11990448B2 (en) 2020-09-18 2024-05-21 Intel Corporation Direct bonding in microelectronic assemblies
US11264357B1 (en) 2020-10-20 2022-03-01 Invensas Corporation Mixed exposure for large die

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4829018A (en) * 1986-06-27 1989-05-09 Wahlstrom Sven E Multilevel integrated circuits employing fused oxide layers
JPH0391227A (ja) * 1989-09-01 1991-04-16 Nippon Soken Inc 半導体基板の接着方法
JPH0547943A (ja) * 1991-08-19 1993-02-26 Seiko Epson Corp 半導体集積装置
JPH0547767A (ja) * 1991-08-19 1993-02-26 Yamaha Corp 集積回路装置の配線構造
JPH05121283A (ja) * 1991-10-24 1993-05-18 Sony Corp 半導体装置の製造方法
DE59406156D1 (de) * 1993-02-11 1998-07-16 Siemens Ag Verfahren zur Herstellung einer dreidimensionalen Schaltungsanordnung
WO1996001497A1 (de) * 1994-07-05 1996-01-18 Siemens Aktiengesellschaft Verfahren zur herstellung einer dreidimensionalen schaltungsanordnung
US6423571B2 (en) * 1994-09-20 2002-07-23 Hitachi, Ltd. Method of making a semiconductor device having a stress relieving mechanism
EP0714124B1 (de) * 1994-11-17 2003-01-29 Infineon Technologies AG Verfahren zur Befestigung eines ersten Substrates auf einem zweiten Substrat und Verwendung des Verfahrens zur Herstellung einer dreidimensionalen Schaltungsanordnung
JPH1083980A (ja) * 1996-09-06 1998-03-31 Hitachi Ltd 半導体装置の製造方法
US6097096A (en) * 1997-07-11 2000-08-01 Advanced Micro Devices Metal attachment method and structure for attaching substrates at low temperatures

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102544034A (zh) * 2010-10-27 2012-07-04 索尼公司 固态摄像器件和半导体器件及其制造方法以及电子装置

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