FR3082656B1 - Circuit integre comprenant des macros et son procede de fabrication - Google Patents

Circuit integre comprenant des macros et son procede de fabrication Download PDF

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Publication number
FR3082656B1
FR3082656B1 FR1855325A FR1855325A FR3082656B1 FR 3082656 B1 FR3082656 B1 FR 3082656B1 FR 1855325 A FR1855325 A FR 1855325A FR 1855325 A FR1855325 A FR 1855325A FR 3082656 B1 FR3082656 B1 FR 3082656B1
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France
Prior art keywords
macros
manufacturing
integrated circuit
macro
circuit
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Active
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FR1855325A
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English (en)
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FR3082656A1 (fr
Inventor
Hughes Metras
Fabien Clermidy
Didier Lattard
Sebastien Thuries
Pascal Vivet
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Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Priority to FR1855325A priority Critical patent/FR3082656B1/fr
Priority to EP19180679.3A priority patent/EP3584825A1/fr
Priority to US16/443,441 priority patent/US10937778B2/en
Publication of FR3082656A1 publication Critical patent/FR3082656A1/fr
Application granted granted Critical
Publication of FR3082656B1 publication Critical patent/FR3082656B1/fr
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/22Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H01L22/10Measuring as part of the manufacturing process
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    • H01L2224/802Applying energy for connecting
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    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/351Thermal stress
    • H01L2924/3512Cracking
    • H01L2924/35121Peeling or delaminating

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

L'invention concerne un niveau d'un circuit 3D, comprenant : un ou plusieurs circuits macros, chaque circuit macro comprenant une pluralité de cellules macros (202) agencées en une matrice (101), les cellules macros (202) étant séparées entre elles par des espaces ; et des vias d'interconnexion (110) disposés dans les espaces entre les cellules macros (202).
FR1855325A 2018-06-18 2018-06-18 Circuit integre comprenant des macros et son procede de fabrication Active FR3082656B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR1855325A FR3082656B1 (fr) 2018-06-18 2018-06-18 Circuit integre comprenant des macros et son procede de fabrication
EP19180679.3A EP3584825A1 (fr) 2018-06-18 2019-06-17 Circuit intégré comprenant des macros et son procédé de fabrication
US16/443,441 US10937778B2 (en) 2018-06-18 2019-06-17 Integrated circuit comprising macros and method of fabricating the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1855325A FR3082656B1 (fr) 2018-06-18 2018-06-18 Circuit integre comprenant des macros et son procede de fabrication
FR1855325 2018-06-18

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Publication Number Publication Date
FR3082656A1 FR3082656A1 (fr) 2019-12-20
FR3082656B1 true FR3082656B1 (fr) 2022-02-04

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FR1855325A Active FR3082656B1 (fr) 2018-06-18 2018-06-18 Circuit integre comprenant des macros et son procede de fabrication

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EP (1) EP3584825A1 (fr)
FR (1) FR3082656B1 (fr)

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KR20220065292A (ko) * 2020-11-13 2022-05-20 삼성전자주식회사 반도체 패키지 및 그의 제조 방법
US11894356B2 (en) * 2021-08-17 2024-02-06 Macronix International Co., Ltd. Chip having multiple functional units and semiconductor structure using the same
WO2023121644A1 (fr) 2021-12-20 2023-06-29 Monde Wireless Inc. Dispositif à semi-conducteurs pour circuit intégré rf
TWI790139B (zh) * 2022-03-09 2023-01-11 力晶積成電子製造股份有限公司 基底穿孔測試結構

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FR3082656A1 (fr) 2019-12-20

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