FR3079966B1 - Circuit 3d sram avec transistors double-grille a agencement ameliore - Google Patents

Circuit 3d sram avec transistors double-grille a agencement ameliore Download PDF

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Publication number
FR3079966B1
FR3079966B1 FR1853115A FR1853115A FR3079966B1 FR 3079966 B1 FR3079966 B1 FR 3079966B1 FR 1853115 A FR1853115 A FR 1853115A FR 1853115 A FR1853115 A FR 1853115A FR 3079966 B1 FR3079966 B1 FR 3079966B1
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FR
France
Prior art keywords
sram
transistor
dual
circuit
transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1853115A
Other languages
English (en)
Other versions
FR3079966A1 (fr
Inventor
Francois Andrieu
Remy Berthelon
Bastien Giraud
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Crolles 2 SAS
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
STMicroelectronics Crolles 2 SAS
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Publication date
Application filed by Commissariat a lEnergie Atomique CEA, STMicroelectronics Crolles 2 SAS, Commissariat a lEnergie Atomique et aux Energies Alternatives CEA filed Critical Commissariat a lEnergie Atomique CEA
Priority to FR1853115A priority Critical patent/FR3079966B1/fr
Priority to US16/379,476 priority patent/US10741565B2/en
Publication of FR3079966A1 publication Critical patent/FR3079966A1/fr
Application granted granted Critical
Publication of FR3079966B1 publication Critical patent/FR3079966B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8221—Three dimensional integrated circuits stacked in different levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)

Abstract

La demande concerne un circuit intégré à mémoire SRAM et doté de plusieurs niveaux superposés de transistors, le circuit intégré comprenant des cellules SRAM dotées d'un premier transistor et d'un deuxième transistor appartenant à un niveau supérieur de transistors et ayant chacun une double-grille composée d'une électrode supérieure et d'une électrode inférieure agencée de part et d'autre d'une couche semi-conductrice (110), une électrode de grille inférieure du premier transistor étant reliée à une électrode de grille inférieure du deuxième transistor.
FR1853115A 2018-04-10 2018-04-10 Circuit 3d sram avec transistors double-grille a agencement ameliore Active FR3079966B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR1853115A FR3079966B1 (fr) 2018-04-10 2018-04-10 Circuit 3d sram avec transistors double-grille a agencement ameliore
US16/379,476 US10741565B2 (en) 2018-04-10 2019-04-09 3D SRAM circuit with double gate transistors with improved layout

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1853115 2018-04-10
FR1853115A FR3079966B1 (fr) 2018-04-10 2018-04-10 Circuit 3d sram avec transistors double-grille a agencement ameliore

Publications (2)

Publication Number Publication Date
FR3079966A1 FR3079966A1 (fr) 2019-10-11
FR3079966B1 true FR3079966B1 (fr) 2022-01-14

Family

ID=63143221

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1853115A Active FR3079966B1 (fr) 2018-04-10 2018-04-10 Circuit 3d sram avec transistors double-grille a agencement ameliore

Country Status (2)

Country Link
US (1) US10741565B2 (fr)
FR (1) FR3079966B1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3083912A1 (fr) * 2018-07-13 2020-01-17 Commissariat A L'energie Atomique Et Aux Energies Alternatives Memoire sram / rom reconfigurable par polarisation de substrat
FR3103963B1 (fr) * 2019-12-03 2021-12-03 Commissariat Energie Atomique Dispositif memoire 3d comprenant des cellules memoires de type sram a polarisation arriere ajustable

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6643159B2 (en) * 2002-04-02 2003-11-04 Hewlett-Packard Development Company, L.P. Cubic memory array
US20070183185A1 (en) * 2006-01-11 2007-08-09 The Regents Of The University Of California Finfet-based sram with feedback
WO2008069277A1 (fr) * 2006-12-07 2008-06-12 National Institute Of Advanced Industrial Science And Technology Dispositif sram
FR2910999B1 (fr) * 2006-12-28 2009-04-03 Commissariat Energie Atomique Cellule memoire dotee de transistors double-grille, a grilles independantes et asymetriques
FR2932003B1 (fr) * 2008-06-02 2011-03-25 Commissariat Energie Atomique Cellule de memoire sram a transistor integres sur plusieurs niveaux et dont la tension de seuil vt est ajustable dynamiquement
JP5278971B2 (ja) * 2010-03-30 2013-09-04 独立行政法人産業技術総合研究所 Ｓｒａｍ装置
US9865330B2 (en) * 2010-11-04 2018-01-09 Qualcomm Incorporated Stable SRAM bitcell design utilizing independent gate FinFET
TWI456739B (zh) * 2011-12-13 2014-10-11 Nat Univ Tsing Hua 三維記憶體晶片之控制結構
US8964452B2 (en) * 2012-12-26 2015-02-24 Applied Micro Circuits Corporation Programmable resistance-modulated write assist for a memory device
US9875789B2 (en) * 2013-11-22 2018-01-23 Taiwan Semiconductor Manufacturing Company, Ltd. 3D structure for advanced SRAM design to avoid half-selected issue

Also Published As

Publication number Publication date
US10741565B2 (en) 2020-08-11
US20190312039A1 (en) 2019-10-10
FR3079966A1 (fr) 2019-10-11

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