TW201730364A - 半導體元件用磊晶基板、半導體元件以及半導體元件用磊晶基板之製造方法 - Google Patents
半導體元件用磊晶基板、半導體元件以及半導體元件用磊晶基板之製造方法 Download PDFInfo
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- TW201730364A TW201730364A TW105134697A TW105134697A TW201730364A TW 201730364 A TW201730364 A TW 201730364A TW 105134697 A TW105134697 A TW 105134697A TW 105134697 A TW105134697 A TW 105134697A TW 201730364 A TW201730364 A TW 201730364A
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Abstract
本發明係提供經抑制電流崩塌發生的半導體元件用磊晶基板。半導體元件用磊晶基板係包括:由經摻雜Zn的GaN所構成半絕緣性獨立式基板、鄰接上述獨立式基板的緩衝層、鄰接上述緩衝層的通道層、以及設置於上述緩衝層對向側呈夾置上述通道層狀態的障壁層;上述緩衝層係抑制Zn從上述獨立式基板擴散於上述通道層的擴散阻障層。
Description
本發明係關於半導體元件,特別係關於使用由半絕緣性GaN所構成獨立式基板形成的半導體元件。
氮化物半導體係因為具有直接躍遷式寬能階,且具有高絕緣崩潰電場、高飽和電子速度,故而利用為LED、LD等發光裝置、高頻/高功率的電子裝置用半導體材料。
氮化物電子裝置的代表性構造係有如由以AlGaN為「障壁層」、以GaN為「通道層」進行積層形成的高電子遷移率電晶體(HEMT)構造。此係活用利用氮化物材料特有較大的極化效應(自發性極化效應與壓電極化效應),而在AlGaN/GaN積層界面處生成高濃度二維電子氣體的特徵。
氮化物電子裝置一般係使用藍寶石、SiC、Si之類商業上容易取得的異種材料底層基板製作而成。然而,在該等異種材料基板上進行異質磊晶成長的GaN膜中,會有因GaN與異種材料基板間之晶格常數、熱膨脹係數的差異,而造成產生多數缺陷的問題。
另一方面,在GaN基板上使GaN膜進行同質磊晶成長時,不會有上述因晶格常數、熱膨脹係數差異而造成的缺
陷發生,使GaN膜呈良好的結晶性。
故,當在GaN基板上製作氮化物HEMT構造時,會提升在AlGaN/GaN積層界面所存在二維電子氣體的遷移率,因而使用該構造所製作的HEMT元件(半導體元件)可期待獲特性提升。
但,商業上可取得依氫化物氣相磊晶法(HVPE法)製作的GaN基板,一般會因被取入於結晶內的氧雜質而呈現n型電導型。導電性GaN基板在HEMT元件進行高電壓驅動時,會成為源極-汲極間的漏電流路徑。所以,為製作HEMT元件,最好利用半絕緣性GaN基板。
為實現半絕緣性GaN基板,已知將過渡金屬元素(例如Fe)、第IIA族元素(例如Mg)之類形成深受體能階的元素,摻雜於GaN結晶中係屬有效。
第IIA族元素中,藉由選擇鋅元素(Zn),便可實現高品質的半絕緣性GaN單晶基板,此已屬公知事實(例如參照專利文獻1)。相關GaN結晶中的Zn元素擴散尚未有調查,在高溫環境下發生擴散,且擴散容易度係依存於GaN結晶的結晶性(例如參照非專利文獻4)。又,在基板上形成經摻雜過渡金屬元素之鐵(Fe)的高電阻層,更在該高電阻層與電子走行層之間形成Fe取入效果較高的中間層,藉此防止Fe進入於電子走行層的態樣亦屬公知(例如參照專利文獻2)。
已然有在半絕緣性GaN基板上、或具半絕緣性GaN膜之基板上製作HEMT構造,並針對諸項特性施行評價(例如參照非專利文獻1至非專利文獻3)。
在經摻雜過渡金屬元素或第IIA族元素而成的半絕緣性GaN單晶基板上,進行磊晶成長GaN膜而形成半導體元件用磊晶基板時,Fe、Mg、Zn等受體元素會擴散於GaN膜中,因為在膜中呈現電子陷阱(electron-trap)的作用,因而會有發生電流崩塌(current collapse)現象的問題。
[先行技術文獻]
[專利文獻]
[專利文獻1]日本專利第5039813號公報
[專利文獻2]日本專利特開2013-74211號公報
[非專利文獻]
[非專利文獻1]Yoshinori Oshimura, Takayuki Sugiyama, Kenichiro Takeda, Motoaki Iwaya, Tetsuya Takeuchi, Satoshi Kamiyama, Isamu Akasaki, and Hiroshi Amano, "AlGaN/GaN Heterostructure Field-Effect Transistors on Fe-Doped GaN Substrates with High Breakdown Voltage", Japanese Journal of Applied Physics, vol.50 (2011), p.084102-1-p.084102-5.
[非專利文獻2]V. Desmaris, M. Rudzinski, N. Rorsman, P.R. Hageman, P.K. Larsen, H. Zirath, T.C. Rodle, and H.F.F. Jos, "Comparison of the DC and Microwave Performance of AlGaN/GaN HEMTs Grown on SiC by MOCVD With Fe-Doped or Unintentionally Doped GaN Buffer Layers", IEEE Transactions on Electron Devices, Vol.53, No.9, pp.2413-2417,
September 2006.
[非專利文獻3]M. Azize, Z. Bougrioua, and P. Gibart, "Inhibition of interface pollution in AlGaN/GaN HEMT structures regrown on semi-insulating GaN templates", Journal of Crystal Growth, vol.299 (2007), p.103-p.108.
[非專利文獻4]T. Suzuki, J. Jun, M. Leszczynski, H. Teisseyre, S. Strite, A. Rockett, A. Pelzmann, M. Camp, and K. J. Ebeling, "Optical actvation and diffusivity of ion-implanted Zn acceptors in GaN under high-pressure, high-temperature annealing", Journal of Applied Physics, Vol.84 (1998), No.2, pp.1155-1157.
本發明係有鑑於上述課題而完成,目的在於提供:經抑制電流崩塌發生的半導體元件用磊晶基板。
為解決上述課題,本發明第1態樣的半導體元件用磊晶基板,係包括:由經摻雜Zn的GaN所構成半絕緣性獨立式基板、鄰接上述獨立式基板的緩衝層、鄰接上述緩衝層的通道層、以及設置於上述緩衝層對向側呈夾置上述通道層狀態的障壁層;上述緩衝層係抑制Zn從上述獨立式基板擴散於上述通道層的擴散阻障層。
本發明第2態樣係就第1態樣的半導體元件用磊晶基板,其中,上述緩衝層係厚度方向至少其中一部分範圍由依1×1018cm-3以上濃度摻雜C,而成的第IIIA族氮化物層。
本發明第3態樣係就第2態樣的半導體元件用磊
晶基板,其中,上述第IIIA族氮化物層係GaN層。
本發明第4態樣係就第2態樣的半導體元件用磊晶基板,其中,上述第IIIA族氮化物層係由相異組成的2以上第IIIA族氮化物層積層而成,且上述2以上第IIIA族氮化物層中之至少一層係由經C依1×1018cm-3以上濃度摻雜而成的多層緩衝層、或者由含2或以上之第IIIA族元素的第IIIA族氮化物所構成,且第IIIA族元素的存在比率在厚度方向有變化的成分梯度緩衝層。
本發明第5態樣係就第2至4態樣中任一態樣之半導體元件用磊晶基板,其中,上述通道層的Zn濃度係1×1016cm-3以下。
本發明第6態樣係就第2至4態樣中任一態樣之半導體元件用磊晶基板,其中,上述通道層係由GaN構成,上述障壁層係由AlGaN構成。
本發明第7態樣的半導體元件,係包括:由經摻雜Zn的GaN所構成半絕緣性獨立式基板、鄰接上述獨立式基板的緩衝層、鄰接上述緩衝層的通道層、設置於上述緩衝層對向側呈夾置上述通道層狀態的障壁層、以及在上述障壁層上設置的閘極、源極及汲極;其中,上述緩衝層係抑制Zn從上述獨立式基板擴散於上述通道層的擴散阻障層。
本發明第8態樣係就第7態樣的半導體元件,其中,上述緩衝層係厚度方向至少其中一部分範圍由依1×1018cm-3以上濃度摻雜C,而成的第IIIA族氮化物層。
本發明第9態樣係就第8態樣的半導體元件,其
中,上述第IIIA族氮化物層係GaN層。
本發明第10態樣係就第8態樣的半導體元件,其中,上述第IIIA族氮化物層係由相異組成的2以上第IIIA族氮化物層積層而成,且上述2以上第IIIA族氮化物層中之至少一層係由經C依1×1018cm-3以上濃度摻雜而成的多層緩衝層、或者由含2或以上之第IIIA族元素的第IIIA族氮化物所構成,且第IIIA族元素的存在比率在厚度方向有變化的成分梯度緩衝層。
本發明第11態樣係就第8至第10態樣中任一態樣之半導體元件,其中,上述通道層的Zn濃度係1×1016cm-3以下。
本發明第12態樣係就第8至第10態樣中任一態樣之半導體元件,其中,上述通道層係由GaN構成,上述障壁層係由AlGaN構成。
本發明第13態樣的製造半導體元件用磊晶基板之方法,係包括:a)準備由經摻雜Zn的GaN所構成半絕緣性獨立式基板的準備步驟;b)鄰接上述獨立式基板形成緩衝層的緩衝層形成步驟;c)鄰接上述緩衝層形成通道層的通道層步驟;以及d)在位於上述緩衝層對向側位置處呈夾置上述通道層狀態形成障壁層的障壁層形成步驟;其中,緩衝層形成步驟中,所形成的上述緩衝層係抑制Zn從上述獨立式基板擴散於上述通道層的擴散阻障層。
本發明第14態樣係就第13態樣的半導體元件用磊晶基板之製造方法,其中,緩衝層形成步驟中,藉由上述緩
衝層係厚度方向至少其中一部分範圍係經C依1×1018cm-3以上濃度摻雜的第IIIA族氮化物層形成,而抑制Zn從上述獨立式基板擴散於上述通道層。
本發明第15態樣係就第14態樣的半導體元件用磊晶基板之製造方法,其中,上述第IIIA族氮化物層係由GaN形成。
本發明第16態樣係就第14態樣的半導體元件用磊晶基板之製造方法,其中,上述第IIIA族氮化物層係由至少一層經C依1×1018cm-3以上濃度摻雜且相異組成的2以上第IIIA族氮化物層積層而形成多層緩衝層、或者由含2或以上之第IIIA族元素的第IIIA族氮化物所構成,且形成第IIIA族元素的存在比率在厚度方向有變化的成分梯度緩衝層。
本發明第17態樣係就第14至第16態樣中任一態樣之半導體元件用磊晶基板之製造方法,其中,上述緩衝層形成步驟中,依上述通道層的Zn濃度成為1×1016cm-3以下的方式,由上述第IIIA族氮化物層形成上述緩衝層。
本發明第18態樣係就第14至第16態樣中任一態樣之半導體元件用磊晶基板之製造方法,其中,上述通道層係由GaN構成,上述障壁層係由AlGaN形成。
本發明第19態樣係就第13至第16態樣中任一態樣之半導體元件用磊晶基板,其中,上述獨立式基板係依通量法製作。
根據本發明第1至第19態樣,在使用半絕緣性GaN獨立式基板狀態下,實現經減輕電流崩塌地半導體元件。
1‧‧‧獨立式基板
2‧‧‧緩衝層
3‧‧‧通道層
4‧‧‧障壁層
5‧‧‧源極
6‧‧‧汲極
7‧‧‧閘極
10‧‧‧磊晶基板
20‧‧‧HEMT元件
圖1係HEMT元件20的截面構造示意圖。
圖2係實施例1的磊晶基板中,Zn元素、C元素的濃度分佈圖。
圖3係圖2中,GaN緩衝層與GaN基板的界面附近之放大圖。
圖4係比較例1的磊晶基板中,Zn元素、C元素的濃度分佈圖。
圖5係圖4中,摻雜C之GaN緩衝層與GaN基板的界面附近之放大圖。
圖6係實施例7中,距障壁層4表面的深度方向Zn元素與C元素之濃度分佈圖。
圖7係實施例8中,距障壁層4表面的深度方向Zn元素與C元素之濃度分佈、及Al元素的二次離子訊號分佈圖。
本說明書中所示週期表的族編號係根據1989年國際理論與應用化學聯合會(International Union of Pure Applied Chemistry:IUPAC)的無機化學命名法修訂版之第IA~VIIIA族編號表示,第IIIA族係指鋁(Al)、鎵(Ga)、銦(In)等,第IVA族係指矽(Si)、鍺(Ge)、錫(Sn)、鉛(Pb)等,第VA族係指氮(N)、磷(P)、砷(As)、銻(Sb)等。
<磊晶基板及HEMT元件之概要>
圖1係含有本發明半導體元件用磊晶基板一實施形態之磊
晶基板10所構成,本發明半導體元件一實施形態的HEMT元件20之截面構造示意圖。
磊晶基板10係包括:獨立式基板1、緩衝層2、通道層3及障壁層4。又,HEMT元件20係在磊晶基板10上(障壁層4上)設有源極5、汲極6及閘極7。另外,圖1中的各層厚度比率並非反映實際狀態。
獨立式基板1係經Zn摻雜1×1018cm-3以上的(0001)面方位GaN基板,在室溫下呈比電阻1×102Ωcm以上的半絕緣性。獨立式基板1的尺寸並無特別的限制,若考慮處置(握持、移動等)的容易度等,較佳係具有數百μm~數mm程度的厚度。該獨立式基板1係例如可利用通量(Flux)法製作。
利用通量法進行的獨立式基板1之形成,概略係在耐壓容器內呈水平旋轉自如配置的育成容器(氧化鋁坩堝)內,將種子基板浸漬於含有金屬Ga、金屬Na、金屬Zn、及C(碳)的熔液中,在使育成容器進行水平旋轉狀態下,藉由一邊導入氮氣、一邊將育成容器內保持既定溫度與既定壓力,而將在種子基板上所形成的GaN單晶,從種子基板上分離便可獲得。種子基板最好使用利用MOCVD法在藍寶石基板上形成GaN薄膜之所謂模板基板等。
緩衝層2係在獨立式基板1其中一主面上(鄰接)形成之具有50nm~1000nm程度厚度的層。本實施形態中,緩衝層2係不同於所謂依未滿800℃低溫形成之所謂低溫緩衝層,而是依照與通道層3、障壁層4之形成溫度相同程度的溫度形成。
本實施形態的磊晶基板10中,緩衝層2係設計成在製作於獨立式基板1中摻雜Zn形成的磊晶基板10時,抑制擴散於通道層3甚至其上方障壁層4的擴散阻障層。緩衝層2較佳一例係在厚度方向至少其中一部分的範圍內,由經依1×1018cm-3以上濃度摻雜C的第IIIA族氮化物所構成的層形成。
此情況,緩衝層2亦可全體在由單一第IIIA族氮化物所構成單一層中,依1×1018cm-3以上濃度摻雜C而成者,亦可在由不同組成的2以上第IIIA族氮化物層所構成多層緩衝層之至少一層中,依1×1018cm-3以上濃度摻雜C而成者。單一層係可例示全體由GaN構成的GaN緩衝層(摻雜C之GaN層)等。多層緩衝層係可例示如在AlaGa1-aN層(0<a≦1)上積層著摻雜C之GaN層的構成等。或者,緩衝層2亦可由含有2或以上之第IIIA族元素(例如Ga與Al)的第IIIA族氮化物構成,且各元素的存在比率(莫耳分率)在厚度方向有變化之成分梯度緩衝層,且藉由在厚度方向至少其中一部分範圍內依1×1018cm-3以上濃度摻雜C而設置。相關緩衝層2所衍生的效果,容後述。
或者,亦可為由經摻雜Al的GaN所構成的層(摻雜Al之GaN層)、由AlN所構成的層,形成緩衝層2之態樣。相關該等層亦是與摻雜C之GaN層同樣,具有擴散阻障層的功能。
通道層3係在緩衝層2上(鄰接)形成的層。通道層3係形成50nm~5000nm程度的厚度。又,障壁層4係設置在緩
衝層2的對向側設計成夾置通道層3狀態的層。障壁層4係形成2nm~40nm程度的厚度。
障壁層4係如圖1所示,亦可鄰接通道層3形成,此情況,二層的界面成為異質接面界面。或者,亦可在通道層3與障壁層4之間設置未圖示的間隔層,此情況,從通道層3與間隔層的界面起至障壁層4與間隔層的界面間之區域便成為異質接面界面區域。
任一情況的較佳一例均係通道層3由GaN形成,障壁層4由AlGaN(AlxGa1-xN、0<x<1)或InAlN(InyAl1-yN、0<y<1)形成。但,通道層3與障壁層4的組合並不僅侷限於此。
緩衝層2、通道層3、及障壁層4的形成係例如利用MOCVD法實現。利用MOCVD法進行的層形成係例如當緩衝層2與通道層3由GaN形成,而障壁層4由AlGaN形成的情況,便使用構成可將相關Ga、Al的有機金屬(MO)原料氣體(TMG、TMA)、氨氣、氫氣、以及氮氣,供應給反應器內的公知MOCVD爐,於將反應器內所載置的獨立式基板1加熱至既定溫度狀態,使藉由使各層所對應的有機金屬原料氣體、與氨氣進行氣相反應,而生成的GaN結晶、AlGaN結晶,依序沉積於獨立式基板1上而實施。
源極5與汲極6分別係具有十數nm~百數十nm程度厚度的金屬電極。源極5與汲極6最好係例如形成由Ti/Al/Ni/Au所構成的多層電極。源極5與汲極6係在與障壁層4之間具有歐姆性接觸。源極5與汲極6較佳一例係利用真
空蒸鍍法與光學微影製程形成。另外,為提升二電極的歐姆性接觸,最好在電極形成後,於650℃~1000℃間的既定溫度氮氣環境中施行數十秒鐘的熱處理。
閘極7分別係具有十數nm~百數十nm程度厚度的金屬電極。閘極7最好係例如由Ni/Au所構成多層電極形成。閘極7係在與障壁層4之間具有肖特基性接觸。閘極7較佳一例係利用真空蒸鍍法與光學微影製程形成。
<磊晶基板及HEMT元件之製作方法>
(獨立式基板之製作)
首先,針對利用通量法進行的獨立式基板1之製作順序進行說明。
首先準備具有與所欲製作獨立式基板1的直徑為同程度直徑之c面藍寶石基板,在其表面上,依450℃~750℃溫度形成10nm~50nm程度厚度的GaN低溫緩衝層,然後,於1000℃~1200℃溫度下,利用MOCVD法形成厚度1μm~10μm程度的GaN薄膜,便獲得可利用為種子基板的MOCVD-GaN模板。
其次,以所獲得MOCVD-GaN模板為種子基板,利用Na通量法形成摻雜Zn之GaN單晶層。
具體而言,首先在氧化鋁坩堝內載置MOCVD-GaN模板,接著在該氧化鋁坩堝內分別填充入金屬Ga:10g~60g、金屬Na:15g~90g、金屬Zn:0.1g~5g、C:10mg~500mg。
將該氧化鋁坩堝放入加熱爐中,將爐內溫度設為800℃~950℃,並將爐內壓力設為3MPa~5MPa,施行20小時
~400小時左右的加熱,然後冷卻至室溫。經冷卻結束後,從爐內取出氧化鋁坩堝。依照以上順序,獲得表面上依300μm~3000μm厚度沉積褐色GaN單晶層的MOCVD-GaN模板。
依此所獲得GaN單晶層使用鑽石磨粒施行研磨,使表面平坦化。藉此獲得在MOCVD-GaN模板上形成GaN單晶層的Flux-GaN模板。其中,研磨係依Flux-GaN模板的氮化物層總厚度,保持充分大於最終所欲獲得獨立式基板1之目標厚度值的範圍實施。
其次,利用雷射剝離法,從種子基板側將雷射光依0.1mm/秒~100mm/秒的掃描速度進行掃描並照射,而從Flux-GaN模板分離出種子基板。雷射光最好使用例如波長355nm之Nd:YAG三次諧波。該情況,脈衝寬係只要1ns~1000ns、脈衝週期係1kHz~200kHz程度便可。照射時,最好將雷射光進行適當聚光,而調整光密度。又,雷射光的照射最好在針對Flux-GaN模板從種子基板的對向側依30℃~600℃程度的溫度施行加熱狀態下實施。
經分離出種子基板後,針對從所獲得積層構造體的種子基板剝離之一側的面施行研磨處理。藉此,獲有由經依1×1018cm-3以上濃度摻雜Zn的GaN所構成獨立式基板1。
(磊晶基板之製作)
接著,針對利用MOCVD法施行的磊晶基板10之製作進行說明。磊晶基板10係在將獨立式基板1載置於MOCVD爐的反應器內所設置承載器上的狀態下,依照下述條件依序積層
形成緩衝層2、通道層3、及障壁層4而獲得。其中,相關緩衝層2係例示形成單一GaN緩衝層、或含有第IIIA族元素之Ga與Al的多層緩衝層、或成分梯度緩衝層的情況。另外,形成溫度係指承載器加熱溫度。
另外,本實施形態中,所謂「第VA族/第IIIA族氣體比」係指第VA族(N)原料的氨供應量,相對於第IIIA族(Ga、Al、In)原料的TMG(三甲基鎵)、TMA(三甲基鋁)、及TMI(三甲基銦)總供應量之比(莫耳比)。又,障壁層4係由AlGaN形成時的Al原料氣體/第IIIA族原料氣體比,係Al原料供應量相對於第IIIA族(Ga、Al)原料全體供應量的比(莫耳比),當障壁層4係由InAlN形成時的Al原料氣體/第IIIA族原料氣體比,係In原料供應量相對於第IIIA族(In、Al)原料全體供應量的比(莫耳比)。且,配合所需障壁層4的組成(Al莫耳比x或In組成比y)而決定。
緩衝層2:形成溫度=900℃~1100℃;反應器內壓力=5kPa~30kPa;載氣=氫;第VA族/第IIIA族氣體比=100~4000;Al原料氣體/第IIIA族原料氣體比=0(GaN緩衝層的情況);Al原料氣體/第IIIA族原料氣體比=依0~1範圍對應於厚度方向的位置(多層緩衝層或成分梯度緩衝層的情況)。
通道層3:形成溫度=1000℃~1200℃;
反應器內壓力=15kPa~105kPa;載氣=氫;第VA族/第IIIA族氣體比=1000~10000。
障壁層4(由AlGaN形成的情況):形成溫度=1000℃~1200℃;反應器內壓力=1kPa~30kPa;第VA族/第IIIA族氣體比=5000~20000;載氣=氫;Al原料氣體/第IIIA族原料氣體比=0.1~0.4。
障壁層4(由InAlN形成的情況):形成溫度=700℃~900℃;反應器內壓力=1kPa~30kPa;第VA族/第IIIA族氣體比=2000~20000;載氣=氮;In原料氣體/第IIIA族原料氣體比=0.1~0.9。
(HEMT元件之製作)
使用磊晶基板10的HEMT元件20之製作,係藉由使用公知技術便可實現。
例如使用光學微影製程與RIE(Reactive Ion Etching,反應性離子蝕刻)法,施行將各個元件成為邊界的部位利用蝕刻除去至50nm~1000nm程度的元件分離處理後,在磊晶基板10的表面(障壁層4的表面)上形成厚度50nm~500nm的SiO2膜,接著使用光學微影將預定形成源極5與汲極6地方的SiO2膜予以蝕刻除去,而獲得SiO2圖案層。
接著,使用真空蒸鍍法與光學微影製程,在預定形成源極5與汲極6的地方,形成由Ti/Al/Ni/Au所構成金屬圖案,藉此形成源極5與汲極6。各個金屬層的厚度依序較佳係設為5nm~50nm、40nm~400nm、4nm~40nm、及20nm~200nm。
然後,為使源極5與汲極6的歐姆性呈良好,便在600℃~1000℃氮氣環境中施行10秒鐘~1000秒鐘的熱處理。
接著,使用光學微影製程,從SiO2圖案層中,除去閘極7預定形成地方的SiO2膜。
再者,使用真空蒸鍍法與光學微影製程,藉由在閘極7預定形成地方形成由Ni/Au所構成肖特基性金屬圖案,而形成閘極7。各金屬層的厚度較佳係設為4nm~40nm及20nm~200nm。
利用以上製程,獲得HEMT元件20。
(緩衝層之效果)
依如上述,本實施形態的HEMT元件20中,獨立式基板1係由Zn依1×1018cm-3以上濃度摻雜的GaN所構成,且緩衝層2係為在磊晶基板10製作時,發揮防止Zn從獨立式基板1擴散於通道層3的擴散阻障層功能而設置。而,該緩衝層2係例示在厚度方向至少其中一部分範圍,依1×1018cm-3以上濃度摻雜C的第IIIA族氮化物所構成之層。
假設C未依如上述濃度條件摻雜於緩衝層2的情況,Zn會從緩衝層2擴散於通道層3(甚至擴散於障壁層4)。此情況,具受體元素功能的Zn便會產生電子陷阱的作用,致使HEMT元件20發生電流崩塌現象。
然而,本實施形態的HEMT元件20,藉由發現上述濃度條件,利用經摻雜C的第IIIA族氮化物層形成緩衝層2,而抑制Zn從獨立式基板1擴散,結果適當地抑制發生電流崩塌。更具體而言,若通道層的Zn濃度在1×1016cm-3以下,便可適當地抑制HEMT元件20發生電流崩塌。
另外,緩衝層2厚度方向至少其中一部分範圍依1×1018cm-3以上濃度的C摻雜,當利用MOCVD法形成第IIIA族氮化物層時,藉由適當調整該層的形成條件(例如成長溫度、反應器內壓力、第VA族氣體與第IIIA族氣體的氣體比、形成厚度等),便可使C濃度變化。另外,在依照MOCVD法所形成結晶層中摻雜的C,主要係源自第IIIA族原料,例如C供應量係利用第IIIA族氣體供應量變化,又,第IIIA族氮化物結晶中的C元素安定性係受溫度及壓力的影響。
所以,在獲得本實施形態的HEMT元件20時,於形成緩衝層2之際,便可採取在厚度方向至少其中一部分範圍處,將C依1×1018cm-3以上濃度摻雜的成長條件,而在形成通道層3之際,便可採取未施行該摻雜的成長條件(例如C濃度較緩衝層2小二階或三階或以上的成長條件)。
依上述所說明,根據本實施形態,使用反絕緣性GaN獨立式基板,可獲得經抑制發生電流崩塌的半導體元件。
[實施例]
(實施例1)
[利用通量法所進行摻雜Zn之GaN單晶基板的製作]
在直徑2吋、厚度0.43mm的c面藍寶石基板表面上,於
550℃下形成30nm的GaN低溫緩衝層,然後於1050℃下利用MOCVD法形成厚度3μm的GaN薄膜,便獲得可利用為種子基板的MOCVD-GaN模板。
以所獲得MOCVD-GaN模板為種子基板,利用Na通量法形成摻雜Zn之GaN單晶層。
具體而言,首先在氧化鋁坩堝內載置MOCVD-GaN模板,接著在該氧化鋁坩堝內分別填充入金屬Ga:30g、金屬Na:45g、金屬鋅:1g、以及碳:100mg。該氧化鋁坩堝放入加熱爐中,將爐內溫度設為850℃、爐內壓力設為4.5MPa,施行約100小時的加熱,然後冷卻至室溫。待冷卻結束後,從爐內取出氧化鋁坩堝,便在MOCVD-GaN模板的表面依約1000μm厚度沉積褐色GaN單晶層。
針對依此所獲得GaN單晶層,使用鑽石磨粒施行研磨而使表面平坦化,且使在底層基板上所形成氮化物層的總厚成為900μm狀態。藉此獲得在MOCVD-GaN模板上形成GaN單晶層的Flux-GaN模板。另外,經肉眼觀察該Flux-GaN模板,並無發現到龜裂。
其次,利用雷射剝離法,將雷射光從種子基板之一側依30mm/秒的掃描速度進行掃描且照射,藉此從Flux-GaN模板上分離出種子基板。雷射光係使用波長355nm的Nd:YAG三次諧波。脈衝寬設為約30ns、脈衝週期設為約50kHz。照射時,藉由將雷射光施行聚光而形成直徑約20μm的圓形狀光束,藉此使光密度成為1.0J/cm程度。又,雷射光的照射係在將Flux-GaN模板從種子基板對向側依50℃前後溫度施行加熱
狀態下實施。
經分離種子基板後,藉由將所獲得積層構造體的種子基板從剝離之一側的面施行研磨處理,便獲得總厚430μm的摻雜Zn之GaN獨立式基板。
針對所獲得摻雜Zn之GaN基板的結晶性,使用X射線搖擺曲線施行評價。(0002)面反射的半值寬係120秒,(10-12)面反射的半值寬係150秒,呈現良好結晶性。
[利用MOCVD法進行的磊晶基板之製作]
接著,利用MOCVD法製作磊晶基板。具體而言,依照以下條件在上述摻雜Zn之GaN基板上,依序積層形成:緩衝層之GaN層、通道層之GaN層、障壁層之AlGaN層。另外,本實施形態中,所謂「第VA族/第IIIA族氣體比」係指第VA族(N)原料供應量,相對於第IIIA族(Ga、Al)原料供應量之比(莫耳比)。又,GaN緩衝層的形成條件係預先確認依高濃度摻雜C的條件,GaN通道層的形成條件係預先確認幾乎沒有摻雜C的條件。
GaN緩衝層:形成溫度=1050℃;反應器內壓力=10kPa;第VA族/第IIIA族氣體比=500;厚度=1000nm。
GaN通道層:形成溫度=1050℃;反應器內壓力=100kPa;
第VA族/第IIIA族氣體比=2000;厚度=1000nm。
AlGaN障壁層:形成溫度=1050℃;反應器內壓力=5kPa;第VA族/第IIIA族氣體比=12000;Al原料氣體/第IIIA族氣體比=0.25;厚度=25nm。
經形成以上的層之後,將承載器溫度降溫至室溫附近,使反應器內回歸至大氣壓後,取出所製作的磊晶基板。
[HEMT元件之製作]
其次,使用該磊晶基板10製作HEMT元件20。另外,HEMT元件係設計成:閘極幅100μm、源極-閘極間隔1μm、閘極-汲極間隔4μm、閘極長1μm狀態。
首先,使用光學微影製程與RIE法,將成為各元件邊界的部位施行蝕刻除去至深度100nm左右。
其次,在磊晶基板上形成厚度100nm的SiO2膜,接著使用光學微影將預定形成源極、汲極地方的SiO2膜予以蝕刻除去,而獲得SiO2圖案層。
其次,使用真空蒸鍍法與光學微影製程,藉由在預定形成源極、汲極的地方,形成由Ti/Al/Ni/Au(膜厚分別係25/200/20/100nm)所構成的金屬圖案,而形成源極及汲極。接著,為使源極及汲極的歐姆性呈良好,便在825℃氮氣環境中施行30秒鐘的熱處理。
然後,使用光學微影製程,從SiO2圖案層除去預定形成閘極地方的SiO2膜。
再者,使用真空蒸鍍法與光學微影製程,藉由在預定形成閘極的地方,形成由Ni/Au(膜厚分別係20/100nm)所構成的肖特基性金屬圖案,而形成閘極。
依照以上製程便可獲得HEMT元件。
[HEMT元件之SIMS評價]
針對所獲得HEMT元件,利用SIMS(二次離子質量分析法)施行磊晶基板深度方向的元素分析,調查Zn元素與C元素的濃度。
圖2所示係本實施例磊晶基板中,Zn元素、C元素的濃度分佈圖。圖3所示係圖2中,GaN緩衝層與GaN基板之界面附近的放大圖。由圖2與圖3所示結果得知以下事項。
(1)在GaN基板中Zn元素呈高濃度(3×1018cm-3)摻雜。
(2)因為C元素濃度在GaN緩衝層中達6×1018cm-3以上,因而存在1×1018cm-3以上範圍,通道層則約在1×1016cm-3以下。
(3)從GaN緩衝層與GaN基板的界面起至基板側依高濃度存在的Zn元素,在GaN緩衝層內急遽減少,SIMS(Secondary Ion Mass Spectrometry,二次離子質譜)測定,到達Zn檢測下限值的5×1014cm-3。即,抑制Zn元素擴散至通道層與障壁層內。
(4)Zn濃度1×1017cm-3地方的Zn濃度每1μm之對
數變化率(濃度常用對數值的變化率)係-74.9。
[HEMT元件之電氣特性評價]
使用半導體參數分析儀,利用DC模式及脈衝模式(靜態汲極偏壓Vdq=30V、靜態閘極偏壓Vgq=-5V)評價HEMT元件的汲極電流-汲極電壓特性(Id-Vd特性)。夾止(pinch-off)臨限值電壓係Vg=-3V。
供評價電流崩塌用的指標係採用施加汲極電壓Vd=5V、閘極電壓Vg=2V施加時DC模式的汲極電流IdDC.Vd=5V.Vg=2v、與脈衝模式的汲極電流Idpulse.vd=5v.vg=2V之比R(=Idpulse.vd=5v.Vg=2v/IdDC.vd=5v.vg=2v、0≦R≦1),針對本實施例的HEMT元件進行求取,結果為0.93。若該R值達0.7以上便可判定電流崩塌少,因而本實施例的HEMT元件可判定為電流崩塌少。
(比較例1)
除GaN緩衝層的成長條件設為不同於實施例1的以下條件之外,其餘均依照與實施例1同樣的條件施行HEMT元件之製作。另外,GaN緩衝層的形成條件係預先確認C摻雜量較小於實施例1的條件。
GaN緩衝層:形成溫度=1050℃;反應器內壓力=30kPa;第VA族/第IIIA族氣體比=500;厚度=300nm。
針對所獲得HEMT元件,依照與實施例1同樣地
施行SIMS測定,調查磊晶基板的Zn元素與C元素之濃度。
圖4所示係本比較例的磊晶基板中,Zn元素、C元素的濃度分佈圖。圖5所示係圖4中,摻雜C之GaN緩衝層與GaN基板的界面附近之放大圖。由圖4與圖5所示結果得知以下事項。
(1)依照與實施例1同樣地在GaN基板中高濃度摻雜Zn元素。
(2)C元素的濃度係在GaN緩衝層最大為2×1017cm-3以上程度,較高於其他區域的濃度,但較低於實施例1,依照與實施例1相同條件所形成GaN通道層的C元素濃度,較高於實施例1成為4×1016cm-3程度。
(3)從GaN緩衝層與GaN基板的界面起至基板側依高濃度存在的Zn元素,雖在GaN緩衝層內呈減少狀態,但減少程度較實施例1緩和,即便在GaN通道層中亦是依照較實施例1情況大2階的5×1016cm-3以上濃度存在。即,Zn元素擴散至通道層。
(4)Zn濃度1×1017cm-3地方的Zn濃度每1μm之對數變化率(濃度常用對數值的變化率)係-7.3。
針對該HEMT元件,經依照與實施例1同樣的條件求取R值,結果係0.31,判定本比較例HEMT元件的電流崩塌抑制不足。
(實施例2~6、比較例2~5)
除將GaN緩衝層的成長條件(成長溫度、反應器內壓力、第VA族/第IIIA族氣體比、形成厚度)等改變為各種條件之
外,其餘均依照與實施例1同樣的條件施行HEMT元件之製作,並針對所獲得HEMT元件,利用SIMS測定求取深度方向上的Zn濃度與C濃度分佈,計算出R值。
所獲得結果一覽合併實施例1、比較例1的結果整理於表1中。
如表1所示,依照GaN緩衝層的C濃度成為1×1018cm-3以上的條件進行製作的實施例1~實施例6之情況,R值達0.85以上、GaN通道層的Zn濃度在1×1015cm-3以下。此項結果顯示實施例1~實施例6均可獲得經抑制電流崩塌的HEMT元件。
再者,Zn濃度1×1017cm-3地方的Zn濃度每1μm之對數變化率係成為-20.0以下的值。此現象表示實施例1~實施例6均係Zn濃度減少呈急遽狀態。
另一方面,依GaN緩衝層的C濃度未滿1×1018cm-3之條件進行製作的比較例1~比較例5之情況,R值最大亦停滯於0.51,GaN通道層的Zn濃度係除比較例2之外,其餘均大於1×1016cm-3。此項結果表示比較例1~比較例5的HEMT元件之電流崩塌並未獲抑制。
再者,就Zn濃度1×1017cm-3地方的Zn濃度每1μm之對數變化率,雖比較例1獲得-8.9、比較例2獲得-7.3的值,但比較例3~比較例5因為Zn濃度低於1×1017cm-3,因而無法計算。此項結果表示比較例1~比較例5相較於實施例1~實施例6之下,Zn的濃度減少較為緩和。
(實施例7)
實施例1~實施例6的HEMT元件係Zn濃度減少呈急遽狀態,所以通道層的Zn濃度低於1×1016cm-3,電流崩塌受抑制,但通道層中在障壁層與通道層的界面(異質界面)附近,若Zn濃度為1×1016cm-3的充分低狀態,則即便Zn濃度減少緩和,但仍會有電流崩塌受抑制的情況。
本實施例中,除將緩衝層2與通道層3的成長條件設為不同於實施例1的以下條件之外,其餘均依照與實施例1同樣的條件施行磊晶基板10的製作、及HEMT元件20的製作。
GaN緩衝層:形成溫度=1050℃;反應器內壓=10kPa;第VA族/第IIIA族氣體比=500;厚度=100nm。
GaN通道層:形成溫度=1050℃;反應器內壓=100kPa;第VA族/第IIIA族氣體比=2000;厚度=1000nm。
圖6所示係針對所獲得HEMT元件,依照與實施例1同樣的條件利用SIMS測定朝深度方向施行測定,所獲得距障壁層4之表面(上面)朝深度方向的Zn元素及C元素濃度分佈圖。由圖6所示結果得知以下事項。
(1)在GaN基板中高濃度摻雜Zn元素。
(2)C元素的濃度在緩衝層中,存在於從最大的3×1018cm-3起至1×1018cm-3以上範圍內,在通道層則大約在2×1016cm-3以下。又,C元素的濃度變化係在緩衝層與通道層的界面處呈現急遽狀態,相對的從緩衝層起至GaN基板的濃度變化則較為緩和。另外,圖6中,雖從障壁層附近起至障壁
層有發現C元素濃度增加,但此現象係因為樣品表面上所附著元素的碰撞造成。
(3)從緩衝層與GaN基板的界面起至基板側依高濃度存在的Zn元素,在緩衝層內急遽減少,在通道層內更加減少,在涵蓋障壁層與通道層的界面(異質界面)附近範圍在內,到達SIMS測定時的Zn檢測下限值之5×1014cm-3。即,Zn元素的擴散獲抑制。
(4)Zn濃度1×1017cm-3地方的Zn濃度每1μm之對數變化率(濃度常用對數值的變化率)係-15.0。
針對該HEMT元件求取R值,結果係0.88。即,判定本實施例的HEMT元件亦是電流崩塌受較佳抑制。
(實施例8)
除將緩衝層2與通道層3的成長條件設為不同於實施例1的以下條件之外,其餘均依照與實施例1同樣的條件施行磊晶基板10的製作、以及HEMT元件20的製作。其中,在緩衝層2形成時,將形成條件設定為第1條件與第2條件等二階段,在形成途中從第1條件切換為第2條件。此係為使緩衝層2形成在AlaGa1-aN層(0<a≦1)上積層著GaN層的多層緩衝層、或形成厚度方向上的Al與Ga存在比率不同之成分梯度緩衝層,而刻意為之。此處,第1條件係使C未積極摻雜於緩衝層2內的條件,第2條件係確認C有摻雜於緩衝層2內的條件。另外,緩衝層2的總厚度係設為110nm。
緩衝層(第1條件):形成溫度=1050℃;
反應器內壓=5kPa;第IIIA族原料氣體=Al原料及Ga原料;第VA族/第IIIA族氣體比=2000;Al原料氣體/第IIIA族原料氣體比=0.03;成長速率=1nm/秒;成長時間=10秒。
緩衝層(第2條件):形成溫度=1050℃;反應器內壓=10kPa;第IIIA族原料氣體=Ga原料;第VA族/第IIIA族氣體比=500;成長速率=1nm/秒;成長時間=100秒。
GaN通道層:形成溫度=1050℃;反應器內壓=100kPa;第VA族/第IIIA族氣體比=2000;厚度=900nm。
圖7所示係針對所獲得HEMT元件,依照與實施例1同樣的條件,利用SIMS測定朝深度方向施行測定,而獲得距障壁層4之表面(上面)朝深度方向的Zn元素、C元素的濃度分佈,以及該深度方向上的Al元素之二次離子訊號分佈(Al元素的二次離子計數率之深度方向分佈)圖。由圖7所示結果得知以下事項。
(1)在GaN基板中高濃度摻雜Zn元素。
(2)C元素的濃度在緩衝層中,存在於從最大的6×1018cm-3起至1×1018cm-3以上範圍內,在通道層則大約在1×1016cm-3以下。又,C元素的濃度變化係在緩衝層與通道層的界面處呈現急遽狀態,相對的從緩衝層起至GaN基板的濃度變化則較為緩和。另外,圖7中,雖從障壁層附近起至障壁層有發現C元素濃度增加,但此現象係因為樣品表面上所附著元素的碰撞造成。
(3)從緩衝層與GaN基板的界面起至基板側依高濃度存在的Zn元素,在緩衝層內急遽減少,在通道層內更加減少,在涵蓋障壁層與通道層的界面(異質界面)附近範圍在內,到達SIMS測定時的Zn檢測下限值之5×1014cm-3。即,Zn元素的擴散獲抑制。
(4)Zn濃度1×1017cm-3地方的Zn濃度每1μm之對數變化率(濃度常用對數值的變化率)係-13.0。
(5)Al元素係存在於較緩衝層全體目標厚度110nm更寬範圍,該範圍亦涵蓋GaN基板其中一部分。
(6)緩衝層中,在C元素濃度最大的區域中幾乎沒有檢測到Al元素,因而可謂緩衝層存在有:明顯摻雜C的GaN層、與些微摻雜C的AlGaN層。
針對該HEMT元件求取R值,結果係0.90。即,判定本實施例的HEMT元件亦是電流崩塌受較佳抑制。
(實施例9)
除將緩衝層2與通道層3的成長條件設為不同於實施例8
的以下條件之外,其餘均依照與實施例8同樣的條件施行HEMT元件20之製作。即,本實施例亦是在緩衝層2形成時,將形成條件設定為第1條件與第2條件等二階段,並形成途中從第1條件切換為第2條件。又,緩衝層2的總厚度係設為350nm。
緩衝層(第1條件):形成溫度=1050℃;反應器內壓=5kPa;第IIIA族原料氣體=Al原料及Ga原料;第VA族/第IIIA族氣體比=2000;Al原料氣體/第IIIA族原料氣體比=0.01;成長速率=1nm/秒;成長時間=50秒。
緩衝層(第2條件):形成溫度=1050℃;反應器內壓=10kPa;第VA族/第IIIA族氣體比=500;成長速率=1nm/秒;成長時間=300秒。
GaN通道層:形成溫度=1050℃;反應器內壓=100kPa;第VA族/第IIIA族氣體比=2000;厚度=1700nm。
從針對所獲得HEMT元件,依照與實施例1同樣的條件,利用SIMS測定朝深度方向施行測定,而獲得距障壁層4之表面(上面)朝深度方向的Zn元素、C元素的濃度分佈,以及該深度方向上的Al元素之二次離子訊號分佈,得知以下事項。
(1)在GaN基板中高濃度(1×1019cm-3)摻雜Zn元素。
(2)C元素的濃度在緩衝層中,存在於從最大的6×1018cm-3起至1×1018cm-3以上範圍內,在通道層則大約在1×1016cm-3以下。又,C元素的濃度變化係在緩衝層與通道層的界面處呈現急遽狀態,相對的從緩衝層起至GaN基板的濃度變化則較為緩和。
(3)從緩衝層與GaN基板的界面起至基板側依高濃度存在的Zn元素,在緩衝層內急遽減少,在通道層內亦減少,在通道層中的障壁層與通道層之的界面(異質界面)附近,到達SIMS測定時的Zn檢測下限值之5×1014cm-3。即,Zn元素的擴散獲抑制。
(4)Zn濃度1×1017cm-3地方的Zn濃度每1μm之對數變化率(濃度常用對數值的變化率)係-58.3。
(5)Al元素係存在於較緩衝層全體目標厚度350nm更寬範圍,該範圍亦涵蓋GaN基板其中一部分。
(6)緩衝層中,在C元素濃度最大的區域中幾乎沒有檢測到Al元素,因而可謂緩衝層存在有:明顯摻雜C的GaN層、與些微摻雜C的AlGaN層。
針對該HEMT元件求取R值,結果係0.92。即,判定本實施例的HEMT元件亦是電流崩塌受較佳抑制。
1‧‧‧獨立式基板
2‧‧‧緩衝層
3‧‧‧通道層
4‧‧‧障壁層
5‧‧‧源極
6‧‧‧汲極
7‧‧‧閘極
10‧‧‧磊晶基板
20‧‧‧HEMT元件
Claims (19)
- 一種半導體元件用磊晶基板,包括:半絕緣性獨立式基板,其乃由經摻雜Zn的GaN所構成;緩衝層,其乃鄰接上述獨立式基板;通道層,其乃鄰接上述緩衝層;以及障壁層,其乃設置於上述緩衝層對向側,呈夾置上述通道層狀態;其中,上述緩衝層係抑制Zn從上述獨立式基板擴散於上述通道層的擴散阻障層。
- 如申請專利範圍第1項之半導體元件用磊晶基板,其中,上述緩衝層係厚度方向至少其中一部分範圍由依1×1018cm-3以上濃度摻雜C,而成的第IIIA族氮化物層。
- 如申請專利範圍第2項之半導體元件用磊晶基板,其中,上述第IIIA族氮化物層係GaN層。
- 如申請專利範圍第2項之半導體元件用磊晶基板,其中,上述第IIIA族氮化物層係由相異組成的2以上第IIIA族氮化物層積層而成,且上述2以上第IIIA族氮化物層中之至少一層係由經C依1×1018cm-3以上濃度摻雜而成的多層緩衝層、或者由含2或以上之第IIIA族元素的第IIIA族氮化物所構成,且第IIIA族元素的存在比率在厚度方向有變化的成分梯度緩衝層。
- 如申請專利範圍第2至4項中任一項之半導體元件用磊晶基板,其中,上述通道層的Zn濃度係1×1016cm-3以下。
- 如申請專利範圍第2至4項中任一項之半導體元件用磊晶 基板,其中,上述通道層係由GaN構成,上述障壁層係由AlGaN構成。
- 一種半導體元件,包括:半絕緣性獨立式基板,其乃由經摻雜Zn的GaN所構成;緩衝層,其乃鄰接上述獨立式基板;通道層,其乃鄰接上述緩衝層;障壁層,其乃設置於上述緩衝層對向側,呈夾置上述通道層狀態;以及閘極、源極及汲極,其乃設置於上述障壁層上;其中,上述緩衝層係抑制Zn從上述獨立式基板擴散於上述通道層的擴散阻障層。
- 如申請專利範圍第7項之半導體元件,其中,上述緩衝層係厚度方向至少其中一部分範圍由依1×1018cm-3以上濃度摻雜C,而成的第IIIA族氮化物層。
- 如申請專利範圍第8項之半導體元件,其中,上述第IIIA族氮化物層係GaN層。
- 如申請專利範圍第8項之半導體元件,其中,上述第IIIA族氮化物層係由相異組成的2以上第IIIA族氮化物層積層而成,且上述2以上第IIIA族氮化物層中之至少一層係由經C依1×1018cm-3以上濃度摻雜而成的多層緩衝層、或者由含2或以上之第IIIA族元素的第IIIA族氮化物所構成,且第IIIA族元素的存在比率在厚度方向有變化的成分梯度緩衝層。
- 如申請專利範圍第8至10項中任一項之半導體元件,其 中,上述通道層的Zn濃度係1×1016cm-3以下。
- 如申請專利範圍第8至10項中任一項之半導體元件,其中,上述通道層係由GaN構成,上述障壁層係由AlGaN構成。
- 一種半導體元件用磊晶基板之製造方法,係製造半導體元件用磊晶基板的方法,包括:a)準備步驟,其乃準備由經摻雜Zn的GaN所構成半絕緣性獨立式基板;b)緩衝層形成步驟,其乃鄰接上述獨立式基板形成緩衝層;c)通道層步驟,其乃鄰接上述緩衝層形成通道層;以及d)障壁層形成步驟,其乃在位於上述緩衝層對向側位置處,呈夾置上述通道層狀態形成障壁層;其中,緩衝層形成步驟中,所形成的上述緩衝層係抑制Zn從上述獨立式基板擴散於上述通道層的擴散阻障層。
- 如申請專利範圍第13項之半導體元件用磊晶基板之製造方法,其中,緩衝層形成步驟中,藉由上述緩衝層係厚度方向至少其中一部分範圍係經C依1×1018cm-3以上濃度摻雜的第IIIA族氮化物層形成,而抑制Zn從上述獨立式基板擴散於上述通道層。
- 如申請專利範圍第14項之半導體元件用磊晶基板之製造方法,其中,上述第IIIA族氮化物層係由GaN形成。
- 如申請專利範圍第14項之半導體元件用磊晶基板之製造方法,其中,上述第IIIA族氮化物層係由至少一層經C依1×1018cm-3以上濃度摻雜且相異組成的2以上第IIIA族氮 化物層積層而形成多層緩衝層、或者由含2或以上之第IIIA族元素的第IIIA族氮化物所構成,且形成第IIIA族元素的存在比率在厚度方向有變化的成分梯度緩衝層。
- 如申請專利範圍第14至16項中任一項之半導體元件用磊晶基板之製造方法,其中,上述緩衝層形成步驟中,依上述通道層的Zn濃度成為1×1016cm-3以下的方式,由上述第IIIA族氮化物層形成上述緩衝層。
- 如申請專利範圍第14至16項中任一項之半導體元件用磊晶基板之製造方法,其中,上述通道層係由GaN構成,上述障壁層係由AlGaN形成。
- 如申請專利範圍第13至16項中任一項之半導體元件用磊晶基板之製造方法,其中,上述獨立式基板係依通量法製作。
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