WO2017077989A1 - 半導体素子用エピタキシャル基板、半導体素子、および、半導体素子用エピタキシャル基板の製造方法 - Google Patents
半導体素子用エピタキシャル基板、半導体素子、および、半導体素子用エピタキシャル基板の製造方法 Download PDFInfo
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- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
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- 229910052784 alkaline earth metal Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
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Images
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/0242—Crystalline insulating materials
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/34—Nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02458—Nitrides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
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- H01L21/02625—Liquid deposition using melted materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
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- H01L21/02628—Liquid deposition using solutions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
Definitions
- the present invention relates to a semiconductor element, and more particularly to a semiconductor element configured using a self-standing substrate made of semi-insulating GaN.
- Nitride semiconductors have a wide band gap of direct transition type, a high dielectric breakdown electric field, and a high saturation electron velocity. Therefore, they are used as light-emitting devices such as LEDs and LDs, and as semiconductor materials for high-frequency / high-power electronic devices. It's being used.
- HEMT high electron mobility transistor
- Nitride electronic devices are generally manufactured using a commercially available heterogeneous material base substrate such as sapphire, SiC, or Si.
- a commercially available heterogeneous material base substrate such as sapphire, SiC, or Si.
- GaN films heteroepitaxially grown on these dissimilar material substrates many defects are generated due to differences in lattice constants and thermal expansion coefficients between GaN and dissimilar material substrates. There is.
- the mobility of the two-dimensional electron gas existing at the AlGaN / GaN laminated interface is improved, so that the HEMT element (semiconductor element) produced using the structure is improved. Improvement in characteristics can be expected.
- a commercially available GaN substrate manufactured by a hydride vapor phase epitaxy (HVPE method) generally exhibits an n-type conductivity due to oxygen impurities incorporated in the crystal. .
- the conductive GaN substrate becomes a leakage current path between the source and drain electrodes when the HEMT device is driven at a high voltage. Therefore, it is desirable to use a semi-insulating GaN substrate to produce a HEMT element.
- a semi-insulating GaN substrate In order to realize a semi-insulating GaN substrate, it is effective to dope a GaN crystal with an element that forms a deep acceptor level such as a transition metal element (for example, Fe) or a group 2 element (for example, Mg). It has been.
- a transition metal element for example, Fe
- a group 2 element for example, Mg
- an acceptor element such as Fe, Mg, Zn is GaN.
- Patent Document 3 discloses that acceptor elements such as Fe and Mg are likely to diffuse, which causes current collapse.
- the present invention has been made in view of the above problems, and an object thereof is to provide an epitaxial substrate for a semiconductor device in which the occurrence of current collapse is suppressed.
- an epitaxial substrate for a semiconductor device includes a semi-insulating free-standing substrate made of GaN doped with Zn, and a buffer layer adjacent to the free-standing substrate.
- the diffusion suppression layer suppresses the diffusion of Zn from the free-standing substrate into the channel layer.
- the dislocation density of the free-standing substrate is 5.0 ⁇ 10 7 cm ⁇ 2 or less, and the thickness of the buffer layer is 10 nm or more.
- the buffer layer had an Al concentration of 1 ⁇ 10 18 cm ⁇ 3 or more and 5 ⁇ 10 21 cm ⁇ 3 or less.
- the concentration of Zn in the channel layer is 1 ⁇ 10 16 cm ⁇ 3 or less.
- the buffer layer in the epitaxial substrate for a semiconductor element according to the second or third aspect, has an Al concentration of 5 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 21 cm ⁇ 3 or less. And so on.
- the buffer layer has a thickness of 20 nm to 200 nm.
- the channel layer is made of GaN and the barrier layer is made of AlGaN.
- a semiconductor device comprising a semi-insulating free-standing substrate made of Zn-doped GaN, a buffer layer adjacent to the free-standing substrate, and a channel adjacent to the buffer layer.
- a barrier layer provided on the opposite side of the buffer layer across the channel layer, and a gate electrode, a source electrode, and a drain electrode provided on the barrier layer,
- the buffer layer is made of Al-doped GaN, and is a diffusion suppression layer that suppresses the diffusion of Zn from the free-standing substrate to the channel layer.
- the dislocation density of the free-standing substrate is 5.0 ⁇ 10 7 cm ⁇ 2 or less
- the thickness of the buffer layer is 10 nm or more and 1000 nm or less
- the buffer layer has an Al concentration of 1 ⁇ 10 18 cm ⁇ 3 or more and 5 ⁇ 10 21 cm ⁇ 3 or less.
- the concentration of Zn in the channel layer is 1 ⁇ 10 16 cm ⁇ 3 or less.
- the Al concentration of the buffer layer is 5 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 21 cm ⁇ 3 or less. did.
- the buffer layer has a thickness of 20 nm to 200 nm.
- the channel layer is made of GaN and the barrier layer is made of AlGaN.
- a method of manufacturing an epitaxial substrate for a semiconductor device comprising: a) a preparatory step of preparing a semi-insulating free-standing substrate made of Zn-doped GaN; and b) A buffer layer forming step for forming a buffer layer adjacent to the buffer layer; c) a channel layer step for forming a channel layer adjacent to the buffer layer; and d) a position opposite to the buffer layer across the channel layer.
- the self-standing substrate having a dislocation density of 5.0 ⁇ 10 7 cm ⁇ 2 or less.
- the buffer layer has a thickness of 10 nm to 1000 nm and an Al concentration of 1 ⁇ 10 18 cm ⁇ 3 to 5 ⁇ 10 21 cm ⁇ 3 .
- the concentration of Zn in the channel layer is 1 ⁇ 10 16 cm ⁇ 3 or less.
- the buffer layer is formed.
- the buffer layer in the method for manufacturing an epitaxial substrate for a semiconductor element according to the fourteenth or fifteenth aspect, is 5 ⁇ 10 18 cm ⁇ 3 or more and 1 It was formed so as to have an Al concentration of ⁇ 10 21 cm ⁇ 3 or less.
- the buffer layer in the method for manufacturing an epitaxial substrate for a semiconductor element according to any one of the fourteenth to sixteenth aspects, in the buffer layer forming step, the buffer layer has a thickness of 20 nm or more and 200 nm or less. To form.
- the channel layer is formed of GaN and the barrier layer is formed of AlGaN. It was to so.
- the self-supporting substrate is manufactured by a flux method.
- a semiconductor element with reduced current collapse can be realized while using a semi-insulating GaN free-standing substrate.
- FIG. 2 is a diagram schematically showing a cross-sectional structure of a HEMT element 20.
- FIG. Sample No. FIG. 4 is a diagram showing a concentration profile of Zn element and Al element in an epitaxial substrate constituting the 1-4 HEMT device. Sample No. It is a figure which shows the concentration profile of Zn element in the epitaxial substrate which comprises the HEMT element of 1-1, and Al element.
- Group 13 refers to aluminum (Al), gallium (Ga), indium (In), etc.
- Group 14 refers to silicon (Si), germanium (Ge), tin (Sn), lead (Pb), etc.
- 15 refers to nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and the like.
- FIG. 1 schematically shows a cross-sectional structure of a HEMT device 20 as an embodiment of a semiconductor device according to the present invention, which includes an epitaxial substrate 10 as an embodiment of an epitaxial substrate for a semiconductor device according to the present invention.
- FIG. 1 schematically shows a cross-sectional structure of a HEMT device 20 as an embodiment of a semiconductor device according to the present invention, which includes an epitaxial substrate 10 as an embodiment of an epitaxial substrate for a semiconductor device according to the present invention.
- the epitaxial substrate 10 includes a free-standing substrate 1, a buffer layer 2, a channel layer 3, and a barrier layer 4.
- the HEMT device 20 is provided with a source electrode 5, a drain electrode 6, and a gate electrode 7 on the epitaxial substrate 10 (on the barrier layer 4).
- the ratio of the thickness of each layer in FIG. 1 does not reflect the actual one.
- the free-standing substrate 1 is a (0001) -oriented GaN substrate doped with Zn of 1 ⁇ 10 18 cm ⁇ 3 or more, has a specific resistance at room temperature of 1 ⁇ 10 2 ⁇ cm or more, and exhibits semi-insulating properties. From the viewpoint of suppressing the diffusion of Zn into the channel layer 3, the dislocation density of the freestanding substrate 1 is preferably 5 ⁇ 10 7 cm 2 or less.
- the size of the self-standing substrate 1 is not particularly limited, but considering the ease of handling (gripping, moving, etc.), it is preferable to have a thickness of about several hundred ⁇ m to several mm.
- Such a self-supporting substrate 1 can be manufactured by, for example, a flux method.
- the formation of the self-supporting substrate 1 by the flux method is generally performed by using a seed substrate in a melt containing metal Ga, metal Na, metal Zn, and C (carbon) in a growth vessel (alumina crucible) that is horizontally rotatable in a pressure vessel.
- the GaN single crystal formed on the seed substrate is separated from the seed substrate by maintaining a predetermined temperature and a predetermined pressure in the growth container while introducing nitrogen gas while the growth container is horizontally rotated. Obtained by.
- a so-called template substrate in which a GaN thin film is formed on a sapphire substrate by MOCVD can be suitably used.
- the buffer layer 2 is a layer formed on (adjacent to) one main surface of the free-standing substrate 1 and having a thickness of 10 nm to 1000 nm.
- the buffer layer 2 is formed at a temperature similar to the formation temperature of the channel layer 3 and the barrier layer 4 unlike the so-called low temperature buffer layer formed at a low temperature of less than 800 ° C. is there.
- buffer layer 2 suppresses diffusion of Zn doped into free-standing substrate 1 to channel layer 3 and further to barrier layer 4 thereabove when epitaxial substrate 10 is manufactured. It is provided as a diffusion suppression layer.
- a suitable example of the buffer layer 2 is a layer made of GaN doped with Al at a concentration of 1 ⁇ 10 18 cm ⁇ 3 or more and 5 ⁇ 10 21 cm ⁇ 3 or less.
- the diffusion of Zn from the free-standing substrate 1 to the channel layer 3 is preferably suppressed, and as a result, current collapse is preferably suppressed in the HEMT device 20 manufactured using the epitaxial substrate 10.
- the buffer layer 2 is provided with a thickness of 20 nm to 200 nm.
- the buffer layer 2 is formed of GaN doped with Al at a concentration of 5 ⁇ 10 18 cm ⁇ 3 to 1 ⁇ 10 21 cm ⁇ 3 . In these cases, current collapse in the HEMT device 20 fabricated using the epitaxial substrate 10 is further suppressed.
- the thickness of the buffer layer 2 is larger than 1000 nm and make the Al concentration of the buffer layer 2 larger than 5 ⁇ 10 21 cm ⁇ 3 , in these cases, the surface of the epitaxial substrate 10 Cracks may occur on the surface of the barrier layer 4.
- the thickness of the buffer layer 2 is made smaller than 10 nm or when the Al concentration of the buffer layer 2 is made smaller than 5 ⁇ 10 17 cm ⁇ 3 , the effect of suppressing the diffusion of Zn cannot be sufficiently obtained. Since current collapse is not sufficiently suppressed, it is not preferable.
- the channel layer 3 is a layer formed on (adjacent to) the buffer layer 2.
- the channel layer 3 is formed to a thickness of about 50 nm to 5000 nm.
- the barrier layer 4 is a layer provided on the side opposite to the buffer layer 2 with the channel layer 3 interposed therebetween.
- the barrier layer 4 is formed to a thickness of about 2 nm to 40 nm.
- the barrier layer 4 may be formed adjacent to the channel layer 3 as shown in FIG. 1, and in this case, the interface between the two layers is a heterojunction interface.
- a spacer layer (not shown) may be provided between the channel layer 3 and the barrier layer 4, and in this case, a region from the interface between the channel layer 3 and the spacer layer to the interface between the barrier layer 4 and the spacer layer is heterogeneous. It becomes a bonding interface region.
- the channel layer 3 is formed by GaN
- the barrier layer 4 is AlGaN (Al x Ga 1-x N, 0 ⁇ x ⁇ 1) to InAlN (In y Al 1-y N, 0 ⁇ y ⁇ A preferred example is that formed in 1).
- the combination of the channel layer 3 and the barrier layer 4 is not limited to this.
- the formation of the buffer layer 2, the channel layer 3, and the barrier layer 4 is realized by, for example, the MOCVD method.
- the MOCVD method for example, when the buffer layer 2 is formed of Al-doped GaN, the channel layer 3 is formed of GaN, and the barrier layer 4 is formed of AlGaN, the layer formation by the MOCVD method is about Ga and Al.
- a self-supporting MOCVD furnace constructed to be able to supply organometallic (MO) source gases (TMG, TMA), ammonia gas, hydrogen gas, and nitrogen gas into the reactor, and placed in the reactor This can be done by sequentially depositing on the free-standing substrate 1 GaN crystals or AlGaN crystals generated by a gas phase reaction between an organometallic source gas corresponding to each layer and ammonia gas while heating the substrate 1 to a predetermined temperature.
- MO organometallic
- the source electrode 5 and the drain electrode 6 are metal electrodes each having a thickness of about 10 to 100 nm.
- the source electrode 5 and the drain electrode 6 are preferably formed as multilayer electrodes made of, for example, Ti / Al / Ni / Au.
- the source electrode 5 and the drain electrode 6 are in ohmic contact with the barrier layer 4.
- the source electrode 5 and the drain electrode 6 are preferably formed by a vacuum deposition method and a photolithography process. In order to improve the ohmic contact between both electrodes, it is preferable to perform heat treatment for several tens of seconds in a nitrogen gas atmosphere at a predetermined temperature between 650 ° C. and 1000 ° C. after the electrodes are formed.
- the gate electrodes 7 are metal electrodes each having a thickness of about 10 to 100 nm.
- the gate electrode 7 is preferably configured as a multilayer electrode made of Ni / Au, for example.
- the gate electrode 7 has a Schottky contact with the barrier layer 4.
- the gate electrode 7 is preferably an example formed by a vacuum deposition method and a photolithography process.
- a c-plane sapphire substrate having a diameter similar to that of the free-standing substrate 1 to be manufactured is prepared, and a GaN low-temperature buffer layer is formed on the surface at a temperature of 450 ° C. to 750 ° C. to a thickness of about 10 nm to 50 nm.
- a GaN thin film having a thickness of about 1 ⁇ m to 10 ⁇ m is formed by MOCVD at a temperature of 1000 ° C. to 1200 ° C. to obtain a MOCVD-GaN template that can be used as a seed substrate.
- a Zn-doped GaN single crystal layer is formed using the Na flux method.
- an MOCVD-GaN template is placed in an alumina crucible, and subsequently, 10 g to 60 g of metal Ga, 15 g to 90 g of metal Na, and 0.1 g of metal Zn are placed in the alumina crucible. 5 g and 10 mg to 500 mg of C are charged respectively.
- the alumina crucible is placed in a heating furnace, the furnace temperature is set to 800 ° C. to 950 ° C., the furnace pressure is set to 3 MPa to 5 MPa, and heated for about 20 hours to 400 hours, and then cooled to room temperature. After cooling is complete, the alumina crucible is removed from the furnace.
- an MOCVD-GaN template having a brown GaN single crystal layer deposited on the surface with a thickness of 300 ⁇ m to 3000 ⁇ m is obtained.
- the GaN single crystal layer thus obtained is polished using diamond abrasive grains, and the surface thereof is flattened. Thereby, a flux-GaN template in which a GaN single crystal layer is formed on the MOCVD-GaN template is obtained.
- the polishing is performed in such a range that the total thickness of the nitride layer in the flux-GaN template is maintained at a value sufficiently larger than the target thickness of the free-standing substrate 1 to be finally obtained.
- the seed substrate is separated from the flux-GaN template by irradiating laser light from the seed substrate side while scanning at a scanning speed of 0.1 mm / second to 100 mm / second by a laser lift-off method.
- the laser light for example, it is preferable to use a third harmonic of Nd: YAG having a wavelength of 355 nm.
- the pulse width may be about 1 ns to 1000 ns and the pulse period may be about 1 kHz to 200 kHz.
- the laser light irradiation is preferably performed while heating the flux-GaN template at a temperature of about 30 ° C. to 600 ° C. from the side opposite to the seed substrate.
- a free-standing substrate (Zn-doped GaN single-crystal free-standing substrate) 1 made of GaN doped with Zn at a concentration of 1 ⁇ 10 18 cm ⁇ 3 or more is obtained.
- the dislocation density of the free-standing substrate 1 can be controlled by changing the thickness of the Zn-doped GaN single crystal layer formed in the Flux-GaN template. This utilizes the fact that as the Zn-doped GaN single crystal layer is formed thicker, a region having a lower dislocation density is formed thereon. Accordingly, by appropriately determining the formation thickness of the Zn-doped GaN single crystal layer and the polishing amount after laser lift-off, it is possible to obtain the self-supporting substrate 1 having a dislocation density of 5 ⁇ 10 7 cm 2 or less as described above. It has become.
- the epitaxial substrate 10 is formed by stacking the buffer layer 2, the channel layer 3, and the barrier layer 4 in this order under the following conditions with the free-standing substrate 1 placed on a susceptor provided in the reactor of the MOCVD furnace. It is obtained by doing.
- the formation temperature means a susceptor heating temperature.
- the group 15 / group 13 gas ratio is the total of TMG (trimethylgallium), TMA (trimethylaluminum), and TMI (trimethylindium), which are group 13 (Ga, Al, In) raw materials. It is the ratio (molar ratio) of the supply amount of ammonia which is a Group 15 (N) raw material to the supply amount.
- the Al source gas / Group 13 source gas ratio when the barrier layer 4 is formed of AlGaN is the ratio (molar ratio) of the total supply amount of the Group 13 (Ga, Al) source to the supply amount of the Al source.
- the Al source gas / Group 13 source gas ratio when the barrier layer 4 is formed of InAlN is the ratio (molar ratio) of the total supply amount of the Group 13 (In, Al) source to the supply amount of the In source material. is there. Both are determined according to the desired composition of the barrier layer 4 (Al molar ratio x or In composition ratio y).
- Fabrication of the HEMT element 20 using the epitaxial substrate 10 can be realized by applying a known technique.
- an element isolation process is performed to remove a portion that becomes a boundary between individual elements by etching to about 50 nm to 1000 nm using a photolithography process and an RIE (Reactive Ion Etching) method, and then the surface of the epitaxial substrate 10 (the barrier layer). 4 a SiO 2 film having a thickness of 50 nm ⁇ 500 nm is formed on the surface), followed by by a SiO 2 film to be formed location of the source electrode 5 and drain electrode 6 is removed by etching using photolithography, SiO 2 pattern Get a layer.
- RIE Reactive Ion Etching
- the source electrode 5 and the drain electrode 6 are formed by forming a metal pattern made of Ti / Al / Ni / Au at a place where the source electrode 5 and the drain electrode 6 are to be formed using a vacuum deposition method and a photolithography process.
- the thickness of each metal layer is preferably 5 nm to 50 nm, 40 nm to 400 nm, 4 nm to 40 nm, and 20 nm to 200 nm in order.
- heat treatment is performed for 10 seconds to 1000 seconds in a nitrogen gas atmosphere at 600 ° C. to 1000 ° C.
- the SiO 2 film at the location where the gate electrode 7 is to be formed is removed from the SiO 2 pattern layer using a photolithography process.
- the gate electrode 7 is formed by forming a Schottky metal pattern made of Ni / Au at a place where the gate electrode 7 is to be formed by using a vacuum deposition method and a photolithography process.
- the thickness of each metal layer is preferably 4 nm to 40 nm and 20 nm to 200 nm.
- the HEMT element 20 is obtained by the above process.
- the free-standing substrate 1 is made of GaN doped with Zn at a concentration of 1 ⁇ 10 18 cm ⁇ 3 or more
- the buffer layer 2 is an epitaxial substrate. 10 is provided so as to function as a diffusion suppressing layer that prevents Zn from diffusing from the free-standing substrate 1 to the channel layer 3 during the fabrication of the semiconductor layer 10.
- the buffer layer 2 is a GaN layer doped with Al at a concentration of 1 ⁇ 10 18 cm ⁇ 3 to 5 ⁇ 10 21 cm ⁇ 3 .
- Zn diffuses from the buffer layer 2 to the channel layer 3 and further to the barrier layer 4. In this case, a current collapse phenomenon occurs in the HEMT device 20 because Zn functioning as an acceptor element functions as an electron trap.
- the diffusion of Zn from the free-standing substrate 1 is achieved by forming the buffer layer 2 with a GaN layer doped with Al in view of the above-described concentration conditions.
- the generation of current collapse is preferably suppressed. More specifically, the concentration of Zn in the channel layer is not more than 1 ⁇ 10 16 cm -3, generation of current collapse in the HEMT device 20 is appropriately suppressed.
- Example 1 After preparing a Zn-doped GaN single crystal free-standing substrate, seven types of epitaxial substrates were manufactured under the same conditions except that the self-supporting substrate was used as a base substrate and the thickness of the buffer layer was changed. Further, HEMT elements were produced using the respective epitaxial substrates. Hereinafter, a common sample No. is used for seven types of epitaxial substrates and HEMT devices manufactured using the respective epitaxial substrates. 1-1-No. 1-7 is used.
- a GaN low temperature buffer layer of 30 nm is formed on the surface of a c-plane sapphire substrate having a diameter of 2 inches and a thickness of 0.43 mm at 550 ° C., and then a 3 ⁇ m thick GaN thin film is formed by MOCVD at 1050 ° C.
- MOCVD-GaN template that can be used as a seed substrate was obtained.
- a Zn-doped GaN single crystal layer was formed using the Na flux method.
- an MOCVD-GaN template is placed in an alumina crucible, and then 30 g of metal Ga, 45 g of metal Na, 1 g of metal zinc, and 100 mg of carbon are filled in the alumina crucible. did.
- the alumina crucible was placed in a heating furnace, the furnace temperature was 850 ° C., the furnace pressure was 4.5 MPa, and the mixture was heated for about 100 hours, and then cooled to room temperature. After the cooling was completed, the alumina crucible was taken out of the furnace, and a brown GaN single crystal layer was deposited to a thickness of about 1000 ⁇ m on the surface of the MOCVD-GaN template.
- the GaN single crystal layer thus obtained is polished using diamond abrasive grains, the surface thereof is flattened, and the total thickness of the nitride layer formed on the base substrate is 900 ⁇ m. did.
- a flux-GaN template in which a GaN single crystal layer was formed on the MOCVD-GaN template was obtained.
- the Flux-GaN template was observed with the naked eye, no cracks were confirmed.
- the seed substrate was separated from the flux-GaN template by irradiating laser light from the seed substrate side while scanning at a scanning speed of 30 mm / second by the laser lift-off method.
- As the laser light a third harmonic of Nd: YAG having a wavelength of 355 nm was used.
- the pulse width was about 30 ns and the pulse period was about 50 kHz.
- the laser light was condensed into a circular beam having a diameter of about 20 ⁇ m so that the light density was about 1.0 J / cm.
- the laser beam irradiation was performed while heating the flux-GaN template at a temperature of about 50 ° C. from the side opposite to the seed substrate.
- the surface of the obtained laminated structure peeled from the seed substrate was polished to obtain a Zn-doped GaN free-standing substrate having a total thickness of 430 ⁇ m.
- the crystallinity of the obtained Zn-doped GaN substrate was evaluated using an X-ray rocking curve.
- the half width of (0002) plane reflection was 120 seconds, and the half width of (10-12) plane reflection was 150 seconds.
- an epitaxial substrate was produced by MOCVD. Specifically, under the following conditions, an Al-doped GaN layer as a buffer layer, a GaN layer as a channel layer, and an AlGaN layer as a barrier layer were stacked on each Zn-doped GaN substrate in this order.
- the group 15 / group 13 gas ratio is the ratio (molar ratio) of the supply amount of the group 15 (N) raw material to the supply amount of the group 13 (Ga, Al) raw material.
- the epitaxial substrate of the Al-doped GaN buffer layer having a thickness of 0 nm is an epitaxial substrate in which a GaN channel layer is immediately formed on the Zn-doped GaN substrate without forming the Al-doped GaN buffer layer.
- the Al-doped GaN buffer layer is formed under the condition that the Al concentration in the buffer layer is 5 ⁇ 10 19 cm ⁇ 3 .
- the susceptor temperature was lowered to near room temperature, the inside of the reactor was returned to atmospheric pressure, and the fabricated epitaxial substrate was taken out.
- HEMT devices were produced using the respective epitaxial substrates.
- the HEMT device was designed to have a gate width of 100 ⁇ m, a source-gate interval of 1 ⁇ m, a gate-drain interval of 4 ⁇ m, and a gate length of 1 ⁇ m.
- the part which becomes the boundary of each element was removed by etching to a depth of about 100 nm using a photolithography process and the RIE method.
- a SiO 2 film having a thickness of 100nm was formed on the epitaxial substrate, followed by the source electrode by a photolithography, a SiO 2 film to be formed location of the drain electrode by etching away the SiO 2 pattern layer Obtained.
- a metal pattern made of Ti / Al / Ni / Au (each film thickness is 25/200/20/100 nm) is formed at the locations where the source electrode and drain electrode are to be formed by using a vacuum deposition method and a photolithography process. Thus, a source electrode and a drain electrode were formed.
- heat treatment was performed for 30 seconds in a nitrogen gas atmosphere at 825 ° C.
- the SiO 2 film at the location where the gate electrode is to be formed was removed from the SiO 2 pattern layer using a photolithography process.
- a Schottky metal pattern made of Ni / Au (each film thickness is 20/100 nm) is formed at a position where the gate electrode is to be formed, thereby forming the gate electrode. Formed.
- the threading dislocation density was calculated based on the number of dislocations confirmed in each field when the self-supporting substrate was observed in a plurality of fields.
- SIMS evaluation of HEMT element About each HEMT element, the elemental analysis of the depth direction in an epitaxial substrate was performed by SIMS (secondary ion mass spectrometry), and the concentration profile of Zn element and Al element was obtained.
- FIG. 4 is a diagram showing a concentration profile of Zn element and Al element in an epitaxial substrate constituting the 1-4 HEMT device.
- FIG. It is a figure which shows the concentration profile of Zn element in the epitaxial substrate which comprises the HEMT element of 1-1, and Al element.
- the GaN substrate is doped with Zn at a high concentration (1 ⁇ 10 19 cm ⁇ 3 ).
- the Al concentration of the Al-doped GaN buffer layer is 5 ⁇ 10 19 cm ⁇ 3 .
- the GaN substrate is doped with Zn at a high concentration (1 ⁇ 10 19 cm ⁇ 3 ).
- the Zn element gradually decreases in the channel layer, the degree thereof is the same as that of sample No. It is gentle as compared with the HEMT device of 1-4, and even in the vicinity of the barrier layer, the sample no. Zn element exists at a concentration of 8 ⁇ 10 16 cm ⁇ 3 or more, which is one order or more larger than the 1-4 HEMT device.
- pulse / Id DC , 0 ⁇ R ⁇ 1) was adopted, and this was obtained for each HEMT device. If the R value is 0.7 or more, it can be determined that the HEMT element has a small current collapse.
- Table 1 shows the Al concentration of the buffer layer and the Zn concentration of the channel layer, and the R value obtained from the concentration profile for each sample of Experimental Example 1, the thickness of the buffer layer, and cracks on the surface of the epitaxial substrate ( In Table 1, “film crack” is described, and the same applies to the following experimental examples).
- the Al concentration and the Zn concentration were values at the central portion in the thickness direction of the target layer (the same applies to the following experimental examples).
- Table 1 also shows whether each sample corresponds to an example of the present invention or a comparative example.
- sample No. having no buffer layer was used.
- the Zn concentration of the channel layer was higher than 8 ⁇ 10 16 cm ⁇ 3 and 1 ⁇ 10 16 cm ⁇ 3 , and the R value remained at 0.25.
- the Zn concentration in the channel layer was 1 ⁇ 10 16 cm ⁇ 3 or less, and the R value was 0.70 or more. That is, sample No. 1-2 ⁇ No. It can be said that the HEMT device of 1-6 has a small current collapse.
- the Zn concentration of the channel layer was reduced to about 5 ⁇ 10 15 cm ⁇ 3, which is the detection lower limit in SIMS, and the R value was 0.80 or more.
- B.I. G. L means that the Zn concentration is at the background level (the same applies to Tables 2 and 3). That is, sample No. 1-3 to No. It can be said that the current collapse of the 1-5 HEMT device is particularly small.
- Example 2 After producing a Zn-doped GaN single-crystal free-standing substrate under the same production conditions and procedure as in Experimental Example 1, seven types of epitaxial substrates were produced using the free-standing substrate as a base substrate.
- the production conditions at that time were the same except that the Al source gas / Group 13 source gas ratio was different when forming the Al-doped GaN buffer layer so that the Al concentrations were different. More specifically, the Al source gas / Group 13 source gas ratio in forming the buffer layer is 0.00001, 0.00002, 0.0001, 0.001, 0.02, 0.1, 0.00. It was different from 7 level of 2.
- the thickness of the buffer layer was 100 nm.
- the dislocation density is the same as that of Sample No. It is estimated to be about the same as 1-4.
- HEMT elements were produced using the respective epitaxial substrates.
- a common sample No. is used for seven types of epitaxial substrates and HEMT devices manufactured using the respective epitaxial substrates. 2-1. Use 2-7.
- sample no. The epitaxial substrate and the HEMT device of 2-4 are the sample Nos.
- the epitaxial substrate and the HEMT device of 1-4 are the same.
- Table 2 lists the Al concentration of the buffer layer, the Zn concentration of the channel layer, and the R value for each sample of Experimental Example 2, along with the thickness of the buffer layer and the presence or absence of cracks on the surface of the epitaxial substrate. Show. Table 2 also shows whether each sample corresponds to an example of the present invention or a comparative example.
- the sample No. 1 in which the Al concentration in the buffer layer was 5.0 ⁇ 10 17 cm ⁇ 3 was used.
- the Zn concentration in the channel layer was higher than 7 ⁇ 10 16 cm ⁇ 3 and 1 ⁇ 10 16 cm ⁇ 3 , and the R value remained at 0.40.
- the Zn concentration in the channel layer was 1 ⁇ 10 16 cm ⁇ 3 or less, and the R value was 0.70 or more. That is, sample No. 2-2 to No. It can be said that the current collapse is small in the 2-6 HEMT device.
- the Zn concentration in the channel layer was reduced to about 5 ⁇ 10 15 cm ⁇ 3, which is the detection lower limit in SIMS, and the R value was 0.85 or more. That is, sample No. 2-3 ⁇ No. It can be said that the current collapse of the 2-5 HEMT device is particularly small.
- Example 3 After producing a Zn-doped GaN single-crystal free-standing substrate in the same procedure as in Experimental Example 1, three types of epitaxial substrates were produced using the free-standing substrate as a base substrate, and HEMT devices were produced using the respective epitaxial substrates.
- the GaN single-crystal layer is formed by the flux method so that the thickness of the GaN single-crystal layer formed on the surface of the MOCVD-GaN template is different.
- the training time was changed. This is intended to obtain Zn-doped GaN single crystal free-standing substrates having different dislocation densities.
- the thickness of the GaN single crystal layer was changed to three levels of 1000 ⁇ m, 600 ⁇ m, and 200 ⁇ m by changing the heating and holding time at 850 ° C. to three levels of 100 hours, 70 hours, and 40 hours.
- the manufacturing conditions of the epitaxial substrate and the HEMT element are as follows. It was the same as the case of producing the epitaxial substrate according to 1-4.
- the Al source gas / Group 13 source gas ratio is 0.001 so that the Al concentration is 5.0 ⁇ 10 19 cm ⁇ 3, and the thickness of the buffer layer is 100 nm.
- a common sample No. is used for the three types of epitaxial substrates and the HEMT device fabricated using each of them. 3-1. 3-3 is used. However, sample no.
- the epitaxial substrate and the HEMT device of 3-1 are the same as the sample No. 1 in Experimental Example 1.
- the epitaxial substrate and the HEMT device of 1-4 are the same.
- Table 3 the dislocation density of the Zn-doped GaN single crystal free-standing substrate (described as “GaN substrate” in Table 3), the Zn concentration of the channel layer, and the R value for each sample of Experimental Example 3, A list is shown together with the presence or absence of cracks on the surface of the epitaxial substrate. Table 3 also shows whether each sample corresponds to an example of the present invention or a comparative example.
- the sample No. 1 in which the dislocation density in the Zn-doped GaN single-crystal free-standing substrate is 2.0 ⁇ 10 6 cm ⁇ 2 .
- the Zn concentration of the channel layer was reduced to about 5 ⁇ 10 15 cm ⁇ 3, which is the detection lower limit in SIMS, and the R value was 0.90. That is, sample No. It can be said that the current collapse is particularly small in the 3-1 HEMT device.
- a free-standing substrate is used.
- An Al-doped GaN buffer having a dislocation density of 5.0 ⁇ 10 7 cm ⁇ 2 or less and an Al concentration of 1 ⁇ 10 18 cm ⁇ 3 or more and 5 ⁇ 10 21 cm ⁇ 3 or less on the freestanding substrate
- the Zn concentration in the channel layer can be reduced to 1 ⁇ 10 16 cm ⁇ 3 or less.
- the occurrence of current collapse is preferably suppressed.
- the thickness of the buffer layer is 20 nm or more and 200 nm or less, or when the Al concentration of the buffer layer is 5 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 21 cm ⁇ 3 or less, generation of current collapse is further suppressed.
Abstract
Description
図1は、本発明に係る半導体素子用エピタキシャル基板の一実施形態としてのエピタキシャル基板10を含んで構成される、本発明に係る半導体素子の一実施形態としてのHEMT素子20の断面構造を、模式的に示す図である。
(自立基板の作製)
まず、フラックス法による自立基板1の作製手順について説明する。
続いて、MOCVD法によるエピタキシャル基板10の作製について説明する。エピタキシャル基板10は、自立基板1をMOCVD炉のリアクタ内に設けられたサセプタ上に載置した状態で、下記の条件にてバッファ層2、チャネル層3、および障壁層4をこの順にて積層形成することで得られる。なお、形成温度とはサセプタ加熱温度を意味する。
形成温度=900℃~1200℃;
リアクタ内圧力=5kPa~30kPa;
キャリアガス=水素;
15族/13族ガス比=5000~20000;
Al原料ガス/13族原料ガス比=0.00002~0.1。
形成温度=1000℃~1200℃;
リアクタ内圧力=15kPa~105kPa;
キャリアガス=水素;
15族/13族ガス比=1000~10000。
形成温度=1000℃~1200℃;
リアクタ内圧力=1kPa~30kPa;
15族/13族ガス比=5000~20000;
キャリアガス=水素;
Al原料ガス/13族原料ガス比=0.1~0.4。
形成温度=700℃~900℃;
リアクタ内圧力=1kPa~30kPa;
15族/13族ガス比=2000~20000;
キャリアガス=窒素;
In原料ガス/13族原料ガス比=0.1~0.9。
エピタキシャル基板10を用いたHEMT素子20の作製は、公知の技術を適用することで実現可能である。
上述のように、本実施の形態に係るHEMT素子20においては、自立基板1が、1×1018cm-3以上の濃度でZnがドープされたGaNからなるとともに、バッファ層2が、エピタキシャル基板10の作製時にZnが自立基板1からチャネル層3へと拡散することを防止する拡散抑制層として機能するべく設けられてなる。より具体的には、バッファ層2は、1×1018cm-3以上5×1021cm-3以下の濃度でAlがドープされたGaN層である。
ZnドープGaN単結晶自立基板を作製した後、係る自立基板を下地基板として、バッファ層の厚みを違えたほかは同一の条件にて7種類のエピタキシャル基板を作製した。さらに、それぞれのエピタキシャル基板を用いてHEMT素子を作製した。以降においては、7種類のエピタキシャル基板とそれぞれを用いて作製したHEMT素子とに対し、共通のサンプルNo.1-1~No.1-7を用いる。
直径2インチ、厚さ0.43mmのc面サファイア基板の表面に、550℃にてGaN低温バッファ層を30nm成膜し、その後、厚さ3μmのGaN薄膜を1050℃にてMOCVD法により成膜し、種基板として利用可能なMOCVD-GaNテンプレートを得た。
続いて、MOCVD法によって、エピタキシャル基板を作製した。具体的には、以下の条件に従って、バッファ層としてのAlドープGaN層、チャネル層としてのGaN層、障壁層としてのAlGaN層を、それぞれのZnドープGaN基板上にこの順に積層形成した。なお、以下において、15族/13族ガス比とは、13族(Ga、Al)原料の供給量に対する15族(N)原料の供給量の比(モル比)である。
形成温度=1050℃;
リアクタ内圧力=5kPa;
15族/13族ガス比=15000;
Al原料ガス/13族原料ガス比=0.001;
厚み=0、10、20、100、200、1000、または2000nm。
形成温度=1050℃;
リアクタ内圧力=100kPa;
15族/13族ガス比=2000;
厚み=1000nm。
形成温度=1050℃;
リアクタ内圧力=5kPa;
15族/13族ガス比=12000;
Al原料ガス/13族ガス比=0.25;
厚み=25nm。
次に、それぞれのエピタキシャル基板を用いてHEMT素子を作製した。なお、HEMT素子は、ゲート幅が100μm、ソース-ゲート間隔が1μm、ゲート-ドレイン間隔が4μm、ゲート長が1μmとなるように設計した。
サンプルNo.1-4のHEMT素子について、STEM(走査型透過電子顕微鏡)観察し、係る観察結果に基づいてZnドープGaN基板の貫通転位密度を求めたところ、2×106cm-2であった。同条件で作製した、他のサンプルのZnドープGaN基板の転位密度についても、サンプルNo.1-4と同程度と見積もられる。
それぞれのHEMT素子について、SIMS(二次イオン質量分析法)によりエピタキシャル基板における深さ方向の元素分析を行い、Zn元素とAl元素の濃度プロファイルを得た。
半導体パラメーターアナライザーを用いて、サンプルNo.1-1~No.1-6のHEMT素子のドレイン電流ドレイン電圧特性(Id-Vd特性)をDCモードおよびパルスモード(静止ドレインバイアスVdq=30V、静止ゲートバイアスVgq=-5V)にて評価した。ピンチオフ(pinch-off)の閾値電圧はVg=-3Vであった。
実験例1と同様の作製条件および手順でZnドープGaN単結晶自立基板を作製した後、係る自立基板を下地基板として、7種類のエピタキシャル基板を作製した。その際の作製条件は、Al濃度が相異なるように、AlドープGaNバッファ層を形成する際のAl原料ガス/13族原料ガス比を違えたほかは、同一とした。より詳細には、当該バッファ層を形成する際のAl原料ガス/13族原料ガス比は、0.00001、0.00002、0.0001、0.001、0.02、0.1、0.2の7水準に違えた。また、バッファ層の厚みは100nmとした。
実験例1と同様の手順でZnドープGaN単結晶自立基板を作製した後、係る自立基板を下地基板として、3種類のエピタキシャル基板を作製し、それぞれのエピタキシャル基板を用いてHEMT素子を作製した。
上述した実験例1~3の結果からは、以下のことが確認される。
Claims (19)
- ZnがドープされたGaNからなる半絶縁性の自立基板と、
前記自立基板に隣接してなるバッファ層と、
前記バッファ層に隣接してなるチャネル層と、
前記チャネル層を挟んで前記バッファ層とは反対側に設けられてなる障壁層と、
を備え、
前記バッファ層が、AlドープGaNからなり、前記自立基板から前記チャネル層へのZnの拡散を抑制する拡散抑制層である、
ことを特徴とする、半導体素子用エピタキシャル基板。 - 請求項1に記載の半導体素子用エピタキシャル基板であって、
前記自立基板の転位密度が5.0×107cm-2以下であり、
前記バッファ層の厚みが10nm以上1000nm以下であり、
前記バッファ層のAl濃度が1×1018cm-3以上5×1021cm-3以下である、
ことを特徴とする半導体素子用エピタキシャル基板。 - 請求項2に記載の半導体素子用エピタキシャル基板であって、
前記チャネル層におけるZnの濃度は1×1016cm-3以下である、
ことを特徴とする半導体素子用エピタキシャル基板。 - 請求項2または請求項3に記載の半導体素子用エピタキシャル基板であって、
前記バッファ層のAl濃度が5×1018cm-3以上1×1021cm-3以下である、
ことを特徴とする半導体素子用エピタキシャル基板。 - 請求項2ないし請求項4のいずれかに記載の半導体素子用エピタキシャル基板であって、
前記バッファ層の厚みが20nm以上200nm以下である、
ことを特徴とする半導体素子用エピタキシャル基板。 - 請求項1ないし請求項5のいずれかに記載の半導体素子用エピタキシャル基板であって、
前記チャネル層はGaNからなり、前記障壁層はAlGaNからなる、
ことを特徴とする半導体素子用エピタキシャル基板。 - ZnがドープされたGaNからなる半絶縁性の自立基板と、
前記自立基板に隣接してなるバッファ層と、
前記バッファ層に隣接してなるチャネル層と、
前記チャネル層を挟んで前記バッファ層とは反対側に設けられてなる障壁層と、
前記障壁層の上に設けられてなるゲート電極、ソース電極、およびドレイン電極と、
を備え、
前記バッファ層が、AlドープGaNからなり、前記自立基板から前記チャネル層へのZnの拡散を抑制する拡散抑制層である、
ことを特徴とする、半導体素子。 - 請求項7に記載の半導体素子であって、
前記自立基板の転位密度が5.0×107cm-2以下であり、
前記バッファ層の厚みが10nm以上1000nm以下であり、
前記バッファ層のAl濃度が1×1018cm-3以上5×1021cm-3以下である、
ことを特徴とする半導体素子。 - 請求項8に記載の半導体素子であって、
前記チャネル層におけるZnの濃度は1×1016cm-3以下である、
ことを特徴とする半導体素子。 - 請求項8または請求項9に記載の半導体素子であって、
前記バッファ層のAl濃度が5×1018cm-3以上1×1021cm-3以下である、
ことを特徴とする半導体素子。 - 請求項8ないし請求項10のいずれかに記載の半導体素子であって、
前記バッファ層の厚みが20nm以上200nm以下である、
ことを特徴とする半導体素子。 - 請求項7ないし請求項11のいずれかに記載の半導体素子であって、
前記チャネル層はGaNからなり、前記障壁層はAlGaNからなる、
ことを特徴とする半導体素子。 - 半導体素子用のエピタキシャル基板を製造する方法であって、
a)ZnがドープされたGaNからなる半絶縁性の自立基板を用意する準備工程と、
b)前記自立基板に隣接させてバッファ層を形成するバッファ層形成工程と、
c)前記バッファ層に隣接させてチャネル層を形成するチャネル層工程と、
d)前記チャネル層を挟んで前記バッファ層とは反対側の位置に障壁層を形成する障壁層形成工程と、
を備え、
バッファ層形成工程においては、前記バッファ層を、AlドープGaNからなり、前記自立基板から前記チャネル層へのZnの拡散を抑制する拡散抑制層として形成する、
ことを特徴とする半導体素子用エピタキシャル基板の製造方法。 - 請求項13に記載の半導体素子用エピタキシャル基板の製造方法であって、
前記準備工程においては、転位密度が5.0×107cm-2以下である前記自立基板を用意し、
前記バッファ層形成工程においては、前記バッファ層を、10nm以上1000nm以下の厚みに、かつ、1×1018cm-3以上5×1021cm-3以下のAl濃度を有するように、形成する、
ことを特徴とする半導体素子用エピタキシャル基板の製造方法。 - 請求項14に記載の半導体素子用エピタキシャル基板の製造方法であって、
前記バッファ層形成工程においては、前記チャネル層におけるZnの濃度が1×1016cm-3以下となるように、前記バッファ層を形成する、
ことを特徴とする半導体素子用エピタキシャル基板の製造方法。 - 請求項14または請求項15に記載の半導体素子用エピタキシャル基板の製造方法であって、
前記バッファ層形成工程においては、前記バッファ層を、5×1018cm-3以上1×1021cm-3以下のAl濃度を有するように形成する、
ことを特徴とする半導体素子用エピタキシャル基板の製造方法。 - 請求項14ないし請求項16のいずれかに記載の半導体素子用エピタキシャル基板の製造方法であって、
前記バッファ層形成工程においては、前記バッファ層を、20nm以上200nm以下の厚みに形成する、
ことを特徴とする半導体素子用エピタキシャル基板の製造方法。 - 請求項13ないし請求項17のいずれかに記載の半導体素子用エピタキシャル基板の製造方法であって、
前記チャネル層はGaNにて形成され、前記障壁層はAlGaNにて形成される、
ことを特徴とする半導体素子用エピタキシャル基板の製造方法。 - 請求項13ないし請求項18のいずれかに記載の半導体素子用エピタキシャル基板の製造方法であって、
前記自立基板はフラックス法で作製される、
ことを特徴とする半導体素子用エピタキシャル基板の製造方法。
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