CN108807291B - 外延用基板及其制造方法 - Google Patents
外延用基板及其制造方法 Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 143
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 238000000407 epitaxy Methods 0.000 title claims description 30
- 238000000034 method Methods 0.000 title claims description 17
- 230000008021 deposition Effects 0.000 claims abstract description 87
- 239000000463 material Substances 0.000 claims abstract description 18
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- 239000002019 doping agent Substances 0.000 claims description 40
- 238000009826 distribution Methods 0.000 claims description 2
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- 239000010703 silicon Substances 0.000 description 17
- 238000002474 experimental method Methods 0.000 description 10
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 229910002601 GaN Inorganic materials 0.000 description 4
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 4
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- 229910052796 boron Inorganic materials 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052787 antimony Inorganic materials 0.000 description 3
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 3
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- 150000002500 ions Chemical class 0.000 description 3
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- 239000010980 sapphire Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
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- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910001233 yttria-stabilized zirconia Inorganic materials 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
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- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910010092 LiAlO2 Inorganic materials 0.000 description 1
- 229910010936 LiGaO2 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910007948 ZrB2 Inorganic materials 0.000 description 1
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- 230000000903 blocking effect Effects 0.000 description 1
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- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
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- 229910001195 gallium oxide Inorganic materials 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
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- 238000001657 homoepitaxy Methods 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- YQNQTEBHHUSESQ-UHFFFAOYSA-N lithium aluminate Chemical compound [Li+].[O-][Al]=O YQNQTEBHHUSESQ-UHFFFAOYSA-N 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
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- 239000011029 spinel Substances 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
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Abstract
一种外延用基板及其制造方法,该外延用基板包括有一基板、一沉积层、一缓冲层以及一外延层。该沉积层直接设置于该基板上,该沉积层具有一渐变掺杂浓度,该沉积层具有一第一表面以及与其相对的第二表面,其中该第一表面具有该渐变掺杂浓度的最小值;一缓冲层,设置于该沉积层之上;一外延层,设置于该缓冲层之上,该外延层主要由III‑V族的氮化物所组成;其中,该基板与该沉积层为同质材料。藉此,通过该沉积层是直接设置于该基板上,且该沉积层与该基板属于同质的设计,本发明所提供的外延用基板具有散热表现佳、低漏电流等优点。
Description
技术领域
本发明与半导体基板有关;特别是指一种外延用基板及其制造方法。
背景技术
一般半导体工艺中,是于一碳化硅或蓝宝石基板的表面进行外延的步骤,以形成一外延层,再于该外延层上制作所需的结构、半导体组件或电路。
为满足高功率、高频率的半导体应用领域,半导体组件必须耐受较大的击穿电压并且尽可能的降低来自于基板的漏电流等缺陷问题;例如,绝缘层上硅晶圆(Silicon onInsulator Wafer,SOI Wafer)的使用,即是为了有效降低基板漏电的问题,但在现有SOI结构中,通常会在两层基板之间加入一层氧化物层(如SiO2),作为绝缘体以及帮助两层基板黏合之用,然而,由于氧化物层属于热的不良导体,因此,现有SOI工艺所制作出的基板普遍都有散热效果不佳的缺点。
其次,于不同应用上,基板所需的散热效果、热耐受性的要求可能不同,举例而言,于RF组件的应用上,其工作温度相当高,甚至高达400℃之多,因此,若基板的散热不佳,恐影响组件的工作表现。
因此,如何制作出具有强度较佳、低漏电流、耐高温以及散热效果佳的基板,是本领域工作人员亟欲发展的方向之一。
发明内容
有鉴于此,本发明的目的在于提供一种外延用基板,具有高温耐受性高以及低漏电流的优势。
为达成上述目的,本发明提供的一种外延用基板包括有一基板;一沉积层,直接设置于该基板上,该沉积层具有一渐变掺杂浓度,该沉积层具有一第一表面以及与其相对的第二表面,其中该第一表面具有该渐变掺杂浓度的最小值;一缓冲层,设置于该沉积层之上;一外延层,设置于该缓冲层之上,该外延层主要由III-V族的氮化物所组成;其中,该基板与该沉积层为同质材料。
为达成上述目的,本发明提供的一种外延用基板的制造方法包含有提供一基板;形成一沉积层于该基板上,其中该沉积层与该基板为同质材料,该沉积层具有一渐变掺杂浓度,该沉积层具有一第一表面以及与其相对的第二表面,其中该第一表面具有该渐变掺杂浓度的最小值;形成一缓冲层于该沉积层;以及形成一外延层于该缓冲层上,其中该外延层主要由III-V族的氮化物所组成。
本发明的效果在于,该沉积层是直接设置于该基板上,且该沉积层与该基板属于同质材料的设计,因此具有散热表现佳、低漏电流等优点。
附图说明
图1至图2为本发明一第一优选实施例的外延用基板的横截面示意图。
图3为本发明一第二优选实施例的外延用基板的横截面示意图。
【符号说明】
[本发明]
100 外延用基板
10 基板
20 沉积层
20a 第一表面 20b 第二表面
22 高阻抗层区间 22a 第三表面 22b 第四表面
30 缓冲层
40 外延层
D1 第一距离
D2 第二距离
200 外延用基板
210 基板
220 沉积层
220a 第一表面 220b 第二表面
222 第一叠层 224 第二叠层
230 缓冲层
240 外延层
具体实施方式
为能更清楚地说明本发明,现举一优选实施例并配合附图详细说明如下。请参照图1及图2所示,为本发明一第一优选实施例的外延用基板100,其包括有一基板10、一沉积层20、一缓冲层30以及一外延层40,于后一并说明一优选实施例的外延用基板100的制造方法。
首先,执行步骤A:提供一基板。其中,于本实施例当中,所提供的基板10为硅基板,优选的基板10是以重掺杂硅基板为例,其具有一基板掺杂浓度,其中,优选的,该基板掺杂浓度不小于1×1018atom/em3。所述基板10所使用的掺杂物可以为施体(Donor)掺杂物或为受体(Acceptor)掺杂物,例如可以是,硼(B)、铝(Al)、镓Ga、磷(P)、砷(As)、锑(Sb)等,但于其他实施上,并不以此为限。接着,执行步骤B:形成一与该基板互为同质材料的沉积层于该基板上。其中该沉积层具有一渐变掺杂浓度,该沉积层具有一第一表面以及与其相对的第二表面,其中该第一表面具有该渐变掺杂浓度的最小值。
例如,于本实施例中,通过MOCVD工艺直接在基板10上沉积一同为硅质的沉积层20。其中,该沉积层20的掺杂浓度小于该基板10的掺杂浓度,该沉积层20主要是由低掺杂或实质上不掺杂的纯净的单晶硅所构成,例如,该沉积层20为低掺杂,其所选用的掺杂物与该基板10所使用的掺杂物相同或选用不相同的掺杂物。该沉积层20具有一第一表面20a以及一第二表面20b,该沉积层20以其第二表面20b直接结合在该基板10上,而与该基板10直接连接。在高温外延工艺的同时,沉积层的低掺杂物随着热扩散而形成一渐变掺杂浓度分布;在另一实施例中,重掺的基板10的掺杂物可能会随着高热处理部份扩散至实质上不掺杂的沉积层内,因而形成一渐变掺杂浓度分布。此外,沉积层20的渐变掺杂浓度自远离该基板10起的方向降低,其中第一表面20a具有该渐变掺杂浓度的最小值,第二表面20b具有该渐变掺杂浓度的最大值。值得一提的是,前述关于掺杂物选用的异同,包括有但不限于对于掺杂物种类的选择的异同、电导率型态(Conductivity Type)的选择的异同、掺杂物浓度的选择的异同等。
另外,该沉积层20具有一渐变电阻率分布,其中该沉积层20的该第一表面20a具有该渐变电阻率的最大值,例如该沉积层20的电阻率由第二表面20b往第一表面20a的方向递增。特别的是,在该沉积层20的渐变电阻率中,具有一段至少大于1500ohm-cm的高阻抗层区间22,优选的,该高阻抗层区间22的电阻值大于7000ohm-cm,而该高阻抗层区间22的厚度不大于6μm,优选的,该高阻抗层区间22的厚度小于2μm。
另外,上述形成该沉积层20的方式除可以是通过外延(如通过CVD、MOCVD等工艺)等晶体成长的方式外,亦可以通过如溅镀(Sputtering Deposition)、或是直接接合(Directly Bonding)等方式形成,而不以MOCVD工艺为限。
接着,执行步骤C:形成一缓冲层于该沉积层之上。例如,在本实施例中,于该沉积层20的第一表面20a上成长一缓冲层30,而于本实施例中,所述的缓冲层30主要由氮化铝镓(AlxGa1-xN,其中,0≤x<1)所构成,但于其他实施例中,所述的缓冲层30并不以氮化铝镓为限,亦可由其他材质所构成。
接着,执行步骤D:形成一外延层于该缓冲层之上,其中该外延层主要由III-V族的氮化物所组成。举例而言,于本实施例中,在缓冲层30上外延成长一外延层40,所述的外延层40主要由氮化镓(GaN)所组成,前述的缓冲层30是作为外延层40与沉积层20之间的缓冲之用,以达到降低晶格缺陷密度以及提升晶格匹配的应变补偿的效果。
藉此,通过该沉积层20当中的高阻抗层区间22的高阻抗率(高电阻率)的特性,可有效避免所述的基板在后续如CVD、MOCVD工艺等外延或其他工艺中,于形成半导体组件或电路时所产生的电流通过沉积层20而形成漏电流,亦即,可有效地改善半导体组件或电路产生漏电流的问题。
另外,由于本发明的基板10与沉积层20之间是采用直接连接且采取同质材料的设计,其间并未有其他异质结构,因此,就整体来看,相较于现有于基板之间或基板与外延结构之间还增设有二氧化硅(SiO2)层的设计而言,具有散热效果更佳,更适合应用于高温工作环境中的优点。
请配合下表所示,为应用上述实施例的制造方法所制成的外延用基板的实验参数与数据数据。其中,所述高阻抗层区间的厚度定义为第一距离D1,所述第一距离D1实质上为第三表面22a至第四表面22b之间的垂直距离,所述高阻抗层区间的扩散深度定义为第二距离D2,所述第二距离D2实质上为第四表面22b至第二表面20b之间的垂直距离。
其中,实验1与实验2的基板皆选用硅基板,且其硅基板的掺杂物选用P+,如硼,其硅基板的掺杂浓度均大于1×1019atom/cm3,其电阻值约为0.0035ohm-cm,其硅基板的厚度约为1000μm。
实验1与实验2的沉积层选用与硅基板互为同质材料的硅质沉积层,其沉积层的掺杂物皆选用N-,如磷,其沉积层厚度约为25μm,且均经由温度约为1150℃、时间约为310秒的外延工艺形成于硅基板上。其中,实验1与实验2的沉积层的不同之处在于,实验1的沉积层的掺杂浓度约为5000ohm-cm,而实验2的沉积层的掺杂浓度约为10000ohm-cm。
实验1与实验2的外延层的主要成分为GaN,且经由温度约为1000℃、时间约为6小时的外延工艺形成于沉积层上。而通过上述沉积层电阻值选用的差异,实验1获得扩散深度约为1.82μm、厚度小于2μm、电阻值大于7000ohm-cm的高阻抗层区间;而实验2获得扩散深度约为1.86μm、厚度小于2μm、电阻值大于15000ohm-cm的高阻抗层区间。
通过上述实验结果可知,通过本发明所提供的制造方法,可制造出具有高电阻率的高阻抗层区间的外延用基板,例如在上述实验1、2中所获得厚度小于2μm,电阻值大于7000ohm-cm或15000ohm-cm的高阻抗层区间,而通过高阻抗层区间的高电阻率的特性,可有效地避免基板在后续工艺中,于形成半导体组件或电路时所产生的电流通过沉积层,进而可成功改善漏电流的问题;除此之外,由于基板与沉积层是由同质外延的方式制成,因此,还可进一步提升基板的散热效果,以使得基板的应用范围更为广泛。
请参照图3所示,为本发明一第二实施例的外延用基板200,该外延用基板200的制造方法与结构与前述实施例的外延用基板100大致相同,其同样包含有一基板210、一沉积层220、一缓冲层230以及一外延层240。
其中,该基板210是以重掺杂的P型硅基板为例,具有一基板掺杂浓度,其中,优选的,该基板掺杂浓度不小于1×1018atom/cm3。其中,于本实施例当中,所述基板210可以为施体(Donor)掺杂物或为受体(Acceptor)掺杂物,例如可以是,硼(B)、铝(Al)、镓(Ga)、磷(P)、砷(As)、锑(Sb)等,但于其他实施上,并不以此为限。
该沉积层220是直接设置于该基板210上,举例而言,该沉积层220可以是通过外延(如通过CVD、MOCVD等工艺)等晶体成长的方式、或是溅镀(Sputtering Deposition)、或是直接接合(Directly Bonding)等方式形成于该基板210上,但于其他实施例中,并不以此为限。
特别的是,该沉积层220为一叠层结构,其至少包含有一第一叠层222以及一第二叠层224,其中,于一实施例中,其叠层的工艺在于:先于该基板210的表面形成该第一叠层222后,再于该第一叠层222上形成该第二叠层224,而使得该第一叠层222位于该基板210上且位于该基板210与该第二叠层224之间。其中,所述的第一叠层222与基板210之间的掺杂物可采取相同或不同的设计,例如于本实施例中,该第一叠层222的掺杂物与该基板210的掺杂物不相同;而该第二叠层224的掺杂物可采取与第一叠层222的掺杂物相同或不同的设计,例如在本实施例中,所述第二叠层224与该第一叠层222的掺杂物互不相同,而上述关于第一叠层222与第二叠层224的掺杂物选择以及掺杂浓度的设计,供作为一扩散势垒层来使用,亦即,其可用以控制掺杂物离子的扩散速率,并达成避免重掺的基板210的掺杂物扩散至高阻抗层区间的效果。
该沉积层220具有相对的第一表面220a与第二表面220b,其沉积层220的渐变掺杂浓度在该第一表面220a具有最小值;另一方面来说,该沉积层220具有一渐变电阻率分布,该沉积层220的该第一表面220a具有该渐变电阻率的最大值,且该渐变电阻率朝向第二表面220b的方向减少。值得一提的是,于该沉积层220的渐变电阻率中,具有一段至少大于1500ohm-cm的高阻抗层区间,其中所述的高阻抗层区间可成形于该沉积层220的任意位置。值得一提的是,基于该沉积层220为多层的叠层结构,而根据组件需求的不同,所述的第一叠层222以及第二叠层224亦可为交替叠层的多层配置,利用叠层结构控制离子扩散速率,因此,于实务上,针对个别组件的需求,可通过叠层的叠层结构的层数、厚度、掺杂物等参数的调控来控制离子扩散速率,进而可调整高阻抗层区间的成形位置。
接着,于该沉积层220上外延成长一缓冲层230,而于本实施例中,所述的缓冲层230主要由氮化铝镓(AlxGa1-xN,其中,0≤x<1)所构成,但于其他实施例中,所述的缓冲层230并不以氮化铝镓为限,亦可由其他材质所构成。
接着,于该缓冲层230之上,可再外延成长一外延层240,该外延层240主要由III-V族氮化物所构成,例如,于本实施例中,所述的外延层240可由氮化镓(GaN)所构成,前述的缓冲层230作为外延层240与高阻抗层224之间的缓冲之用,以达到降低晶格缺陷密度以及提升晶格匹配的应变补偿的效果。
通过该沉积层220的高电阻率的设计,特别是其中所形成的高阻抗层区间的高电阻率的特性,可有效避免所述的外延用基板200在后续如CVD、MOCVD工艺等外延或其他工艺中,于形成半导体组件或电路时所产生的电流通过高阻抗层区间而形成漏电流,亦即,可有效地改善半导体组件或电路产生漏电流的问题。除此之外,本实施例的外延用基板200同样具有耐高温、不易变形以及散热效果佳,特别适合应用在如RF应用等高温工作环境中的优点。
于前述实施例当中,所述的基板是以电导率型为P型掺杂的硅基板为例,另外,于其他实施例当中,所述的基板亦可使用电导率型为N型掺杂的基板,所使用的掺杂物可以选用为施体(Donor)掺杂物或为受体(Acceptor)掺杂物,例如可以是,硼(B)、铝(Al)、镓Ga、磷(P)、砷(As)、锑(Sb)等或其组合,而且于应用上并不仅限于硅材质的基板;另外,配合前述改用N型掺杂的基板,所述的阻挡层亦可改采N型掺杂,而不以P型掺杂为限。
以上所述仅为本发明优选可行实施例而已,值得一提的是,前述基板与沉积层的材质选用,基本上可根据基板与沉积层之间晶格是否匹配来选择,而不以上述基板为硅基板或沉积层为硅质沉积层为限,于一些实施例当中,基板以及沉积层的材料选用包括有单晶、多晶及/或非晶等;于一些实施例当中,基板以及沉积层的材质材料包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟,及/或锑化铟等;于一些实施例中,基板以及沉积层的材料选用包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP等;或者可选用其他适合的材料。
另外,于一些实施例中,所述的基板与沉积层可选自蓝宝石(sapphire)、氧化镓、氧化锂镓、氧化锂铝、尖晶石、锗、玻璃、二硼化锆、ScALMgO4、SrCu2O2、LiGaO2、LiAlO2、YSZ(Yttria-Stabilized Zirconia),或其他可供外延的材料。
凡应用本发明说明书及权利要求所为的等效变化,理应包含在本发明的权利要求保护范围内。另外需补充说明的是,前述术语「不大于」包含有小于等于的含意,前述术语「不小于」包含有大于等于的含意。
Claims (21)
1.一种外延用基板,其包括有:
一基板;
一沉积层,直接设置于该基板上,该沉积层具有一渐变掺杂浓度,该沉积层具有一第一表面以及与其相对的第二表面,其中该第一表面具有该渐变掺杂浓度的最小值;
一缓冲层,设置于该沉积层之上;
一外延层,设置于该缓冲层之上,该外延层主要由III-V族的氮化物所组成;
其中,该基板与该沉积层为相同材料;
其中,该沉积层具有一渐变电阻率分布,该渐变电阻率具有一段至少大于1500ohm-cm的高阻抗层区间。
2.如权利要求1所述的外延用基板,其中该沉积层的该第一表面具有该渐变电阻率的最大值。
3.如权利要求1所述的外延用基板,其中该高阻抗层区间的厚度不大于6μm。
4.如权利要求1所述的外延用基板,其中该高阻抗层区间的厚度小于2μm。
5.如权利要求1所述的外延用基板,其中该高阻抗层区间的电阻值大于7000ohm-cm。
6.如权利要求1所述的外延用基板,其中该沉积层的渐变掺杂浓度由该第二表面往该第一表面方向渐低。
7.如权利要求1所述的外延用基板,其中该沉积层的掺杂物与该基板的掺杂物相同。
8.如权利要求1所述的外延用基板,其中该沉积层至少包含有一第一叠层以及一第二叠层,该第一叠层位于该基板上且位于该基板与该第二叠层之间,该第二叠层位于该第一叠层之上。
9.如权利要求8所述的外延用基板,其中该第一叠层的掺杂浓度不大于该基板的掺杂浓度。
10.如权利要求8所述的外延用基板,其中该第一叠层的掺杂物与该基板的掺杂物不同。
11.如权利要求8所述的外延用基板,其中该第一叠层的掺杂物与该第二叠层的掺杂物不同。
12.如权利要求8所述的外延用基板,其中该沉积层的该第一表面具有该渐变电阻率的最大值。
13.如权利要求1或8所述的外延用基板,其中该基板为重掺杂基板,其掺杂浓度不小于1×1018atom/cm3。
14.一种外延用基板的制造方法,其包括有:
A、提供一基板;
B、形成一沉积层于该基板上,其中该沉积层与该基板为相同材料,该沉积层具有一渐变掺杂浓度,该沉积层具有一第一表面以及与其相对的第二表面,其中该第一表面具有该渐变掺杂浓度的最小值;其中,该沉积层具有一渐变电阻率分布,该渐变电阻率具有一段至少大于1500ohm-cm的高阻抗层区间;
C、形成一缓冲层于该沉积层上;以及
D、形成一外延层于该缓冲层上,其中该外延层主要由III-V族的氮化物所组成。
15.如权利要求14所述的外延用基板的制造方法,其中该沉积层的渐变掺杂浓度由该第二表面往该第一表面方向渐低。
16.如权利要求14所述的外延用基板的制造方法,其中该沉积层的掺杂物与该基板的掺杂物相同。
17.如权利要求14所述的外延用基板的制造方法,其中该沉积层至少包含有一第一叠层以及一第二叠层,于步骤B中,先于该基板上形成该第一叠层,再于该第一叠层上形成该第二叠层。
18.如权利要求17所述的外延用基板的制造方法,其中该第一叠层的掺杂浓度不大于该基板的掺杂浓度。
19.如权利要求17所述的外延用基板的制造方法,其中该第一叠层的掺杂物与该基板的掺杂物不同。
20.如权利要求17所述的外延用基板的制造方法,其中该第一叠层的掺杂物与该第二叠层的掺杂物不同。
21.如权利要求14或17所述的外延用基板的制造方法,其中该基板为重掺杂基板,其掺杂浓度不小于1×1018atom/cm3。
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