TW200529407A - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- TW200529407A TW200529407A TW094102226A TW94102226A TW200529407A TW 200529407 A TW200529407 A TW 200529407A TW 094102226 A TW094102226 A TW 094102226A TW 94102226 A TW94102226 A TW 94102226A TW 200529407 A TW200529407 A TW 200529407A
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- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F25—REFRIGERATION OR COOLING; COMBINED HEATING AND REFRIGERATION SYSTEMS; HEAT PUMP SYSTEMS; MANUFACTURE OR STORAGE OF ICE; LIQUEFACTION SOLIDIFICATION OF GASES
- F25D—REFRIGERATORS; COLD ROOMS; ICE-BOXES; COOLING OR FREEZING APPARATUS NOT OTHERWISE PROVIDED FOR
- F25D31/00—Other cooling or freezing apparatus
- F25D31/002—Liquid coolers, e.g. beverage cooler
- F25D31/003—Liquid coolers, e.g. beverage cooler with immersed cooling element
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- F25D—REFRIGERATORS; COLD ROOMS; ICE-BOXES; COOLING OR FREEZING APPARATUS NOT OTHERWISE PROVIDED FOR
- F25D3/00—Devices using other cold materials; Devices using cold-storage bodies
- F25D3/005—Devices using other cold materials; Devices using cold-storage bodies combined with heat exchangers
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- F28—HEAT EXCHANGE IN GENERAL
- F28F—DETAILS OF HEAT-EXCHANGE AND HEAT-TRANSFER APPARATUS, OF GENERAL APPLICATION
- F28F3/00—Plate-like or laminated elements; Assemblies of plate-like or laminated elements
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- F25D—REFRIGERATORS; COLD ROOMS; ICE-BOXES; COOLING OR FREEZING APPARATUS NOT OTHERWISE PROVIDED FOR
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Description
200529407 九、發明說明: 【發明所屬之技術領域】 本發明係關於內建半導體構成體的半導體裝置。 【先前技術】 在曰本特開2003-298005號公報所揭示習知半導體裝 置,爲在矽基板的尺寸外具備作爲外部連接用連接端子的錫 球,具有將上面具有多個連接墊的矽基板設於基底板的上 面,在矽基板周圍的基底板的上面設置絕緣層,在矽基板及 • 絕緣層的上面設置上層絕緣膜,在上層絕緣膜的上面設置上 層配線以連接於矽基板的連接墊,由最上層絕緣膜包覆除上 層配線的連接墊部外的部分,而在上層配線的連接墊部上設 置錫球的構成。 【發明內容】 (發明所欲解決之問題) 但是,在上述習知半導體裝置中,設於矽基板周圍之基 底板的上面的絕緣層係文字類的絕緣層,因此在增大絕緣層 ® 的平面尺寸而增大全體的平面尺寸的情況,具有絕緣層形成 大的死區的問題。 本發明之目的在於,提供一種可減少矽基板等的半導體 基板的周圍產生的死區的半導體裝置。 (解決問題之手段) 根據本發明,提供一種半導體裝置,其具備,基底構件 (22);設於上述基底構件(22)上,且具有半導體基板(5)及設 於該半導體基板(5)上的多個外部連接用電極(13)的半導體 200529407 9 構成體(3);設於上述半導體構成體(3)周圍,至少於一面具 有第1配線(3 3、34)的配線板(26);及設在上述半導體構成 體(3)及上述配線板(26)上,連接於上述半導體構成體(3)的 外部連接用電極(13)的第2配線(19)。 (發明效果) 根據本發明,在具有半導體基板及外部連接用電極的半 導體構成體的周圍設有配線板,因此可減少半導體基板的周 圍產生的死區。 # 【實施方式】 (第1實施形態) 第1圖顯示本發明之第1實施形態的半導體裝置的剖面 圖。該半導體裝置具備半導體組塊1。簡言之,半導體組塊 1具有支撐板2、半導體構成體3、絕緣層15、上層絕緣膜 1 6及上層配線19 (第2配線)。亦即,半導體組塊1具備平 面方形的支撐板2。支撐板2可爲樹脂、矽、陶瓷等的絕緣 板,另外,也可爲銅箔等的金屬板,還可爲後述之半固化片 •材或疊層材。 在支撐板2的上面介由晶片接合材構成的黏接層4黏接 較支撐板2的尺寸還要小某一程度的尺寸的平面方形的半導 體構成體3的下面。該情況,半導體構成體3具有後述之配 線12、柱狀電極13及封裝膜14,一般是稱爲CSP(chip size package),如後述,採用在矽晶圓上形成配線12、柱狀電極 1 3及封裝膜1 4後,藉由切割以獲得各個半導體構成體3的 方法,因此也特別稱之爲晶圓位準之CSP(W-CSP)。以下, 200529407 針對半導體構成體3的構成進行說明。 半導體構成體3具備平面方形矽基板(半導體基板)5° 矽基板5的下面係介由黏接層4黏接於支撐板2。在矽基板 5的上面設置指定功能的積體電路(未圖示),在上面週邊部 設置由鋁系金屬等組成的多個連接墊6 ’用以連接於積體電 路。在除連接墊6的中央部外的矽基板5的上面設置由氧化 矽等構成的絕緣膜7,連接墊6的中央部介由設於絕緣膜7 的開口部8而曝露。 Φ 在絕緣膜7的上面設置由環氧系樹脂及聚醯亞胺系樹脂 等所構成的保護膜9。該情況,在對應於絕緣膜7的開口部 8的部分的保護膜9上設置開口部1 0。在保護膜9的上面設 置銅等構成的襯底金屬層11。在襯底金屬層11上面全體設 置銅構成的配線1 2。含有襯底金屬層1 1的配線1 2的一端部 介由兩開口部8、1 0連接於連接墊6。 在配線1 2的連接墊部上面設置銅構成的柱狀電極(外部 連接用電極)1 3。在含有配線1 2的保護膜9的上面設置由環 ^ 氧系樹脂及聚醯亞胺系樹脂等所構成的封裝膜1 4,且使該封 裝膜上面與柱狀電極1 3上面形成於相同面。如此般,被稱 爲W-CSP的半導體構成體3包含砂基板5、連接墊6及絕緣 膜7,又,包含保護膜9、配線12、柱狀電極13及封裝膜 14 〇 在半導體構成體3周圍的支撐板2的上面設置方形框狀 的絕緣層1 5,且使該絕緣層上面與半導體構成體3的上面形 成爲大致相同面。絕緣層1 5如係由環氧系樹脂及聚醯亞胺 200529407 9 系樹脂等的熱硬化性樹脂、或在此種熱硬化性樹脂中混入玻 璃纖維或二氧化矽塡料等的補強材料者所構成。 在半導體構成體3及絕緣層15的上面設置其上面被平 坦化的上層絕緣膜1 6。上層絕緣膜1 6係用於多層電路基板 的通常稱爲疊層材者,例如,由在環氧系樹脂或BT樹脂等 的熱硬化性樹脂中混入玻璃纖維或二氧化矽塡料等的補強 材所構成。在對應於柱狀電極1 3上面中央部的部分的上層 絕緣膜1 6上設置開口部1 7。 φ 在上層絕緣膜1 6上面設置銅等組成的上層襯底金屬層 18。在上層襯底金屬層18的上面全體設置銅等組成的上層 配線1 9。含有上層襯底金屬層1 8的上層配線1 9的一端部, 係介由上層絕緣膜1 6的開口部1 7連接於柱狀電極1 3上面。 如此般構成後,半導體組塊1包含支撐板2、半導體構成體 3、絕緣層1 5、上層絕緣膜1 6及上層配線1 9。 半導體組塊1之支撐板2,係固接於平面方形的下側配 線板(基底構件)2 1上面的指定部位。下側配線板2 1係形成 • 爲介由設於絕緣基板22內的連通部25,連接設於絕緣基板 (基底構件)22上面的上面配線(第3配線)23及設於絕緣基板 22下面的下面配線(第3配線)24。該情況,絕緣基板22通 常爲稱爲半固化片者,例如,其由將環氧系樹脂等的熱硬化 性樹脂含浸於玻璃布或芳族聚醯胺纖維等構成的基材內所 構成,但也可使用疊層材。上面配線23及下面配線24係由 銅箔構成。連通部25係由金屬膏劑或導電性樹脂膏劑等所 構成。 200529407 t 在半導體組塊1周圍之下側配線板21的上面設置方形 框狀的中間配線板26,且使該中間配線板上面與半導體構成 體3的上面形成爲大致相同面。中間配線板26係由多層配 線板所構成,例如,其可爲在第1絕緣基板27的上下面疊 層第2、第3絕緣基板28、29,並介由設於第1絕緣基板27 內的連通部32及設於第1絕緣基板27的上下面的上面配線 (第1配線)33、下面配線(第1配線)34,連接設於第2絕緣 基板28內的連通部30及設於第3絕緣基板29內的連通部 # 3 1的構成。 該情況,第1〜第3絕緣基板27〜29係由下側配線板 2 1的絕緣基板22之相同材料的半固化片材或疊層材構成。 上面配線33及下面配線34係由銅箔所構成。連通部25係 由金屬膏劑或導電性樹脂膏劑等所構成。而第3絕緣基板29 的連通部3 1係連接於下側配線板2 1的上面配線23。 在半導體組塊1及中間配線板26的上面設置上側配線 板35。上側配線板35係形成爲介由設於絕緣基板36內的連 ® 通部39,連接設於絕緣基板36上面的上面配線37(第4配 線)及設於絕緣基板36下面的下面配線(第4配線)38的構 成。該情況,絕緣基板3 6係下側配線21的絕緣基板22之 相同材料的半固化片材或疊層材構成。上面配線37及下面 配線38係由銅箔所構成。連通部39係由金屬膏劑或導電性 樹脂膏劑等所構成。 上側配線板35的下面配線38係連接於中間配線板26 的第2絕緣基板28的連通部30。另外,設於上側配線板35 -10- 200529407 9 的上面配線3 7下的連通部3 9的一部分’未連接於下面配線 3 8,而是連接於半導體組塊1的上層配線1 9的連接墊部。 在上側配線板3 5的上面設置由焊料阻劑等構成的上層 過塗敷膜40。在對應於上側配線板35的上面配線37的連接 墊的部分的上層過塗敷膜40設置開口部4 1。在開口部4 1 內及其上方設置錫球42,用以連接上側配線板3 5的上面配 線3 7的連接墊部。多數個錫球42係在上層過塗敷膜40的 上面配置爲矩陣狀。 • 在下側配線板21的下面設置由焊料阻劑等構成的下層 過塗敷膜43。在對應於下側配線板21的下面配線24的連接 墊的部分的下層過塗敷膜43設置開口部44。在開口部44 內設置金屬膏劑或導電性樹脂膏劑等構成的導電連接部 45。在下層過塗敷膜43的下面設置電容及電阻等構成的晶 片元件(電子零件)46,且使其兩側的電極連接於導電連接部 45 〇 但是,在半導體組塊1中,將支撐板2的尺寸設爲較半 ® 導體構成體3的尺寸還大某一程度,是爲了響應矽基板5上 的連接墊6的數量增加,將上層配線1 9的連接墊的配置區 域也設爲較半導體構成體3的尺寸大某一程度,藉以將上層 配線1 9的連接墊部的尺寸及間距也設爲較柱狀電極1 3的尺 寸及間距大。 因此配置爲矩陣狀的上層配線1 9的連接墊部,不僅僅 配置在對應於半導體構成體3的區域,還配置於對應設於半 導體構成體3側面外側的絕緣層1 5的區域上。也就是說, -11- 200529407 配置爲矩陣狀的上層配線1 9的連接墊部中至少爲最外周的 上層配線1 9的連接墊,係配置於較半導體構成體3還要外 側的位置周圍。 另外,在該半導體裝置中,在具有矽基板5之半導體組 塊1周圍的下側配線板2 1上面設置方形框狀的中間配線板 26,因此即使某種程度增大整體的平面尺寸,仍可減少矽基 板5的周圍產生的死區。 又,在該半導體裝置中,在半導體組塊1周圍的下側配 # 線板2 1上面設置方形框狀的中間配線板26,因此與取代中 間配線板26而單純設置絕緣層的情況比較,可設成高密度 配線構造。亦即,在取代中間配線板26而單純設置絕緣層 的情況,在該絕緣層形成通孔,其只連接上側配線35與下 側配線2 1,而無法設成高密度配線構造。 接著,說明該半導體裝置的製造方法的一例,首先,說 明半導體構成體3的製造方法的一例。該情況,首先如第2 圖所示,準備在晶圓狀態的矽基板(半導體基板)5上,設置 ® 由鋁系金屬等組成的連接墊6,由氧化矽等構成的絕緣膜7, 及由環氧系樹脂及聚醯亞胺系樹脂等所構成的保護膜9,介 由形成於絕緣膜7及保護膜9的開口部8、10而讓連接墊6 的中央部曝露者。在上述內容中,在晶圓狀態的矽基板5上, 在形成有各半導體構成體的區域形成有指定功能的積體電 路,連接墊6分別電氣連接於形成在對應區域的積體電路。 然後,如第3圖所示,在包含介由兩開口部8、1 0而曝 露之連接墊6上面的保護膜9的上面全體形成襯底金屬層 -12- 200529407 0 1 1。該情況,襯底金屬層1 1可僅僅爲由無電解電鍍所形成 的銅層,也可僅僅爲由濺鍍形成的銅層,又可爲在由濺鍍形 成的鈦等的薄膜層上藉由濺鍍形成銅層者。這對後述之上層 襯底金屬層18也相同。 然後,在襯底金屬層1 1上面圖案化形成電鍍阻劑膜 5 1。該情況,在對應於配線1 2形成區域的部分的電鍍阻劑 膜5 1上形成開口部5 2。接著,將襯底金屬層1 1作爲電鍍電 流通路進行銅的電解電鍍,藉以在電鍍阻劑膜5 1的開口部 # 52內的襯底金屬層1 1上面形成配線1 2。然後剝離電鍍阻劑 膜51 〇 然後,如第4圖所示,在包含配線12的襯底金屬層1 1 的上面圖案化形成電鍍阻劑膜53。該情況,在對應於柱狀電 極13形成區域的部分的電鍍阻劑膜53上形成開口部54。接 著將襯底金屬層1 1作爲電鍍電流通路進行銅的電解電鍍, 藉以在電鍍阻劑膜53的開口部54內的配線12的連接墊部 上面形成柱狀電極1 3。然後剝離電鍍阻劑膜53,接著,將 ® 配線1 2作爲遮罩蝕刻除去襯底金屬層1 1的不要部分,如第 5圖所示,僅在配線1 2下殘留襯底金屬層1 1。 然後,如第6圖所示,藉由網版印刷法、自旋塗敷法及 凹版塗敷法等,在包含柱狀電極1 3及配線1 2的保護膜9的 上面全體形成由環氧系樹脂及聚醯亞胺系樹脂等所構成的 封裝膜1 4,且使該封裝膜的厚度形成爲較柱狀電極1 3的高 度要厚。因此,在該狀態下,柱狀電極1 3的上面係由封裝 膜1 4所包覆。 -13- 200529407 然後,適量硏磨封裝膜1 4及柱狀電極1 3的上面側,如 第7圖所示,以使柱狀電極1 3的上面曝露,並且將含有該 曝露之柱狀電極1 3上面的封裝膜1 4上面進行平坦化處理。 在此,適量硏磨柱狀電極1 3的上面側,是因爲藉由電解電 鍍所形成的柱狀電極1 3的高度有誤差,而爲解消此誤差, 將柱狀電極1 3的高度均句化。 然後,如第8圖所示,將黏接層4黏接於矽基板5的下 面全體。黏接層4係由環氧系樹脂、聚醯亞胺系樹脂等的晶 # 片接合材所構成,且藉由加熱加壓而在半硬化狀態下固接於 矽基板5上。接著,對固接於矽基板5上的黏接層4貼合切 割膠帶(未圖示),在經過第9圖所示切割步驟後,從切割膠 帶予以剝離,如第1圖所示,即可獲得多個在矽基板5下面 具有黏接層4的半導體構成體3。 在如此般獲得之半導體構成體3中,在矽基板5下面具 有黏接層4,因此不需要在切割步驟後而在各半導體構成體 3之矽基板5下面分別設置黏接層的極爲麻煩的作業。又, I 在切割步驟後從切割膠帶予以剝離的作業,與在切割步驟後 而在各半導體構成體3之矽基板5下面分別設置黏接層的作 業比較,極爲簡單。 然後,使用如此般獲得的半導體構成體3,說明製造第 1圖所示半導體組塊1的情況的一例。首先,如第1 〇圖所示, 以可採取多片第1圖所示支撐板2的大小尺寸,雖非限定之 意味,但準備平面方形的支撐板2。接著,將分別黏接於半 導體構成體3的矽基板5的下面的黏接層4黏接於支撐板2 -14- 200529407 上面的指定的複數部位。在此之黏接是藉由加熱加壓而使黏 接層4硬化。 然後,如第11圖所示,在半導體構成體3周圍的支撐 板2上面,例如,藉由網版印刷法或自旋塗敷法等,形成絕 緣層形成用層15a。絕緣層形成用層15a,如係環氧系樹脂 及聚醯亞胺系樹脂等的熱硬化性樹脂、或在此種熱硬化性樹 脂中混入玻璃纖維或二氧化矽塡料等的補強材者。 然後在半導體構成體3及絕緣層形成用層15a的上面配 # 置上層絕緣膜形成用片16a。上層絕緣膜形成用片16a,雖 非限定之意味,但以片狀疊層材爲較佳,該疊層材具有在環 氧系樹脂等的熱硬化性樹脂中混入二氧化矽塡料,以使熱硬 化性樹脂形成爲半硬化狀態者。又,上層絕緣膜形成用片1 6a 也可使用將環氧系樹脂等的熱硬化性樹脂含浸於玻璃等的 無機材料構成的織布或不織布內,在將熱硬化性樹脂形成爲 半硬化狀態下形成爲片狀的半固化片材、或、未混入二氧化 矽塡料而僅由熱硬化性樹脂所構成的片狀者。 • 然後,如第1 2圖所示,使用一對加熱加壓板5 5、5 6而 從上下方向加熱加壓絕緣層形成用層15a及上層絕緣膜形成 用片1 6a。於是,在半導體構成體3周圍的支撐板2的上面 形成絕緣層1 5,在半導體構成體3及絕緣層1 5的上面形成 上層絕緣膜1 6。該情況,上層絕緣膜1 6的上面係由上側的 加熱加壓板5 5的下面所頂壓,而成爲平坦面。因此,不需 要用於使上層絕緣膜1 6的上面平坦化的硏磨步驟。 然後,如第1 3圖所示,藉由照射雷射束的雷射加工, -15- 200529407 在對應於柱狀電極1 3上面中央部的部分的上層絕緣膜1 6上 形成開口部1 7 °然後根據需要藉由反拖尾處理除去開口部 17內等所產生的環氧塗膜等。然後,如第14圖所示,在包 含介由開口部1 7曝露的柱狀電極! 3上面的上層絕緣膜i 6 的上面全體’藉由銅的無電解電鍍形成上層襯底金屬層18。 然後,在上層襯底金屬層1 8的上面圖案形成電鍍阻劑膜 57。該情況,在對應於上層配線丨9形成區域的部分的電鍍 阻劑膜57上形成開口部58。 # 然後,將上層襯底金屬層1 8作爲電解電流通路進行銅 的電解電鍍,在電鍍阻劑膜57的開口部58內的上層襯底金 屬層18的上面形成上層配線19。然後,剝離電鍍阻劑膜57, 接著,將上層配線1 9作爲遮罩,蝕刻除去上層襯底金屬層 1 8的不要部分,如第1 5圖所示,僅在上層配線1 9下殘留上 層襯底金屬層18。然後,如第16圖所示,在相互鄰接之半 導體構成體3之間,切斷上層絕緣膜1 6、絕緣層1 5及支撐 板2,獲得多個第1圖所示半導體組塊1。 ® 然後,使用如此般獲得的半導體組塊1,說明製造第1 圖所示半導體裝置的情況的一例。首先,如第1 7圖所示, 以可採取多片第1圖所示下側配線板2 1的大小尺寸,雖非 限定之意味,但準備平面方形的下側集合配線板2 1 a。然後 準備與下側集合配線板2 1 a相同大小的上側集合配線板 35a。又,準備形成與下側集合配線板2 1 a相同大小的中間 集合配線板26a用的第1〜第3絕緣基板27〜29。 在此,各集合配線板2 1 a、2 6 a、3 5 a的基本構造相同, -16- 200529407
P 因此代表性說明下側集合配線板2 1 a的形成方法的一例。首 先,準備在半固化片材或疊層材構成的板狀絕緣基板22的 一面或上下面,疊層銅箔的附銅箔配線用基板。該情況,絕 緣基板22中的環氧系樹脂等的熱硬化性樹脂成爲半硬化狀 態。接著,在絕緣基板22藉由光微影技術或照射雷射束的 雷射加工形成連通孔,在連通孔內充塡金屬膏劑等以形成連 通部25,塗案加工疊層於絕緣基板22的一面或上下面的銅 箔,形成上面配線23及下面配線24。該情況,連通部25 • 也可將導電材料構成的銷柱壓入連通孔內來形成。 作爲其他的方法,在形成連通孔後,藉由無電解電鍍與 電解電鍍、或藉由濺鍍與電解電鍍,可形成上面配線23、下 面配線24及連通部25。又,在第1〜第3絕緣基板27〜29 的情況,然後,藉由沖壓形成多個方形的開口部6 1,將平面 形狀設爲格子狀。 然後,分別將半導體組塊1的支撐板2下面暫時壓合於 下側集合配線板2 1 a的絕緣基板22上面的指定的多個部 ® 位。亦即,使用附加熱機構的晶片接合工具(未圖示),在預 加熱的狀態下邊施加一定壓力邊將半導體組塊1暫時壓合於 含有半硬化狀態的熱硬化性樹脂的絕緣基板2 2上面的指定 部位。暫時壓合條件的一例,爲溫度90〜130°C,壓力0.1 〜1 M p a 〇 然後,在半導體組塊1周圍的下側集合配線板2 1 a上 面,邊由銷等進行定位邊配置第1〜第3絕緣基板27〜29。 在該狀態下,第1〜第3絕緣基板27〜29的開口部6 1的尺 -17- 200529407 寸較半導體組塊1的尺寸略大,因此在第1〜第3絕緣基板 27〜29的開口部6 1與半導體組塊1間形成間隙62。另外, 在該狀態下,第2絕緣板28的上面係配置於較半導體組塊i 的上面略高的位置。 然後’在第2絕緣板28的上面邊由銷等進行定位邊配 置上側集合配線板3 5 a。在上述步驟中,將半導體組塊1及 第1〜第3絕緣基板27〜29配置於下側集合配線板2 1 a上的 順序,也可相反,可先配置第1〜第3絕緣基板27〜29後, ® 在該第1〜第3絕緣基板27〜29的各開口部6 1內配置半導 體組塊1。 然後,如第1 8圖所示,使用一對加熱加壓板6 3、64而 從上下方向加熱加壓下側集合配線板2 1 a、第1〜第3絕緣 基板27〜29及上側集合配線板35a。於是,下側集合配線板 2 1 a的絕緣基板22中的熱硬化性樹脂硬化,而將半導體組塊 1的支撐板2下面固接於絕緣基板22上面。 另外,擠壓出第1〜第3絕緣基板27〜29中的以熔化的 ® 熱硬化性樹脂,充塡於第1 7圖所示間隙62內,且將該熱硬 化性樹脂硬化,與第1〜第3絕緣基板27〜29 —體化,將中 間集合配線板26a固接形成於半導體組塊1的側面及下側集 合配線板2 1 a的上面。又,上側集合配線板3 5 a的絕緣基板 36中的熱硬化性樹脂硬化,而將上側集合配線板35a固接於 半導體組塊1及中間集合配線板26a上面。 在該狀態下,在中間集合配線板26a中’第2絕緣板28 的連通部30與第3絕緣板29的連通部3 1,係介由第1絕緣 200529407
P 基板27的上面配線33、連通部32及下面配線34所連接。 另外,中間集合配線板26a的第3絕緣板29的連通部3 1係 連接於下側集合配線板2 1 a的上面配線23。另外,上側集合 配線板3 5 a的下面配線3 8係連接於中間集合配線板26a的 第2絕緣板28的連通部30。又,上側集合配線板35a的連 通部39的一部分係連接於半導體組塊1的上層配線1 9的連 接墊部。 如此般,藉由使用一對加熱加壓板63、64的上下方向 # 的加熱加壓,將下側集合配線板2 1 a、中間集合配線板26a 及上側集合配線板35a —體化,並將半導體組塊1固接於下 側集合配線板2 1 a的上面,又,由中間集合配線板26a及上 側集合配線板35a包覆半導體組塊1的側面及上面,因此, 可減少製造步驟數。又,上述中,中間集合配線板26a係相 互預先暫時黏接第1〜第3絕緣基板27〜29,並將該暫時黏 接者配置於上側集合配線板35a及下側集合配線板21a之 間,使用一對加熱加壓板63、64進行加熱加壓即可。 • 接著,如第19圖所示,藉由網版印刷法、自旋塗敷法 等,在上側集合配線板35a的上面設置由焊料阻劑等構成的 上層過塗敷膜4 0,另外,在下側集合配線板2 1 a的下面設置 由焊料阻劑等構成的下層過塗敷膜43。該情況,在對應於上 側集合配線板35a的上面配線37的連接墊的部分的上層過 塗敷膜40形成開口部4 1。在對應於下側集合配線板2 1 a的 下面配線24的連接墊的部分的下層過塗敷膜43形成開口部 4 4° -19- 200529407 β 然後,在下層過塗敷膜43的開口部44內形成由金屬膏 劑等構成的導電連接部45以連接於下面配線24的另一端 部。接著,在下層過塗敷膜43的下面設置電容及電阻等組 成的晶片元件46以使其兩側的電極連接於導電連接部45。 然後,在上層過塗敷膜40的開口部4 1內及其上方形成錫球 42,用以連接上面配線37的連接墊部。接著,在相互鄰接 之半導體構成體3之間,切斷上層過塗敷膜40、上側集合配 線板35a、中間集合配線板26a、下側集合配線板21a及下 • 層過塗敷膜43,獲得多個第1圖所示半導體裝置。 (第2實施形態) 第20圖顯示本發明之第2實施形態的半導體裝置的剖 面圖。在該半導體裝置中,與第1圖所示情況的主要差異點 在於,半導體組塊1係在含有上層配線1 9的上層絕緣膜1 6 上面設置由焊料阻劑等構成的上層過塗敷膜7 1,在對應於上 層配線1 9的連接墊的部分的上層過塗敷膜71形成開口部 72,在開口部72內形成由金屬膏劑等構成的導電連接部73 •以連接於上層配線1 9的連接墊部。上層配線板3 5的下面配 線38係連接於半導體組塊1的導電連接部73。 在製造該半導體裝置的情況,在第1實施形態的對應第 17圖所示步驟中,如第21圖所示,其與第20圖所示情況上 下相反,通過將半導體組塊1的導電連接部73連接於上層 配線板3 5的下面配線3 8,將半導體組塊1配置於上層配線 板35的上面,在半導體組塊1周圍的上側集合配線板35a 上面配置第1〜第3絕緣基板27〜29,在第3絕緣基板29 -20- 200529407 上面配置下側集合配線板2 1 a。 (第3實施形態) 在第1、第2實施形態中,在半導體構成體3的周圍構 成設有絕緣層1 5的半導體組塊1,在該半導體組塊1的周圍 設置中間配線板26。相對於此,在第23圖所示第3實施形 態中,在半導體構成體3的周圍具有直接設置中間配線板26 的構成。在該第3實施形態中,可縮小省略了絕緣層1 5的 部分的半導體裝置全體的面積。第3實施形態之其他構成’ φ 與第1實施形態相同,故而針對對應的元件賦以相同的元件 符號,並省略其說明。但是,黏接層4係在加熱加壓半硬化 狀態的支撐板2而進行硬化時,藉由支撐板2的固接力而保 持半導體構成體3的矽基板5的構成,故而省略。另外’在 該第3寳施形態中,上層絕緣膜16僅形成於半導體構成體3 的上面,但實質上還可將中間配線板26的上面與半導體構 成體3的上面設爲相同面,將上層絕緣膜1 6設爲跨越中間 配線板26的上面與半導體構成體3的上面而包覆全體。 ♦(其他的實施形態) 在上述實施形態中,作爲中間配線板26,係使用多層配 線板,例如,針對使用疊層由疊層材構成的第1〜第3絕緣 基板27〜29所成者的情況進行了說明,但不限於此,例如, 還可使用具有通孔電鍍導通部的兩面配線構造。 另外,在上述實施形態中,半導體構成體3具有作爲外 部連接用電極的柱狀電極1 3,但不限於此,也可不具有柱狀 電極,而具有作爲外部連接用電極的具有連接墊部的配線 -2 1 - 200529407 1 2,另外,也可不具有柱狀電極及配線,而具有作爲外部連 接用電極的連接墊6。另外,在上述實施形態中,針對將半 導體組塊1的上層配線設爲1層的情況進行了說明,但不限 於此,也可設爲2層以上。 另外,在上述實施形態中,係在相互鄰接之半導體構成 體3間進行切斷,但不限於此,還可將2個或其以上的半導 體構成體3作爲一組進行切斷。該情況,複數個一組的半導 體構成體3可爲同種或異種的任一者。 ® 另外,在上述實施形態中,作爲電子零件搭載有晶片元 件46,但不限於此,也可搭載裸晶片或由CSP等所構成的 半導體構成體。另外,無論是在搭載晶片元件的情況,還是 在搭載半導體構成體的情況,也可取代導電連接部45,而使 用錫球。另外,也可取代第20圖所示導電連接部73,而使 用錫球。 【圖式簡單說明】 第1圖爲顯示本發明之第1實施形態的半導體裝置的剖 面圖。 第2圖爲第1圖所示半導體構成體的製造時,初期準備 者的剖面圖。 第3圖爲接續第2圖的製造步驟的剖面圖。 第4圖爲接續第3圖的製造步驟的剖面圖。 第5圖爲接續第4圖的製造步驟的剖面圖。 第6圖爲接續第5圖的製造步驟的剖面圖。 第7圖爲接續第6圖的製造步驟的剖面圖。 -22- 200529407 第8圖爲接續第7圖的製造步驟的 第9圖爲接續第8圖的製造步驟的 第1 〇圖爲接續第9圖的製造步驟t 第1 1圖爲接續第1 〇圖的製造步驟 第1 2圖爲接續第1 1圖的製造步驟 第1 3圖爲接續第1 2圖的製造步驟 第14圖爲接續第13圖的製造步驟 第1 5圖爲接續第1 4圖的製造步驟 • 第1 6圖爲接續第1 5圖的製造步驟 第1 7圖爲接續第1 6圖的製造步驟 第1 8圖爲接續第1 7圖的製造步驟 第1 9圖爲接續第1 8圖的製造步驟 第20圖爲顯示本發明之第2實施 剖面圖。 第21圖爲第20圖所示半導體構成 驟的剖面圖。 • 第22圖爲顯示本發明之第3實施 剖面圖。 【元件符號說明】 1 半導體組塊 2 支撐板 3 半導體構成體 4 黏接層 5 矽基板(半導體基板) 剖面圖。 剖面圖。 Ϊ勺剖面圖。 的剖面圖。 的剖面圖。 的剖面圖。 的剖面圖。 的剖面圖。 的剖面圖。 的剖面圖。 的剖面圖。 的剖面圖。 形態的半導體裝置的 體的製造時,指定步 形態的半導體裝置的 -23- 200529407
6 連 接 墊 7 絕 緣 膜 8 開 □ 部 9 保 護 膜 10 開 □ 部 11 襯 底 金 屬 層 12 配 線 13 柱 狀 電 極 14 封 裝 膜 15 絕 緣 層 16 上 層 絕 緣 膜 17 開 □ 部 18 上 層 襯 底 金屬層 19 上 層 配 線 (第 2配 線) 2 1 下 側 配 線 板 22 絕 緣 基 板 23 上 面 配 線 (第 3配 線) 24 下 面 配 線 (第 3配 線) 25、30、 31、 32 > > 39 運通 26 中 間 配 線 板 27 〜29 第 1 第 3絕 丨緣基板 33 上 面 配 線 (第 1配 線) 34 下 面 配 線 (第 1配 線) 35 上 側 配 線 板 - 24- 200529407 36 絕 緣 基 板 37 上 面 配 線 (第4 配 線) 38 下 面 配 線 (第4 配 線)) 40 上 層 過 塗 敷膜 41 開 □ 部 42 錫 球 43 下 層 ciH, m 塗 敷膜 44 開 □ 部 45 導 電 連 接 部 46 晶 片 元 件 (電子 零 件) 55、 56 、 63 、 64 加熱 加 壓板 -25-
Claims (1)
- 200529407 • * 十、申請專利範圍: 1· 一種半導體裝置,其特徵爲具備: 基底構件(22);設於基底構件(2 2)上,且具有半導體基 板(5)及設於該半導體基板(5)上的多個外部連接用電極 (13)的半導體構成體(3);設於半導體構成體(3)周圍,至少 於一面具有第1配線(3 3、34)的配線板(26);及設在半導 體構成體(3)及配線板(26)上,連接於半導體構成體(3)的外 部連接用電極(13)的第2配線(19)。 ® 2·如申請專利範圍第1項之半導體裝置,其中半導體構成體 (3)具有形成於半導體基板(5)的外部連接用電極(13)間的 封裝膜(14)。 3·如申請專利範圍第1項之半導體裝置,其中基底構件(22) 係在至少一面具有電氣地連接於配線板(26)的第1配線 (33、34)的第 3 配線(23、24)。 4·如申請專利範圍第1項之半導體裝置,其中基底構件(2 2) 係由含有熱硬化性樹脂的材料構成。 ® 5·如申請專利範圍第4項之半導體裝置,其中基底構件(22) 係由含有補強材的材料構成。 6·如申請專利範圍第4項之半導體裝置,其中在半導體構成 體(3)及第2配線(19)上形成對向面側絕緣膜(36)。 7 .如申請專利範圍第6項之半導體裝置,其中對向面側絕緣 膜(3 6)具有與基底構件(22)實質相同的面積。 8 .如申請專利範圍第6項之半導體裝置,其中對向面側絕緣 膜(3 6)係由含有熱硬化性樹脂的材料構成。 -26- 200529407 9.如申請專利範圍第6項之半導體裝置,其中對向面側絕緣 膜(36)係由含有補強材的材料構成。 10.如申請專利範圍第6項之半導體裝置,其中在對向面側絕 緣膜(36)上形成有第4配線(37)。 1 1.如申請專利範圍第10項之半導體裝置,其中第4配線(37) 係於對向面側絕緣膜(3 6)上延出,具有對應於配線板(2 6) 而配置於其上方的連接墊部。 12.如申請專利範圍第11項之半導體裝置,其中具有包覆除設 • 於對向面側絕緣膜(36)上的第4配線(37)的連接墊部的部 分外的過塗敷膜(40)。^ 1 3 .如申請專利範圍第1 2項之半導體裝置,其中在過塗敷膜 (40)表面設有錫球(42)以連接連接墊部。 14.如申請專利範圍第1項之半導體裝置,其中配線板(26)係 由多層配線板所構成。 15·如申請專利範圍第1項之半導體裝置,其中在半導體構成 體(3)與配線板(26)之間設有絕緣層(15)。 ® 16.如申請專利範圍第1項之半導體裝置,其中在半導體構成 體(3)上面設有上層絕緣層(16),第2配線(19)係設於上層 絕緣層(1 6 )上。 17·如申請專利範圍第1項之半導體裝置,其中在半導體構成 體(3)與基底構件(22)之間配置支撐板(2)。 18·如申請專利範圍第1項之半導體裝置,其中半導體構成體 (3)係藉由基底構件(22)的固接力而保持於該基底構件 (22)〇 -27- 200529407 19·如申請專利範圍第1項之半導體裝置,其中半導體構成體 (3)具有形成於作爲外部連接用電極(13)的柱狀電極及半 導體基板(5)上的柱狀電極間的封裝膜(14)。 2 0·如申請專利範圍第1項之半導體裝置,其中半導體構成體 (3),係讓具有較半導體基板(5)大的面積且用以支撐半導 體基板(5)的支撐板(2)、半導體基板(5)及包覆封裝膜(14) 側面的絕緣層(15)形成爲一體,並與半導體基板(5)、柱狀 電極(13)、封裝膜(14)、支撐板(2)及絕緣層(15)共同構成 Φ 半導體組塊(1)。 21·如申請專利範圍第1項之半導體裝置,其中基底構件(21) 在搭載有半導體構成體(3)之面的相反面具有第3配線 (24),且將電子零件(46)電氣連接於第3配線(24)。-28-
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JP (1) | JP4055717B2 (zh) |
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2004
- 2004-01-27 JP JP2004018535A patent/JP4055717B2/ja not_active Expired - Fee Related
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2005
- 2005-01-21 US US11/041,040 patent/US7064440B2/en not_active Expired - Fee Related
- 2005-01-26 TW TW094102226A patent/TWI253743B/zh active
- 2005-01-26 KR KR1020050006930A patent/KR100595891B1/ko not_active IP Right Cessation
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CN100341127C (zh) | 2007-10-03 |
CN1649119A (zh) | 2005-08-03 |
US20050161823A1 (en) | 2005-07-28 |
TWI253743B (en) | 2006-04-21 |
KR20050077272A (ko) | 2005-08-01 |
JP2005216935A (ja) | 2005-08-11 |
US7064440B2 (en) | 2006-06-20 |
JP4055717B2 (ja) | 2008-03-05 |
KR100595891B1 (ko) | 2006-06-30 |
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