TW200503179A - Integration method of a semiconductor device having a recessed gate electrode - Google Patents

Integration method of a semiconductor device having a recessed gate electrode

Info

Publication number
TW200503179A
TW200503179A TW092123866A TW92123866A TW200503179A TW 200503179 A TW200503179 A TW 200503179A TW 092123866 A TW092123866 A TW 092123866A TW 92123866 A TW92123866 A TW 92123866A TW 200503179 A TW200503179 A TW 200503179A
Authority
TW
Taiwan
Prior art keywords
transistors
gate electrode
recessed gate
semiconductor device
integration method
Prior art date
Application number
TW092123866A
Other languages
English (en)
Other versions
TWI278969B (en
Inventor
Ji-Young Kim
Hyoung-Sub Kim
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of TW200503179A publication Critical patent/TW200503179A/zh
Application granted granted Critical
Publication of TWI278969B publication Critical patent/TWI278969B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
TW092123866A 2003-07-14 2003-08-29 Integration method of a semiconductor device having a recessed gate electrode TWI278969B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR10-2003-0048079A KR100511045B1 (ko) 2003-07-14 2003-07-14 리세스된 게이트 전극을 갖는 반도체 소자의 집적방법

Publications (2)

Publication Number Publication Date
TW200503179A true TW200503179A (en) 2005-01-16
TWI278969B TWI278969B (en) 2007-04-11

Family

ID=29997551

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092123866A TWI278969B (en) 2003-07-14 2003-08-29 Integration method of a semiconductor device having a recessed gate electrode

Country Status (7)

Country Link
US (2) US6939765B2 (zh)
JP (1) JP4477953B2 (zh)
KR (1) KR100511045B1 (zh)
CN (1) CN1577802A (zh)
DE (1) DE10359493B4 (zh)
GB (1) GB2404083B (zh)
TW (1) TWI278969B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7553737B2 (en) 2006-06-08 2009-06-30 Nanya Technology Corp. Method for fabricating recessed-gate MOS transistor device
TWI455188B (zh) * 2007-02-21 2014-10-01 Samsung Electronics Co Ltd 包括其間具有步進差異之閘極圖案之半導體積體電路裝置，配置在閘極圖案之間之連接線，以及製造其之方法

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KR100500472B1 (ko) * 2003-10-13 2005-07-12 삼성전자주식회사 리세스 게이트 트랜지스터 구조 및 형성방법
KR100615593B1 (ko) * 2004-05-06 2006-08-25 주식회사 하이닉스반도체 리세스채널을 구비한 반도체소자의 제조 방법
KR100608369B1 (ko) * 2004-11-08 2006-08-09 주식회사 하이닉스반도체 주변영역에의 모스펫 소자 제조방법
KR100603931B1 (ko) * 2005-01-25 2006-07-24 삼성전자주식회사 반도체 소자 제조방법
JP4944766B2 (ja) * 2005-02-25 2012-06-06 スパンション エルエルシー 半導体装置及びその製造方法
US7384849B2 (en) * 2005-03-25 2008-06-10 Micron Technology, Inc. Methods of forming recessed access devices associated with semiconductor constructions
DE102006016550B4 (de) * 2005-04-09 2010-04-29 Samsung Electronics Co., Ltd., Suwon-si Feldeffekttransistoren mit vertikal ausgerichteten Gate-Elektroden und Verfahren zum Herstellen derselben
US7214621B2 (en) * 2005-05-18 2007-05-08 Micron Technology, Inc. Methods of forming devices associated with semiconductor constructions
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KR100625126B1 (ko) * 2005-08-16 2006-09-15 삼성전자주식회사 반도체 장치 및 이의 제조 방법
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KR100711520B1 (ko) * 2005-09-12 2007-04-27 삼성전자주식회사 리세스된 게이트 전극용 구조물과 그 형성 방법 및리세스된 게이트 전극을 포함하는 반도체 장치 및 그 제조방법.
KR100703027B1 (ko) 2005-09-26 2007-04-06 삼성전자주식회사 리세스 게이트 형성 방법
KR100689840B1 (ko) * 2005-10-04 2007-03-08 삼성전자주식회사 리세스된 게이트 전극을 갖는 반도체소자 및 그의 제조방법
JP4773182B2 (ja) * 2005-10-28 2011-09-14 エルピーダメモリ株式会社 半導体装置の製造方法
KR100704475B1 (ko) * 2005-12-28 2007-04-09 주식회사 하이닉스반도체 듀얼 폴리 리세스 게이트를 갖는 반도체 소자의 제조방법
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JP4600834B2 (ja) * 2006-07-13 2010-12-22 エルピーダメモリ株式会社 半導体装置の製造方法
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US7883965B2 (en) * 2006-07-31 2011-02-08 Hynix Semiconductor Inc. Semiconductor device and method for fabricating the same
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7553737B2 (en) 2006-06-08 2009-06-30 Nanya Technology Corp. Method for fabricating recessed-gate MOS transistor device
TWI455188B (zh) * 2007-02-21 2014-10-01 Samsung Electronics Co Ltd 包括其間具有步進差異之閘極圖案之半導體積體電路裝置，配置在閘極圖案之間之連接線，以及製造其之方法

Also Published As

Publication number Publication date
DE10359493B4 (de) 2010-05-12
KR100511045B1 (ko) 2005-08-30
DE10359493A1 (de) 2005-02-17
KR20050008223A (ko) 2005-01-21
GB2404083B (en) 2005-11-02
US6939765B2 (en) 2005-09-06
TWI278969B (en) 2007-04-11
GB2404083A (en) 2005-01-19
US20050014338A1 (en) 2005-01-20
GB0327716D0 (en) 2003-12-31
CN1577802A (zh) 2005-02-09
JP4477953B2 (ja) 2010-06-09
JP2005039270A (ja) 2005-02-10
US20050275014A1 (en) 2005-12-15

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