JP4944766B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
- Publication number
- JP4944766B2 JP4944766B2 JP2007504608A JP2007504608A JP4944766B2 JP 4944766 B2 JP4944766 B2 JP 4944766B2 JP 2007504608 A JP2007504608 A JP 2007504608A JP 2007504608 A JP2007504608 A JP 2007504608A JP 4944766 B2 JP4944766 B2 JP 4944766B2
- Authority
- JP
- Japan
- Prior art keywords
- bit line
- region
- trench isolation
- semiconductor substrate
- view
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
Description
Claims (3)
- 半導体基板と、
前記半導体基板上に形成されたONO膜と、
前記半導体基板内に形成され、かつ、平面視において前記ONO膜のそれぞれを挟むように延びる複数のビットラインと、
前記複数のビットラインのそれぞれと電気的に接続する接続部とを有し、
前記半導体基板は、平面視において前記接続部を挟み込むように前記複数のビットラインのそれぞれの両側に設けられたトレンチ分離領域を有し、
前記複数のビットラインは、平面視において、前記半導体基板の上方に形成された複数のワードラインと交差しており、
前記トレンチ分離領域同士の間に不純物注入領域があり、
前記不純物領域は、前記複数のビットラインのそれぞれから突出しており、かつ、前記複数のビットラインのそれぞれに隣接しており、さらに、前記トレンチ分離領域のそれぞれに接している、半導体装置。 - 前記複数のワードラインのそれぞれの前記接続部が設けられている側の側部に側壁を具備する、請求項1記載の半導体装置。
- 前記側壁が窒化シリコン膜である、請求項2記載の半導体装置。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2005/003213 WO2006090477A1 (ja) | 2005-02-25 | 2005-02-25 | 半導体装置及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2006090477A1 JPWO2006090477A1 (ja) | 2008-07-24 |
JP4944766B2 true JP4944766B2 (ja) | 2012-06-06 |
Family
ID=36927128
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007504608A Expired - Fee Related JP4944766B2 (ja) | 2005-02-25 | 2005-02-25 | 半導体装置及びその製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7968404B2 (ja) |
JP (1) | JP4944766B2 (ja) |
WO (1) | WO2006090477A1 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7642158B2 (en) * | 2005-09-30 | 2010-01-05 | Infineon Technologies Ag | Semiconductor memory device and method of production |
BRPI0806696A2 (pt) | 2007-01-12 | 2015-06-16 | Alcon Res Ltd | Visão intermediária aperfeiçoada com óptica multifocal fácica utilizando acomodação residual. |
US11080454B2 (en) * | 2019-08-30 | 2021-08-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit, system, and method of forming the same |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11186528A (ja) * | 1997-12-25 | 1999-07-09 | Sony Corp | 不揮発性半導体記憶装置及びその製造方法 |
JP2003174106A (ja) * | 2001-12-07 | 2003-06-20 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP2003224213A (ja) * | 2002-01-30 | 2003-08-08 | Mitsubishi Electric Corp | 不揮発性半導体記憶装置 |
JP2004039866A (ja) * | 2002-07-03 | 2004-02-05 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2004111737A (ja) * | 2002-09-19 | 2004-04-08 | Fasl Japan Ltd | 半導体装置の製造方法 |
JP2004193178A (ja) * | 2002-12-06 | 2004-07-08 | Fasl Japan 株式会社 | 半導体記憶装置及びその製造方法 |
JP2004349312A (ja) * | 2003-05-20 | 2004-12-09 | Sharp Corp | 半導体記憶装置 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6232181B1 (en) | 1999-10-21 | 2001-05-15 | United Microelectronics Corp. | Method of forming a flash memory |
US6271088B1 (en) | 2001-01-05 | 2001-08-07 | United Microelectronics Corp. | Method for fabricating a buried vertical split gate memory device with high coupling ratio |
US6562675B1 (en) * | 2001-08-17 | 2003-05-13 | Cypress Semiconductor Corp. | Adjustment of threshold voltages of selected NMOS and PMOS transistors using fewer masking steps |
US6828623B1 (en) | 2002-08-30 | 2004-12-07 | Advanced Micro Devices, Inc. | Floating gate memory device with homogeneous oxynitride tunneling dielectric |
DE10246343B4 (de) | 2002-10-04 | 2007-02-08 | Infineon Technologies Ag | Verfahren zur Herstellung eines Halbleiterspeicherzellenfeldes |
US20040079984A1 (en) * | 2002-10-25 | 2004-04-29 | Hsuan-Ling Kao | Polysilicon self-aligned contact and a polysilicon common source line and method of forming the same |
US6847087B2 (en) | 2002-10-31 | 2005-01-25 | Ememory Technology Inc. | Bi-directional Fowler-Nordheim tunneling flash memory |
TW591761B (en) | 2003-07-11 | 2004-06-11 | Macronix Int Co Ltd | NAND type binary nitride read only memory and the manufacturing method |
KR100511045B1 (ko) * | 2003-07-14 | 2005-08-30 | 삼성전자주식회사 | 리세스된 게이트 전극을 갖는 반도체 소자의 집적방법 |
US7423312B1 (en) * | 2004-07-20 | 2008-09-09 | Spansion Llc | Apparatus and method for a memory array with shallow trench isolation regions between bit lines for increased process margins |
KR100630725B1 (ko) | 2004-12-17 | 2006-10-02 | 삼성전자주식회사 | 매립된 비트라인을 가진 반도체 소자 및 그 제조방법 |
-
2005
- 2005-02-25 WO PCT/JP2005/003213 patent/WO2006090477A1/ja not_active Application Discontinuation
- 2005-02-25 JP JP2007504608A patent/JP4944766B2/ja not_active Expired - Fee Related
-
2006
- 2006-02-24 US US11/361,630 patent/US7968404B2/en not_active Expired - Fee Related
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11186528A (ja) * | 1997-12-25 | 1999-07-09 | Sony Corp | 不揮発性半導体記憶装置及びその製造方法 |
JP2003174106A (ja) * | 2001-12-07 | 2003-06-20 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP2003224213A (ja) * | 2002-01-30 | 2003-08-08 | Mitsubishi Electric Corp | 不揮発性半導体記憶装置 |
JP2004039866A (ja) * | 2002-07-03 | 2004-02-05 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2004111737A (ja) * | 2002-09-19 | 2004-04-08 | Fasl Japan Ltd | 半導体装置の製造方法 |
JP2004193178A (ja) * | 2002-12-06 | 2004-07-08 | Fasl Japan 株式会社 | 半導体記憶装置及びその製造方法 |
JP2004349312A (ja) * | 2003-05-20 | 2004-12-09 | Sharp Corp | 半導体記憶装置 |
Also Published As
Publication number | Publication date |
---|---|
WO2006090477A1 (ja) | 2006-08-31 |
US7968404B2 (en) | 2011-06-28 |
JPWO2006090477A1 (ja) | 2008-07-24 |
US20060263989A1 (en) | 2006-11-23 |
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