WO2006090477A1 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
- Publication number
- WO2006090477A1 WO2006090477A1 PCT/JP2005/003213 JP2005003213W WO2006090477A1 WO 2006090477 A1 WO2006090477 A1 WO 2006090477A1 JP 2005003213 W JP2005003213 W JP 2005003213W WO 2006090477 A1 WO2006090477 A1 WO 2006090477A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- bit line
- semiconductor substrate
- region
- trench isolation
- semiconductor device
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 78
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 44
- 238000000034 method Methods 0.000 title abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 238000002955 isolation Methods 0.000 claims description 50
- 230000002093 peripheral effect Effects 0.000 claims description 13
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 2
- 230000015654 memory Effects 0.000 abstract description 37
- 239000010408 film Substances 0.000 description 68
- 238000005468 ion implantation Methods 0.000 description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 16
- 229910052710 silicon Inorganic materials 0.000 description 16
- 239000010703 silicon Substances 0.000 description 16
- 239000011229 interlayer Substances 0.000 description 10
- 239000010410 layer Substances 0.000 description 9
- 230000001681 protective effect Effects 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- -1 Metal Oxide Nitride Chemical class 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
Definitions
- the present invention relates to a nonvolatile memory and a manufacturing method thereof, and more particularly to a nonvolatile memory having an ONO (Oxide Nitride Oxide) film and a manufacturing method thereof.
- ONO Oxide Nitride Oxide
- nonvolatile memories which are semiconductor devices capable of rewriting data
- technical development for the purpose of miniaturization of the memory cell is being advanced because of the high storage capacity.
- a floating gate type flash memory that accumulates electric charges in a floating gate has been widely used.
- a thin film of a tunnel oxide film is required.
- the thin film of the tunnel oxide film increases the leakage current that flows through the tunnel oxide film, and the charge accumulated in the floating gate is lost due to the introduction of defects in the tunnel oxide film. This is because a failure in reliability will occur.
- a flash memory having an ONO (Oxide / Nitride / Oxide) film such as a MONOS (Metal Oxide Nitride Oxide Silicon) type or a SONOS (Silicon Oxide Nitride Oxide Silicon) type.
- ONO Oxide / Nitride / Oxide
- MONOS Metal Oxide Nitride Oxide Silicon
- SONOS Silicon Oxide Nitride Oxide Silicon
- charges are accumulated in the silicon nitride film layer, which is an insulating film. Therefore, even if there is a defect in the tunnel oxide film, charge loss is unlikely to occur as in the floating gate type.
- a flash memory having an ONO film is described in Non-Patent Document 1, for example.
- FIG. 1 is a top view of the memory cell area of the prior art (the protective film 32, the interlayer insulating film 30, the wiring 34, and the ONO film 16 are not shown), and Fig. 2 is an enlarged view of Fig. 1.
- FIG. 3 is a cross-sectional view of FIG. 2
- FIG. 4 is a cross-sectional view of FIG.
- Bit lines 14 are formed in predetermined regions of the P-type silicon semiconductor substrate 10.
- An ONO film 16 is formed on the semiconductor substrate 10 as an oxide silicon film that is a tunnel oxide film, a silicon nitride film that is a trap layer, and an oxide silicon film that is a top oxide film layer.
- a polycrystalline silicon film is formed as a word line 20 serving as a gate of the core cell in a predetermined region on the ONO film 16.
- bit line connection region 42 In the bit line connection region 42, the bit line 14 and the wiring 34 are connected via a connection hole 40 formed in the interlayer insulating film 30. A protective film 32 is formed on the wiring.
- the bit line connection region 42 is a region where the connection holes 40 are arranged in a row in the direction of the word line 20.
- the bit line connection area 42 is provided at intervals of one word line 20. In order to miniaturize memory cells, it is required to reduce the bit line interval and the word line interval including the bit line connection region 42.
- Non-Patent Document 1 Boaz Eitan et. Al, Electron Device Letters, Vol. 21, No. 11
- FIG. 5 is a diagram in the case where the connection hole 40 is formed to be shifted to the left with respect to the bit line 14.
- the contact hole 40 force SP type silicon semiconductor substrate: is in contact with L0. Due to the 55 junction, a leak current flows between the bit line 14 and the semiconductor substrate 10 through the connection hole 40. In order to prevent this, if the bit line 14 and the connection hole 40 are secured with a sufficient margin for exposure and the width and interval of the bit line 14 are determined, it is difficult to reduce the bit line interval.
- the present invention suppresses leakage current between the bit line and the connection hole that occurs when the overlapping of the bit line and the connection hole is shifted in the vertical direction from the bit line, and overlaps the bit line and the connection hole.
- Semiconductor device capable of reducing the margin of memory and miniaturizing memory cells and method of manufacturing the same The purpose is to provide the law.
- the present invention includes a semiconductor substrate, an ONO film formed on the semiconductor substrate, a bit line formed in the semiconductor substrate, and a connection part electrically connected to the bit line.
- the semiconductor substrate has a trench isolation region provided on both sides of the bit line so as to sandwich the connection portion. According to the present invention, even when the overlap between the bit line and the connection portion is shifted in the vertical direction from the bit line, the connection portion is formed on the trench isolation region. And semiconductor substrate force S will not leak. As a result, it is possible to provide a semiconductor device capable of reducing the overlap margin between the bit line and the connection portion and miniaturizing the memory cell.
- the present invention is a semiconductor device in which the trench isolation region is formed between word lines. According to the present invention, by forming the trench isolation region between the word lines, the leakage current between the bit line and the semiconductor substrate can be reduced.
- the present invention is a semiconductor device comprising a side wall on a side portion of the word line having the connection portion. According to the present invention, even when the connecting portion is displaced in the direction parallel to the bit line, it is possible to prevent the connecting portion from contacting the word line. As a result, it is possible to provide a semiconductor device in which the margin of overlap between the word line and the connection portion can be reduced and the memory cell can be miniaturized.
- the present invention is a semiconductor device in which the side wall is a silicon nitride film.
- the side wall can have selectivity with the interlayer insulating film when the connection portion is dry-etched. As a result, even when the connecting portion is displaced in the direction parallel to the bit line, it is possible to more reliably prevent the connecting portion and the word line from contacting each other.
- the present invention is a semiconductor device in which the bit line and the trench isolation region are in contact with each other. According to the present invention, no gap is formed between the bit line and the trench isolation region, which also has a semiconductor substrate force. This can prevent leakage current from flowing between the bit line and the semiconductor substrate.
- the present invention includes a step of forming a trench isolation region in a semiconductor substrate, a step of forming a bit line in the semiconductor substrate, and a step of forming an ONO film on the semiconductor substrate. Forming a connection portion connected to the bit line, wherein the connection portion is formed so as to be sandwiched between the trench isolation regions provided on both sides of the bit line. is there. According to the present invention, even when the overlap between the bit line and the connection portion is shifted in the vertical direction from the bit line, the connection portion is formed on the trench isolation region. And semiconductor substrate force S does not leak. As a result, it is possible to provide a method for manufacturing a semiconductor device in which the margin for overlapping the bit line and the connection portion can be reduced and the memory cell can be miniaturized.
- the present invention includes a step of forming a word line on the ONO film after a step of forming an ONO film on the semiconductor substrate, and a side portion of the word line, the connection portion being provided. Forming a side wall on the side of the semiconductor device. According to the present invention, even if the connecting portion is displaced in the direction parallel to the bit line, the connecting portion and the word line do not come into contact with each other. As a result, it is possible to provide a method for manufacturing a semiconductor device in which the margin for overlapping the word line and the connection portion can be reduced and the memory cell can be miniaturized.
- the present invention is a method for manufacturing a semiconductor device, wherein the step of forming the side wall is a step of forming simultaneously with the side wall formed on the gate side portion of the peripheral circuit. According to the present invention, since the side wall is formed simultaneously with the side wall formed on the gate side portion of the peripheral circuit, the manufacturing process can be simplified.
- the step of forming a bit line in the semiconductor substrate is a step of forming impurities by implanting the bit line and a region adjacent to the bit line in the trench isolation region.
- a method for manufacturing a semiconductor device even when the overlap between the bit line and the trench isolation region is shifted in the vertical direction from the bit line, the gap between the bit line and the trench isolation region is not formed. This can prevent leakage current from flowing between the bit line and the semiconductor substrate.
- the bit line and the connection portion since the overlapping force between the bit line and the connection portion is shifted in the vertical direction from the bit line, the connection portion is in contact with the trench isolation region. The semiconductor substrate will not be clogged. As a result, the bit line and the connection It is possible to provide a semiconductor device capable of reducing the overlap margin and miniaturizing a memory cell and a manufacturing method thereof.
- FIG. 1 is a top view (Part 1) of the prior art.
- FIG. 2 is a top view (part 2) of the prior art.
- FIG. 3 is a cross-sectional view (part 1) of the prior art.
- FIG. 4 is a cross-sectional view (part 2) of the prior art.
- FIG. 5 is a cross-sectional view for explaining the problems of the prior art.
- FIG. 6 is a top view (part 1) showing the manufacturing process of the first embodiment.
- FIG. 7 is a sectional view (No. 1) showing the manufacturing process of the first embodiment.
- FIG. 8 is a sectional view (No. 2) showing the manufacturing process of the first embodiment.
- FIG. 9 is a sectional view (No. 3) showing the manufacturing process of the first embodiment.
- FIG. 10 is a sectional view (No. 4) showing the manufacturing process of the first embodiment.
- FIG. 11 is a sectional view (No. 5) showing the manufacturing process of Example 1.
- FIG. 12 is a top view (part 2) showing the manufacturing process of the first embodiment.
- FIG. 13 is a sectional view (No. 6) showing the manufacturing process of the first embodiment.
- FIG. 14 is a sectional view (No. 7) showing the manufacturing process of the first embodiment.
- FIG. 15 is a cross-sectional view for explaining the effect of the first embodiment.
- FIG. 16 is a top view showing the manufacturing process of Example 2.
- FIG. 17 is a sectional view (No. 1) showing the manufacturing process of the second embodiment.
- FIG. 18 is a sectional view (No. 2) showing the manufacturing process of the second embodiment.
- FIG. 19 is a sectional view (No. 3) showing the manufacturing process of the second embodiment.
- FIG. 20 is a sectional view (No. 4) showing the manufacturing process of the second embodiment.
- FIG. 21 is a sectional view (No. 5) showing the manufacturing process of the second embodiment.
- FIG. 22 is a sectional view (No. 6) showing the manufacturing process of the second embodiment.
- FIG. 23 is a sectional view (No. 7) showing the manufacturing process of the second embodiment.
- FIG. 24 is a sectional view (No. 8) showing the manufacturing process of the second embodiment.
- FIG. 25 is a cross-sectional view for explaining the effect of Example 2.
- FIG. 26 is a layout diagram of Example 1.
- FIG. 27 is a cross-sectional view showing an ion implantation step in Example 1.
- FIG. 28 is a cross-sectional view showing an ion implantation step when bit line overlay is shifted in Example 1.
- FIG. 29 is a cross-sectional view showing a case where bit line overlay is shifted in the first embodiment.
- FIG. 30 is a layout diagram of Example 3.
- FIG. 31 is a cross-sectional view showing the production process of Example 3.
- FIG. 32 is a layout diagram of a modification of the third embodiment.
- a semiconductor device and a manufacturing method thereof according to the first embodiment will be described with reference to FIGS. 6 to 14.
- a trench isolation region 50 is formed in a predetermined region of the P-type silicon semiconductor substrate 10 (or a P-type semiconductor region formed in the semiconductor substrate) using an STI (Shallow Trench Isolation) method.
- the trench isolation region is a region in which a groove (trench) portion is formed in the semiconductor substrate 10 and an oxide film such as an oxide silicon film is formed and buried in the groove portion.
- the trench isolation region 50 is formed by the following method, for example.
- the semiconductor substrate 10 in a predetermined region is etched by a dry etching method to form a groove.
- a silicon oxide film is formed on the entire surface by a thermal oxidation method or a CVD method. Flatten by CMP (Chemical Mechanical Polish) method or selective etching. As a result, the silicon oxide film is buried in the groove, and a trench isolation region is formed.
- CMP Chemical Mechanical Polish
- FIG. 6 is a top view of the memory cell after the trench isolation region 50 is formed.
- 7 is a cross-sectional view of A
- FIG. 8 is a cross-sectional view of B.
- a trench isolation region 50 is formed between the bit lines in the bit line connection region 42 where the connection hole is formed.
- an ONO film 16 is formed on the semiconductor substrate 10 as an oxide silicon film as a tunnel oxide film, a silicon nitride film as a trap layer, and an acid as a top oxide film layer.
- a silicon film is formed by thermal oxidation or CVD.
- a word line 20 (not shown) to be the gate of the core cell is formed by forming, for example, a polycrystalline silicon film and etching a predetermined region.
- the polycrystalline silicon film can be a laminated structure of silicide.
- An oxide silicon film such as BPSG (Boron-Phosphorus Silicated Glass) is formed as an interlayer insulating film 30 on the transistor using a CVD method.
- a connection hole 40 (a connection portion electrically connected to the bit line 14) connected to the bit line 14 is formed in the bit line connection region 42 of the interlayer insulating film 30.
- the wiring 34 is formed using, for example, an aluminum alloy so as to fill the connection hole 40.
- the protective film 32 is formed of, for example, an oxide silicon film to complete the memory cell.
- FIG. 12 is a top view (the protective film 32, the wiring 34, the interlayer insulating film 30, and the ONO film 16 are not shown).
- the cross-sectional view of A—A ′ is shown in FIG. 13, and the cross-sectional view of B—B ′ is shown.
- FIG. 12 the trench isolation regions 50 are provided on both sides of the bit line 14 and are formed so as to sandwich the connection holes 40 between the both sides.
- the trench isolation region 50 is formed between adjacent word lines 20.
- the plurality of trench isolation regions 50 are arranged linearly along the word line 20.
- a trench isolation region 50 is formed between the word lines 20 in which the connection holes 40 are not formed.
- FIG. 15 is a cross-sectional view taken along the line AA ′ in the first embodiment when the connection hole 40 is formed by shifting the force of the bit line 14 in the left direction. Even in the region 55 where the connection hole 40 is formed outside the bit line 14, the connection hole 40 is formed on the trench isolation region 50. For this reason, there is no leakage current between the semiconductor substrate 10 and the connection hole 40 that is not electrically connected. Therefore, the overlap margin at the time of exposure of the bit line 14 and the connection hole 40 can be reduced, and the memory cell can be miniaturized.
- FIG. 16 is a top view when the second embodiment is completed (the protective film 32, the interlayer insulating film 30, the wiring 34, and the ONO film 16 are not shown).
- 17 to 23 are cross-sectional views of the BB ′ cross section showing the manufacturing process of the second embodiment.
- the right side is a memory cell region, and the left side is a view of the vicinity of the gate in the peripheral circuit region.
- FIG. 17 is obtained by the same manufacturing process as in FIGS. 7 to 10 of the first embodiment.
- an ONO film 16 is formed on the semiconductor substrate 10 having the bit lines 14.
- an ONO film 16 is formed on the semiconductor substrate 10.
- the ONO film in the peripheral circuit region is selectively removed, and an oxide silicon film is formed as the gate oxide film 60.
- the word line 20 that becomes the gate of the core cell is formed using, for example, polycrystalline silicon, and in the peripheral circuit region, the gate 64 4 force, for example, using polycrystalline silicon. It is formed. At this time, the word line 20 and the gate 64 are formed simultaneously, thereby simplifying the manufacturing process.
- shallow V, N-type regions 66 are formed on both sides of the gate 64 in the peripheral circuit region, for example, by relatively small doping amount by phosphorus ion implantation.
- a silicon nitride film 22 is formed using a CVD method.
- the bit line connection region 42 in the peripheral circuit region and the memory cell region is selectively anisotropically etched.
- LDD Lightly Doped Drain
- side walls 62 are formed on both sides of the gate 64, and side walls 22 are formed on the bit line connection region 42 side of the word lines 20.
- deep N-type regions 68 having a relatively large doping amount are formed on both sides of the LDD sidewall 62 by, for example, arsenic ion implantation.
- an LDD structure is formed in the peripheral circuit region.
- FIG. 23 is a cross section taken along the line AA ′ in FIG.
- FIG. 25 is a cross-sectional view taken along the line BB ′ when the connection hole 40 is displaced in the direction parallel to the bit line.
- the word line 40 can be protected from the dry etching when the connection hole 40 is formed. As a result, it is possible to reduce the overlap margin at the time of exposure of the word line 20 and the connection hole 40 and realize a miniaturized memory cell. Further, since the side wall 22 is formed at the same time as the LDD side wall 62, the manufacturing process can be simplified.
- Example 3 is an example relating to a region where bit lines are implanted. First, the problem in the first embodiment will be described.
- FIG. 26 shows the layout of the trench isolation region 50 in the memory cell according to the first embodiment and the layout of the region 52 for ion implantation for forming the bit line 14! /
- FIG. 27 is a cross-sectional view of the bit line 14 during the ion implantation process. Corresponds to A— ⁇ in Fig. 26.
- the photoresist 36 is provided with an opening of a region 52 where ion implantation is performed.
- Reference numeral 54 schematically illustrates ion implantation.
- arsenic is used for ion implantation.
- Ions for forming the bit line 14 are implanted under the opening of the region 52 where ion implantation is performed. Thereafter, the N-type bit line 14 is formed by heat treatment.
- FIG. 28 shows a cross-sectional view at the time of the ion implantation process in the case where there is a deviation in the vertical direction with respect to the bit line in the exposure force of the trench isolation region 50 region and the region 52 where ion implantation is performed. .
- the region 52 where ion implantation is performed is formed so as to be shifted to the right with respect to the trench isolation region 50 region.
- a gap 56 is formed between the trench isolation region 50 and the bit line 14.
- FIG. 29 is a view when the connection hole 40 is formed in this state.
- the connection hole 40 is in contact with the gap 56. For this reason, electrical bonding occurs between the semiconductor substrate 10 and the connection hole 40 which are the gaps 56, and a leak current flows between the bit line 14 and the semiconductor substrate 10 through the connection hole 40. There is a problem with Example 1.
- FIG. 30 shows a layout of the region of the trench isolation region 50 in the memory cell according to the third embodiment and the region 52 for performing ion implantation for forming the bit line 14! /.
- the ion-implanted region 52 extends continuously in the bit line connection region 42 in the direction perpendicular to the bit line.
- FIG. 31 is a cross-sectional view of the ion implantation process for forming the bit line 14.
- a in Figure 30 is a cross-sectional view of the ion implantation process for forming the bit line 14.
- a region 52 for ion implantation is formed continuously.
- Reference numeral 54 schematically illustrates ion implantation.
- arsenic is used for ion implantation.
- ions are also implanted into the trench isolation region 50.
- the ions injected into the trench isolation region 50 remain in the oxide silicon film embedded in the trench isolation region 50 and do not affect the insulation characteristics of the trench isolation region 50.
- an N-type bit line 14 is formed by heat treatment.
- a region 52 where ion implantation for forming the bit line 14 is performed is continuous in the bit line connection region 42 in the direction perpendicular to the bit line. It does not have to be extended. If it overlaps with the trench isolation region 50, the function is fulfilled, and the overlap distance L1 is preferably larger than the overlap margin during exposure of the bit line 14 and the trench isolation region 52.
- the overlapping force between the bit line 14 and the trench isolation region 50 can be obtained even when the bit line 14 and the trench isolation region 50 are displaced in the vertical direction with respect to the bit line.
- the gap 56 is not formed. As a result, no leak current flows between the bit line 14 and the semiconductor substrate 10.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2005/003213 WO2006090477A1 (ja) | 2005-02-25 | 2005-02-25 | 半導体装置及びその製造方法 |
JP2007504608A JP4944766B2 (ja) | 2005-02-25 | 2005-02-25 | 半導体装置及びその製造方法 |
US11/361,630 US7968404B2 (en) | 2005-02-25 | 2006-02-24 | Semiconductor device and fabrication method therefor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2005/003213 WO2006090477A1 (ja) | 2005-02-25 | 2005-02-25 | 半導体装置及びその製造方法 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/361,630 Continuation US7968404B2 (en) | 2005-02-25 | 2006-02-24 | Semiconductor device and fabrication method therefor |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2006090477A1 true WO2006090477A1 (ja) | 2006-08-31 |
Family
ID=36927128
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2005/003213 WO2006090477A1 (ja) | 2005-02-25 | 2005-02-25 | 半導体装置及びその製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7968404B2 (ja) |
JP (1) | JP4944766B2 (ja) |
WO (1) | WO2006090477A1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007103920A (ja) * | 2005-09-30 | 2007-04-19 | Qimonda Ag | 半導体メモリデバイスおよび製造方法 |
US8100527B2 (en) | 2007-01-12 | 2012-01-24 | Novartis Ag | Intermediate vision with phakic multifocal optics utilizing residual accommodations |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11080454B2 (en) * | 2019-08-30 | 2021-08-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit, system, and method of forming the same |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11186528A (ja) * | 1997-12-25 | 1999-07-09 | Sony Corp | 不揮発性半導体記憶装置及びその製造方法 |
JP2003224213A (ja) * | 2002-01-30 | 2003-08-08 | Mitsubishi Electric Corp | 不揮発性半導体記憶装置 |
JP2004039866A (ja) * | 2002-07-03 | 2004-02-05 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2004111737A (ja) * | 2002-09-19 | 2004-04-08 | Fasl Japan Ltd | 半導体装置の製造方法 |
JP2004193178A (ja) * | 2002-12-06 | 2004-07-08 | Fasl Japan 株式会社 | 半導体記憶装置及びその製造方法 |
JP2004349312A (ja) * | 2003-05-20 | 2004-12-09 | Sharp Corp | 半導体記憶装置 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6232181B1 (en) | 1999-10-21 | 2001-05-15 | United Microelectronics Corp. | Method of forming a flash memory |
US6271088B1 (en) | 2001-01-05 | 2001-08-07 | United Microelectronics Corp. | Method for fabricating a buried vertical split gate memory device with high coupling ratio |
US6562675B1 (en) * | 2001-08-17 | 2003-05-13 | Cypress Semiconductor Corp. | Adjustment of threshold voltages of selected NMOS and PMOS transistors using fewer masking steps |
JP2003174106A (ja) * | 2001-12-07 | 2003-06-20 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US6828623B1 (en) | 2002-08-30 | 2004-12-07 | Advanced Micro Devices, Inc. | Floating gate memory device with homogeneous oxynitride tunneling dielectric |
DE10246343B4 (de) | 2002-10-04 | 2007-02-08 | Infineon Technologies Ag | Verfahren zur Herstellung eines Halbleiterspeicherzellenfeldes |
US20040079984A1 (en) * | 2002-10-25 | 2004-04-29 | Hsuan-Ling Kao | Polysilicon self-aligned contact and a polysilicon common source line and method of forming the same |
US6847087B2 (en) | 2002-10-31 | 2005-01-25 | Ememory Technology Inc. | Bi-directional Fowler-Nordheim tunneling flash memory |
TW591761B (en) | 2003-07-11 | 2004-06-11 | Macronix Int Co Ltd | NAND type binary nitride read only memory and the manufacturing method |
KR100511045B1 (ko) * | 2003-07-14 | 2005-08-30 | 삼성전자주식회사 | 리세스된 게이트 전극을 갖는 반도체 소자의 집적방법 |
US7423312B1 (en) * | 2004-07-20 | 2008-09-09 | Spansion Llc | Apparatus and method for a memory array with shallow trench isolation regions between bit lines for increased process margins |
KR100630725B1 (ko) | 2004-12-17 | 2006-10-02 | 삼성전자주식회사 | 매립된 비트라인을 가진 반도체 소자 및 그 제조방법 |
-
2005
- 2005-02-25 WO PCT/JP2005/003213 patent/WO2006090477A1/ja not_active Application Discontinuation
- 2005-02-25 JP JP2007504608A patent/JP4944766B2/ja not_active Expired - Fee Related
-
2006
- 2006-02-24 US US11/361,630 patent/US7968404B2/en not_active Expired - Fee Related
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11186528A (ja) * | 1997-12-25 | 1999-07-09 | Sony Corp | 不揮発性半導体記憶装置及びその製造方法 |
JP2003224213A (ja) * | 2002-01-30 | 2003-08-08 | Mitsubishi Electric Corp | 不揮発性半導体記憶装置 |
JP2004039866A (ja) * | 2002-07-03 | 2004-02-05 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2004111737A (ja) * | 2002-09-19 | 2004-04-08 | Fasl Japan Ltd | 半導体装置の製造方法 |
JP2004193178A (ja) * | 2002-12-06 | 2004-07-08 | Fasl Japan 株式会社 | 半導体記憶装置及びその製造方法 |
JP2004349312A (ja) * | 2003-05-20 | 2004-12-09 | Sharp Corp | 半導体記憶装置 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007103920A (ja) * | 2005-09-30 | 2007-04-19 | Qimonda Ag | 半導体メモリデバイスおよび製造方法 |
US8100527B2 (en) | 2007-01-12 | 2012-01-24 | Novartis Ag | Intermediate vision with phakic multifocal optics utilizing residual accommodations |
Also Published As
Publication number | Publication date |
---|---|
JPWO2006090477A1 (ja) | 2008-07-24 |
JP4944766B2 (ja) | 2012-06-06 |
US7968404B2 (en) | 2011-06-28 |
US20060263989A1 (en) | 2006-11-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4325972B2 (ja) | 不揮発性半導体記憶装置を含む半導体集積回路装置の製造方法 | |
KR20030055166A (ko) | 반도체 장치 및 그 제조 방법 | |
JP2006286720A (ja) | 半導体装置およびその製造方法 | |
KR101037036B1 (ko) | 불휘발성 반도체 메모리 및 그 제조 방법 | |
KR101022666B1 (ko) | 메모리 소자 및 그 제조 방법 | |
JP4822792B2 (ja) | 半導体装置およびその製造方法 | |
US9171962B2 (en) | Semiconductor device and method of manufacturing the same | |
JP3849759B2 (ja) | 半導体装置 | |
US7091090B2 (en) | Nonvolatile memory device and method of forming same | |
JP4944766B2 (ja) | 半導体装置及びその製造方法 | |
US8207560B2 (en) | Nonvolatile semiconductor memory device and method of fabricating the same | |
EP1898460B1 (en) | Semiconductor device and fabrication method thereof | |
TWI740995B (zh) | 半導體裝置之製造方法 | |
JP2004047802A (ja) | 半導体装置の製造方法 | |
JP2013004791A (ja) | 半導体装置およびその製造方法 | |
US20050032310A1 (en) | Semiconductor memory device and manufacturing method thereof | |
JP2011119508A (ja) | 半導体装置の製造方法 | |
JP2004006449A (ja) | 半導体集積回路装置 | |
JP3675381B2 (ja) | 半導体装置の製造方法 | |
JP3653540B2 (ja) | 半導体装置の製造方法 | |
JP5657612B2 (ja) | 半導体装置およびその製造方法 | |
WO2006106570A1 (ja) | 半導体装置 | |
JP2009004802A (ja) | 半導体記憶装置及びその製造方法 | |
US20100155809A1 (en) | Semiconductor device of common source structure and manufacturing method of semiconductor device of common source structure | |
JP2006173469A (ja) | 半導体装置およびその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 11361630 Country of ref document: US |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWP | Wipo information: published in national office |
Ref document number: 11361630 Country of ref document: US |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2007504608 Country of ref document: JP |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 05719564 Country of ref document: EP Kind code of ref document: A1 |
|
WWW | Wipo information: withdrawn in national office |
Ref document number: 5719564 Country of ref document: EP |