KR950028585A - Ic 장착 보드에 땜납 범프를 형성하는 방법 - Google Patents

Ic 장착 보드에 땜납 범프를 형성하는 방법 Download PDF

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KR950028585A
KR950028585A KR1019950007230A KR19950007230A KR950028585A KR 950028585 A KR950028585 A KR 950028585A KR 1019950007230 A KR1019950007230 A KR 1019950007230A KR 19950007230 A KR19950007230 A KR 19950007230A KR 950028585 A KR950028585 A KR 950028585A
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solder
openings
solder resist
forming
bumps
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KR1019950007230A
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도로 후와
미쯔오 나까하시
히로끼 고조
가즈마사 네모또
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모리따 겐조
엔지케이 인슐레이터즈 가부시끼가이샤
원본미기재
듀폰 가부시끼가이샤
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Publication of KR950028585A publication Critical patent/KR950028585A/ko

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Abstract

본 발명의 목적은 소형화되더라도 충분한 양의 땜납으로 된 땜납 범프가 형성될 수 있는 땜납 범프를 형성하는 방법을 제공하기 위한 것이다.
전도체 배선이 형성되어 있는 IC 칩을 장착하기 위한 보드(1) 상에 땜납 범프를 형성하는 본 발명에 따른 방법은 전도체 배선(2)가 형성되어 있는 보드의 표면 상에 감광성 제1땜납 레지스트(3)를 형성하는 단계, 땜납 범프가 형성될 제1땜납 레지스트(3)의 사이트들에 포토에칭하여 제1개구들(3a)를 형성하는 단계, 제1땜납 레지스트상에 제2땜납 레지스트(4)를 형성하는 단계, 제1개구들에 대응하는 제2땜납 레지스트의 사이트들에 포토에칭하여 제1개구들과 접속되는 제2개구들(4a)를 형성하는 단계, 제1 및 제2개구들은 땜납(5)로 충진하는 단계, 리플로우 처리를 실행하는 단계, 및 제1땜납 레지스트의 적어도 일부가 잔존하도록 에칭하는 단계를 포함한다.

Description

IC장착 보드에 땜납 범프를 형성하는 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 땜납 범프를 형성하는 방법의 프로세스를 설명하는 단면도,
제2도는 본 발명의 땜납 범프를 형성하는 방법의 프로세스를 설명하는 단면도,
제3도는 본 발명의 땜납 범프를 형성하는 방법의 프로세스를 설명하는 단면도,
제4도는 본 발명의 땜납 범프를 형성하는 방법의 프로세스를 설명하는 단면도,
제8도는 본 발명의 땜납 범프를 형성하는 방법의 프로세스를 설명하는 단면도.

Claims (8)

  1. 전도체 배선이 형성되어 있는 IC 칩을 장착하기 위한 보드 상에 땜납 범프를 형성하는 방법에 있어서, 전도체 배선이 형성되어 있는 보드의 표면 상에 감광성 제1땜납 레지스트를 형성하는 단계, 땜납 범프가 배치될 제1땜납 레지스트의 사이트들에 포토에칭하여 제1개구들을 형성하는 단계, 제1땜납 레지스트상에 제2땜납 레지스트를 형성하는 단계, 제1개구들에 대응하는 제2땜납 레지스트의 사이트들에 포토에칭하여 제1개구들과 접속하는 제2개구들을 형성하는 단계, 제1 및 제2개구들을 땜납으로 충진하는 단계, 리플로우 처리를 실행하는 단계, 및 제1땜납 레지스트의 적어도 일부가 잔존하도록 에칭하는 단계를 포함하는 것을 특징으로 하는 보드 상에 땜납 범프를 형성하는 방법.
  2. 전도체 배선이 형성되어 있는 IC칩 장착 보드 상에 땜납 범프를 형성하는 방법에 있어서, 도선들 사이의 공간들이 채워지도록 전도체 배선이 형성되어 있는 보드의 표면 상에 액체의 제1땜납 레지스트를 코팅하는 단계, 제1땜납 레지스트 상에 제2땜납 레지스트를 형성하는 단계, 땜납 범프들이 형성될 제1 및 제2땜납 레지스트들의 사이트들에 포토에칭하여 개구들을 형성하는 단계, 상기 개구들을 땜납으로 충진하는 단계, 리플로우 처리를 실행하는 단계, 및 제1땜납 레지스트의 적어도 일부가 잔존하도록 에칭하는 단계를 포함하는 것을 특징으로 하는 IC칩 장착 보드 상에 땜납 범프를 형성하는 방법.
  3. 제1항 또는 제2항에 있어서, 제2땜납 레지스트를 막형 감광성 땜납 레지스트로 구성하는 것을 특징으로 하는 IC칩 장착 보드 상에 땜납 범프를 형성하는 방법.
  4. 제1항 또는 제3항에 있어서, S1이 제1개구들의 개구 면적이고, S2가 제2개구들의 개구 면적일 때, S2/S1≥1인 것을 특징으로 하는 IC칩 장착 보드 상에 땜납 범프를 형성하는 방법.
  5. 제1항 내지 제4항 중 어느 한 항에 있어서, 제1땜납 레지스트를 특정 에천트에 관하여 제2땜납 레지스트의 재료보다 에칭 속도가 느린 재료로 만드는 것을 특징으로 하는 IC칩 장착 보드 상에 땜납 범프를 형성하는 방법.
  6. 전도체 배선이 형성되어 있는 IC칩 장착 보드 상에 땜납 범프를 형성하는 방법에 있어서, 도선들 사이의 공간들이 채워지도록 전도체 배선이 형성되어 있는 보드의 표면 상에 액체의 제1땜납 레지스트를 코팅하는 단계, 제1땜납 레지스트 상에 감광성 제2땜납 레지스트를 형성하는 단계, 땜납 범프가 형성될 제2땜납 레지스트의 사이트들에 제1개구들을 형성하는 단계, 제2땜납 레지스트 상에 제3땜납 레지스트를 형성하는 단계, 제1개구들에 대응하는 제3땜납 레지스트의 사이트들에 포토에칭하여 제1개구들과 접속하는 제2개구들을 형성하는 단계, 제1 및 제2개구들을 땜납으로 충진하는 단계, 리플로우 처리를 실행하는 단계, 및 제3땜납 레지스트를 제거하는 단계를 포함하는 것을 특징으로 하는 IC칩 장착 보드 상에 땜납 범프를 형성하는 방법.
  7. 제6항에 있어서, S1이 제1개구들의 개구 면적이고, S2가 제2개구들의 개구 면적일 때, S2/S1≥1이 성립되는 것을 특징으로 하는 IC칩 장착 보드 상에 땜납 범프를 형성하는 방법.
  8. 제7항에 있어서, 상기 개구들이 지그재그 패턴으로 형성되는 것을 특징으로 하는 IC칩 장착 보드 상에 땜납 범프를 형성하는 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950007230A 1994-03-31 1995-03-31 Ic 장착 보드에 땜납 범프를 형성하는 방법 KR950028585A (ko)

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Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5750868A (en) * 1994-12-08 1998-05-12 Pioneer Hi-Bred International, Inc. Reversible nuclear genetic system for male sterility in transgenic plants
USRE43509E1 (en) * 1996-12-19 2012-07-17 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
EP0849983B1 (en) * 1996-12-20 2001-10-24 Alcatel Process to create metallic stand-offs on a circuit board
JP3500032B2 (ja) * 1997-03-13 2004-02-23 日本特殊陶業株式会社 配線基板及びその製造方法
US6461953B1 (en) 1998-08-10 2002-10-08 Fujitsu Limited Solder bump forming method, electronic component mounting method, and electronic component mounting structure
JP3423930B2 (ja) * 1999-12-27 2003-07-07 富士通株式会社 バンプ形成方法、電子部品、および半田ペースト
JP4748889B2 (ja) * 2000-12-26 2011-08-17 イビデン株式会社 多層プリント配線板の製造方法
JP4707273B2 (ja) * 2000-12-26 2011-06-22 イビデン株式会社 多層プリント配線板の製造方法
JP4212992B2 (ja) * 2003-09-03 2009-01-21 Ｔｄｋ株式会社 半田ボールの供給方法および供給装置
JP2006135156A (ja) * 2004-11-08 2006-05-25 Compeq Manufacturing Co Ltd 回路基板上へのはんだバンプの形成方法
TWI253888B (en) 2004-12-09 2006-04-21 Advanced Semiconductor Eng Method of packaging flip chip and method of forming pre-solders on substrate thereof
JP4669703B2 (ja) * 2005-01-19 2011-04-13 イビデン株式会社 プリント配線板及びその製法
US7517788B2 (en) * 2005-12-29 2009-04-14 Intel Corporation System, apparatus, and method for advanced solder bumping
GB0807485D0 (en) * 2008-04-24 2008-06-04 Welding Inst Method of applying a bump to a substrate
JP2010245317A (ja) * 2009-04-07 2010-10-28 Ricoh Microelectronics Co Ltd 電子部品実装方法
WO2011038090A1 (en) * 2009-09-23 2011-03-31 3M Innovative Properties Company Electrical connection and method for making the same
JP5585354B2 (ja) * 2010-09-29 2014-09-10 凸版印刷株式会社 半導体パッケージの製造方法
CN102458039A (zh) * 2010-10-18 2012-05-16 上海嘉捷通电路科技有限公司 一种厚铜线路板
CN110676175A (zh) * 2019-09-24 2020-01-10 浙江集迈科微电子有限公司 一种键合工艺制作大锡球的方法
CN113923885B (zh) * 2021-09-18 2023-05-05 厦门大学 用于焊接微小芯片的柔性线路板的制作方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57152146A (en) * 1981-03-13 1982-09-20 Citizen Watch Co Ltd Manufacture of semiconductor device
JPH0252436A (ja) * 1988-08-17 1990-02-22 Shimadzu Corp ハンダバンプ製造方法
US5316788A (en) * 1991-07-26 1994-05-31 International Business Machines Corporation Applying solder to high density substrates

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