KR920702797A - 강 유전체를 구비한 반도체 장치 및 그 제조 방법 - Google Patents

강 유전체를 구비한 반도체 장치 및 그 제조 방법

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Publication number
KR920702797A
KR920702797A KR1019910701909A KR910701909A KR920702797A KR 920702797 A KR920702797 A KR 920702797A KR 1019910701909 A KR1019910701909 A KR 1019910701909A KR 910701909 A KR910701909 A KR 910701909A KR 920702797 A KR920702797 A KR 920702797A
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film
semiconductor device
electrode
steel dielectric
semiconductor substrate
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KR1019910701909A
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KR100349999B1 (ko
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가즈히로 다께나까
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아아자와 스스무
세이꼬 엡슨 가부시끼가이샤
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Publication of KR920702797A publication Critical patent/KR920702797A/ko
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/792Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes
    • H01L29/456Ohmic electrodes on silicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/516Insulating materials associated therewith with at least one ferroelectric layer
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B53/00Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음

Description

강 유전체를 구비한 반도체 장치 및 그 제조방법.
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 이 발명의 실시예1에 관계하는 강 유전체 캐패시터를 구비한 반도체 장치를 도시하는 주요 단면도.
제2도는 이 발명의 실시예2에 관계하는 강 유전체 캐패시터를 구비한 반도체 장치를 도시하는 주요 단면도.
제3A도, 제3B도, 제3C도는 실시예2의 주요 제조 프로세스를 각각 설명하기 위한 단면도.

Claims (9)

  1. 산소 결합성에 있는 반도체 기체의 주평면상 또는 내부에 있어서 전극을 거쳐서 형성된 강 유전체막을 소자 요소로 하는 반도체 장치이며, 그 반도체 기체와 그 전극 사이에는 도전성 산화막이 형성되어 이루는 것을 특징으로 하는 강 유전체를 구비한 반도체 장치.
  2. 제1항에 있어서, 상기 도전성 산화막은 Ru산화막, Re산화막, Mo산화막, ITo(인듐, 주석, 옥사이드)막 중의 어느 하나 또는 그것들 금속의 혼합막인 것을 특징으로 하는 강 유전체를 구비하는 반도체 장치.
  3. 산소 결합성이 있는 반도체 기체의 주평면상 또는 내부에 있어서 전극을 거쳐서 형성된 강 유전체막을 소자 요소로 하는 반도체 장치이며, 그 반도체 기체와 그 전극 사이에는 도전 금속막이 형성되어 이루는 것을 특징으로 하는 강 유전체를 구비한 반도체 장치.
  4. 제3항에 있어서, 상기 도전 금속막은 상기 도전성 산화막을 생성 가능한 금속막인 것을 특징으로 하는 강 유전체막을 갖는 반도체 장치.
  5. 제4항에 있어서, 상기 도전 금속막은 Ru막, Re막, Mo막 중의 어느 하나 또는 그것들 금속의 혼합막인것을 특징으로 하는 강 유전체를 구비한 반도체 장치.
  6. 제1항 내지 5항 중 어느 한 항에 있어서, 상기 반도체 기체의 계면에는 금속 실리사이드 막이 형성되어 이루는 것을 특징으로 하는 강 유전체를 구비한 반도체 장치.
  7. 제6항에 있어서, 상기 금속 실리사이드막은 Ti, Rt, Ru, Re, Mo, W, Ta중의 어느 한 금속을 주성분으로 한 실리사이드 막인 것을 특징으로 하는 강 유전체를 구비한 반도체 장치.
  8. 산소 결합성이 있는 반도체 기체의 주평면상 또는 내부에 있어서 전극을 거쳐서 형성된 강 유전체막을 소자 요소로 하는 반도체 장치의 제조 방법에 있어서, 그 반도체 기체의 주평면 또는 내부면에 도전성 산화물을 생성가능한 도전 금속막을 퇴전하고 그 도전성 금속층의 위에 상기 전극 및 상기 유전체막을 순차 적층한 후, 산소를 포함하는 분위기 중에서 열처리를 실시하는 것을 특징으로 하는 강 유전체를 구비한 반도체 장치의 제조방법.
  9. 제8항에 있어서, 상기 도전 금속막은 Ru, Re, Mo중의 어느 한 금속 또는 그것들의 혼합물로 이루는 것을 특징으로 하는 강 유전체를 구비한 반도체 장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910701909A 1990-04-24 1991-04-23 강유전체를구비한반도체장치및그제조방법 KR100349999B1 (ko)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
JP90-108012 1990-04-24
JP90-108013 1990-04-24
JP90-108011 1990-04-24
JP10801190 1990-04-24
JP10801390 1990-04-24
JP10801290 1990-04-24
PCT/JP1991/000539 WO1991016731A1 (en) 1990-04-24 1991-04-23 Semiconductor device having ferroelectric material and method of producing the same

Publications (2)

Publication Number Publication Date
KR920702797A true KR920702797A (ko) 1992-10-06
KR100349999B1 KR100349999B1 (ko) 2002-12-11

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Country Status (5)

Country Link
US (1) US5293510A (ko)
EP (1) EP0478799B1 (ko)
KR (1) KR100349999B1 (ko)
DE (1) DE69123422T2 (ko)
WO (1) WO1991016731A1 (ko)

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Publication number Publication date
EP0478799A1 (en) 1992-04-08
WO1991016731A1 (en) 1991-10-31
KR100349999B1 (ko) 2002-12-11
DE69123422T2 (de) 1997-06-05
EP0478799A4 (en) 1992-10-21
US5293510A (en) 1994-03-08
DE69123422D1 (de) 1997-01-16
EP0478799B1 (en) 1996-12-04

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