WO1996015556A1

WO1996015556A1 - Integrated circuit capacitors utilizing low curie point ferroelectrics

Info

Publication number: WO1996015556A1
Application number: PCT/US1995/014875
Authority: WO
Inventors: Tate Evans Joseph, Jr.
Original assignee: Radiant Technologies, Inc.
Priority date: 1994-11-15
Filing date: 1995-11-15
Publication date: 1996-05-23
Also published as: AU4365096A

Abstract

The invention is applicable to integrated circuit having ferroelectric layers that are switched between two states during the operation of the integrated circuit. In the present invention (10), a capacitor (19) has a ferroelectric layer (22) constructed from a material having a Curie point below 400 °C. In the typical integrated circuit fabrication process, the final step in the process before packaging involves annealing the circuit at a temperature above the Curie point of the ferroelectric layer used in an integrated circuit according to the present invention. Hence, any accumulated asymmetric charge distribution in the ferroelectric layer resulting from the processing of the integrated circuit after the deposition of the ferroelectric layer is eliminated. If the normal fabrication process does not involve a final annealing step at a temperature above the Curie point of the ferroelectric layer, a final annealing step in which the ferroelectric is annealed at a temperature above its Curie point is used.

Description

INTEGRATED CIRCUIT CAPACITORS UTILIZING LOW CIIRTF

POINT FERRQELECTRICS

Field of the Invention

The present invention relates to integrated circuits, and more particularly, to integrated circuits including ferroelectric devices.

Background of the Invention

Circuits based on ferroelectric capacitors have been known for some time. A ferroelectric capacitor consists of a thin film of ferroelectric material sandwiched between two electrodes. These circuits store information in the polarization of a ferroelectric dielectric. In destructively readout circuits, the direction of polarization of the dielectric is detected by applying a polarization signal in a known direction and then detecting the amount of charge leaving the capacitor. In non-destructively readout systems, one of the electrodes is actually a semiconductor with two contacts thereon. The state of polarization of the dielectric determines the electric field in the semiconductor which, in turn, determines the resistance between the two contacts. The later circuit is analogous to a FET.

To construct useful memories from these devices, a large number of cells must be fabricated on an integrated circuit having addressing circuitry and sense amplifiers. Typically, the additional circuitry is fabricated using conventional CMOS fabrication techniques on a silicon wafer. The ferroelectric capacitors are then fabricated on top of the CMOS wafer and covered with a dielectric layer. Vias are opened in the dielectric layer to the various connection points and metallic conductors are deposited to provide the connections between the various memory cells. The entire circuit is then covered with a passivation layer such as silicon dioxide. The passivated wafer is then subjected to a forming gas anneal in which it is heated to 350 to 400°C in a hydrogen atmosphere. The individual dice are then cut and packaged.

While individual memory cells have been successfully demonstrated for some time, the production of practical working memories has been problematic at best. The operation of the basic memory cells depends on switching the domains in the ferroelectric. The difference in the two states used to store information depends on a reproducible polarization in the two states. The various processing stages to which the circuits are subjected after the fabrication of the capacitors result in charge carriers being trapped asymmetrically in the domains. The trapped carriers result in a permanent dipole that does not switch with the domains. Hence, the electric field is the sum of the permanent dipole field and the switchable field of the domains. The larger the permanent dipole, the poorer the performance of the memory cell.

Broadly, it is the object of the present invention to provide an improved ferroelectric capacitor structure.

It is a further object of the present invention to provide a ferroelectric capacitor structure and construction method that is more immune to post fabrication processing than prior art structures.

These and other objects of the present invention will become apparent to those skilled in the art from the following detailed description of the invention and the accompanying drawings.

Brief Description of the Drawings

Figure 1 is a cross-sectional view of an integrated circuit element having a CMOS transistor and a ferroelectric based capacitor.

Summary of the invention

The invention is applicable to integrated circuits having ferroelectric layers that are switched between two states during the operation of the integrated circuit. In the present invention, the ferroelectric layer is constructed from a material having a Curie point below 400 °C. In the typical integrated circuit fabrication process, the final step in the process before packaging involves annealing the circuit at a temperature above the Curie point of the ferroelectric layer used in an integrated circuit according to the present invention. Hence, any accumulated asymmetric charge distribution in the ferroelectric layer resulting from the processing of the integrated circuit after the deposition of the ferroelectric layer is eliminated. If the normal fabrication process does not involve a final annealing step at a temperature above the Curie point of the ferroelectric layer, a final annealing step in which the ferroelectric is annealed at a temperature above its Curie point is used.

Detailed Description of the Invention

The manner in which the present invention gains its advantages may be more easily understood with reference to a typical integrated circuit structure having a capacitor 19 connected to a CMOS transistor 11 as shown in Figure 1 at 10. Transistor 11 includes a drain 12, gate region comprising gate oxide 15 and gate electrode 16 and a source 14. The gate structures are isolated with the aid of a glass layer 17. After constructing transistor 11, capacitor 19 is constructed by depositing a first electrode 20 on a thermal oxide layer 18. A layer 22 of ceramic material such as PZT or PLZT is deposited over electrode 20 and then sintered to form a thin film dielectric. A top electrode is then deposited on layer 22. The top and bottom electrodes are typically constructed from platinum. Bottom electrode 20 is typically constructed by first depositing a glue material such as Titanium onto which the platinum is deposited. After capacitor 11 is completed, the structure is covered with an interlayer dielectric layer 30 and vias are opened in this layer to make connections to the various electrodes. For example, source 14 is connected to top electrode 22 by a metal layer 25. Connections to the other electrodes and the drain of transistor 11 have been omitted to simplify the drawings.

After the various connections are made, the structure is covered with a layer of dielectric such as silicon dioxide or silicon nitride to seal the circuit. The circuit is then typically annealed at a temperature of between 350 and 400 °C in an atmosphere of 5% hydrogen, 95% nitrogen.

The problems with prior art capacitor structures based on PZT ferroelectrics arise from oxygen vacancies that move at high temperatures under the influence of the electric field generated by the domains. Oxygen vacancies in the PZT lattice behave as positive charge carriers. At normal operating temperatures (i.e., 50°C to 150°C), the oxygen vacancies are frozen into the PZT lattice and cannot move. When the dielectric is sintered during the deposition process and then quickly cooled, the oxygen vacancies are uniformly distributed within each domain in the dielectric layer. As the temperature is increased during the various processing steps, oxygen vacancies enter the conduction band and move under the influence of the remnant polarization field generated by the domains. The number of mobile oxygen vacancies present at any temperature is a very sensitive function of the temperature. Hence, when the integrated circuit is heated during the post capacitor fabrication processing steps, the mobility of the oxygen vacancies increases dramatically and these oxygen vacancies move to the negatively charged end of the domains. When the temperature returns to normal, the oxygen vacancies are frozen into place and remain even if an electric field sufficient to switch the domains is applied. These positive carriers can be viewed as creating an electrostatically charged dipole that offsets the fields generated by the domains.

The oxygen vacancies can be returned to a uniform distribution by heating the ferroelectric layer above the Curie point of the ferroelectric material and then quickly cooling the ferroelectric layer. At temperatures above the Curie point, the domains disappear, and hence, there is no electric field to cause the oxygen vacancies to assume a non-random distribution. The electric field generated by the oxygen vacancies themselves forces the oxygen vacancies to disperse forming a random distribution. If the ferroelectric is rapidly cooled from a temperature above its Curie point to room temperature the oxygen vacancies will be frozen in their random distribution since the field of the domain will have had insufficient time to act on them.

In principle, the damage done by heating the capacitor during the processing steps following the sintering operation can be reversed by annealing the capacitors at a temperature above the ferroelectric's Curie point after all of the processing steps that involve heating the ferroelectric to temperatures below the Curie point have been completed. Unfortunately, there is no practical method for heating only the capacitor; hence the entire integrated circuit would need to be heated. The Curie point of the PZT dielectric used in prior art capacitor's is typically above 450 °C. This temperature is above the temperature at which the aluminum conductors used for many of the conduction paths in the integrated circuit would be damaged. Hence, this solution has not been possible in prior art capacitor designs.

The present invention solves this problem by utilizing a dielectric material with a Curie point below 400°C. The Curie point ofPLZT may be adjusted by adjusting the composition of the P ZT. For example, prior art capacitors typically employed a PZT composition having 20% Zr and 80% Ti in the B sites of the ceramic. This composition leads to a Curie point of about 450°C. In contrast, PLZT having a composition of 8/20/80 has a Curie point of about 300°C. Hence, the damage done by heating the capacitors in post capacitor fabrication operations may be cured by annealing the capacitors at a temperature that is about 50°C above the Curie point, i.e., 350°C. In fabrication protocols utilizing a final anneal in the hydrogen atmosphere as described above, this anneal also cures the damage resulting from the prior sub-curie point i ating operations. If the final processing step prior to packaging does not use sucl. an anneal, a separate annealing step may be used.

Other PLZT compositions may be used to provide a Curie point at different temperatures. Table I lists a number of different PLZT compositions and the Curie points of the resulting dielectrics. Here, a composition of x/y/z means that the ferroelectric has x% lead in the A site, and the remaining A sites are filed with La. The B sites have y% Zr and z% Ti.

Composition Curie Point (°C)

8/20/80 -300

8/40/60 240

12/40/60 140

0/65/35 370

2/65/35 320

6/65/35 190

7/65/35 155

8/65/35 110

Capacitors constructed from barium titanate have problems similar to those constructed from PZT. Barium titanate compositions typically provide a Curie point of approximately 120°C which will allow the capacitors to be annealed at a temperature above the Curie point without damaging the aluminum conductors.

It should be noted, however, that a material with too low a Curie point is also poorly suited for integrated circuit memories that are to operate over the normal temperature ranges. Memory devices store information in the remnant polarization of the ferroelectric. Typically, a polarization in one direction is used to store a "0", and a polarization in the other direction is used to store a " 1 ". If the operating temperature of the device is too near the Curie point, information will be lost, since the remnant polarization also disappears at the Curie point. In this regard, it is important to note that there is a statistical distribution of domains in most ferroelectric compositions. Hence, some of the domains will be lost before the temperature reaches the Curie point.

It should also be noted that ferroelectrics with low Curie points have been known to the prior art for some time. The present invention is based on the combination of polarized ferroelectrics and aluminum or other low melting point conductors in an integrated circuit. In the presence of these low temperature conductors that prevents prior art systems using high Curie point ferroelectrics from being annealed after the forming anneal.

Various modifications to the present invention will become apparent to those skilled in the art from the foregoing description and accompanying drawings. Accordingly, the present invention is to be limited solely by the scope of the following claims.

Claims

WHAT IS CLAIMED:

1. In an integrated circuit comprising a conduction path and a ferroelectric layer, said ferroelectric layer having a polarization that is switched between two states during the operation of said integrated circuit, the improvement comprising constructing said ferroelectric layer from a material having a Curie point temperature less than the temperature at which said conduction path is damaged.

2. The integrated circuit of Claim 1 wherein said ferroelectric layer comprises a PZT layer.

3. The integrated circuit of Claim 1 wherein said ferroelectric layer comprises a PLZT layer.

4. The integrated circuit of Claim 1 wherein said ferroelectric layer comprises barium titanate layer.

5. The integrated circuit of Claim 1 wherein said Curie point is below 400 °C.

6. The integrated circuit of Claim 1 wherein said conduction path comprises aluminum.