KR920005316A - 다층배선방법 - Google Patents

다층배선방법 Download PDF

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Publication number
KR920005316A
KR920005316A KR1019910010743A KR910010743A KR920005316A KR 920005316 A KR920005316 A KR 920005316A KR 1019910010743 A KR1019910010743 A KR 1019910010743A KR 910010743 A KR910010743 A KR 910010743A KR 920005316 A KR920005316 A KR 920005316A
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South Korea
Prior art keywords
wiring
signal
layer
group
signal wiring
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KR1019910010743A
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English (en)
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KR950007423B1 (ko
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가쓰요시 스즈끼
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미다 가쓰시게
가부시기가이샤 히다찌세이사꾸쇼
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Publication of KR920005316A publication Critical patent/KR920005316A/ko
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Publication of KR950007423B1 publication Critical patent/KR950007423B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76892—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern
    • H01L21/76894—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern using a laser, e.g. laser cutting, laser direct writing, laser repair
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Optics & Photonics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

내용 없음

Description

다층배선방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본원 발명의 일실시예에 관한 다층배선방법을 일양태로 실시한 반도체집적회로칩의 다층배선의 상태를 설명하는 부분단면도,
제2도는 최하위층으로부터 최상위층으로 셀단자를 인상하는 인상배선경로의일예의 설명도,
제3도는 회로요소의 셀단자로부터 고정의 배선패턴을 사용하여 최상위층에인상배선을 행하는 배선예를 나타낸 도면.

Claims (7)

  1. 다층의 배선층을 가진 반도체집적회로의 회로소자 사이의 신호배선을 다층의 배선층을 사용하여 행하는 다층배선방법에 있어서, 신호배선을 보수가능성이 낮은 제1의 신호배선군과 보수가능성이 높은 제2의 신호배선군으로 분할하여, 제1의 신호배선군의 신호배선을 다층배선층의 하층에 할당하여 배선하고, 다음에 제2의 신호 배선군의 신호배선을 다층배선층의 상층에 할당하여 배선하는 것을 특징으로 하는 다층배선방법.
  2. 제1항에 있어서, 보수가능성이 높은 제2의 신호배선군의 신호선은 신호지연시간 허용범위가 큰 논리신호 배선인 것을 특징으로 하는 다층배선방법.
  3. 제1항에 있어서, 신호배선군을 보수가능성의 가능성비율에 의해 3단계이상으로 분류하여, 가장 보수가능성이 높은 신호배선군을 다층배선의 상층에 할당하고, 가장 보수가능성이 낮은 신호배선군은 다층배선의 하층에 할당하고 그 중간의 것에 대해서는 보수가능성이 높은것으로부터 차례로 배선경로가 비어 있는 상층에 할당해가는 것을 특징으로 하는 다층배선방법.
  4. 제1항에 있어서, 보수가능성에 의해서 분류된 각 신호배선군의 각 신호에 각신호배선군별로 보수가능성이 높은 순으로 큰 비중을 부여하고, 배선경로, 배선층결정시에 비중이 큰 신호배선을 우선적으로 다층배선의 상층에 할당하여 배선하는 것을 특징으로 하는 다층배선방법.
  5. 제4항에 있어서, 비중이 큰 신호배선을 우선적으로 다층배선의 상층에 할당하여 배선하여 방법으로서, 배선처리를 비중별로 분류된 신호배선군의 비중이 큰 군으로부터 차례로 상층을 우선적으로 사용하여 행하는 것을 특징으로 하는 다층배선방법.
  6. 다층의 배선층을 가진 반도체집적회로의 회로소자의 셀단자 이의 신호배선을다층의 배선층을 사용하여 행하는 다층배선방법에 있어서, 신호배선종별마다에 각 배선층을 할당하여 다층배선을 행하는 경우에, 신호배선을 보수가능성이 낮은 제1의 신호배선군과 보수가능성이 높은 제2의 신호배선군으로 분할하여, 제1의 신호배선군의 신호배선의 셀단자 및 미사용의 셀단자는 배선층의 하층에 배치하여 배선을 행하고, 제2의 신호배선군의 신호배선의 셀단자는 배선층의 상층까지 인출한 후에 배선을 행하는 것을 특징으로 하는 다층배선방법.
  7. 제6항에 있어서, 보수가능성이 높은 제2의 신호배선군의 신호배선의 셀단자를 배선층의 상층까지 인출하는 인상배선에 대해, 상층까지 인상하는 선로를 라이브러리화해 두고, 셀단자의 인상배선은 라이브러리를 전개한이상 배선패턴에 의해 형성하는 것을 특징으로 하는 다층배선방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910010743A 1990-08-28 1991-06-27 다층배선방법 KR950007423B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP90-228770 1990-08-28
JP2228770A JP2731288B2 (ja) 1990-08-28 1990-08-28 多層配線方法
JP90-228,770 1990-08-28

Publications (2)

Publication Number Publication Date
KR920005316A true KR920005316A (ko) 1992-03-28
KR950007423B1 KR950007423B1 (ko) 1995-07-10

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US (1) US5196362A (ko)
JP (1) JP2731288B2 (ko)
KR (1) KR950007423B1 (ko)
DE (1) DE4128568C2 (ko)

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Also Published As

Publication number Publication date
KR950007423B1 (ko) 1995-07-10
JP2731288B2 (ja) 1998-03-25
US5196362A (en) 1993-03-23
DE4128568A1 (de) 1992-03-05
DE4128568C2 (de) 2001-03-29
JPH04107951A (ja) 1992-04-09

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