DE3852692T2 - Integriertes Schaltkreis-Bauelement vom Typ "Master Slice" und dessen Verwendung. - Google Patents

Integriertes Schaltkreis-Bauelement vom Typ "Master Slice" und dessen Verwendung.

Info

Publication number
DE3852692T2
DE3852692T2 DE3852692T DE3852692T DE3852692T2 DE 3852692 T2 DE3852692 T2 DE 3852692T2 DE 3852692 T DE3852692 T DE 3852692T DE 3852692 T DE3852692 T DE 3852692T DE 3852692 T2 DE3852692 T2 DE 3852692T2
Authority
DE
Germany
Prior art keywords
type
integrated circuit
circuit component
master slice
slice
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3852692T
Other languages
English (en)
Other versions
DE3852692D1 (de
Inventor
Yuko Fukui
Katsuhiro Ohtani
Hiroyuki Miyamoto
Masao Nishiura
Moriyuki Chimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP62267066A external-priority patent/JPH01109743A/ja
Priority claimed from JP26706587A external-priority patent/JPH0748554B2/ja
Priority claimed from JP26706787A external-priority patent/JPH0748555B2/ja
Priority claimed from JP27621487A external-priority patent/JPH0748556B2/ja
Priority claimed from JP63145156A external-priority patent/JPH0728013B2/ja
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Publication of DE3852692D1 publication Critical patent/DE3852692D1/de
Application granted granted Critical
Publication of DE3852692T2 publication Critical patent/DE3852692T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
DE3852692T 1987-10-22 1988-10-19 Integriertes Schaltkreis-Bauelement vom Typ "Master Slice" und dessen Verwendung. Expired - Fee Related DE3852692T2 (de)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP62267066A JPH01109743A (ja) 1987-10-22 1987-10-22 マスタースライス方式半導体集積回路装置の製造方法
JP26706587A JPH0748554B2 (ja) 1987-10-22 1987-10-22 マスタースライス方式半導体集積回路装置の製造方法
JP26706787A JPH0748555B2 (ja) 1987-10-22 1987-10-22 マスタースライス方式半導体集積回路装置の製造方法
JP27621487A JPH0748556B2 (ja) 1987-10-30 1987-10-30 マスタースライス方式半導体集積回路装置の製造方法
JP63145156A JPH0728013B2 (ja) 1988-06-13 1988-06-13 マスタースライス方式半導体集積回路装置の製造方法

Publications (2)

Publication Number Publication Date
DE3852692D1 DE3852692D1 (de) 1995-02-16
DE3852692T2 true DE3852692T2 (de) 1995-08-03

Family

ID=27527728

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3852692T Expired - Fee Related DE3852692T2 (de) 1987-10-22 1988-10-19 Integriertes Schaltkreis-Bauelement vom Typ "Master Slice" und dessen Verwendung.

Country Status (3)

Country Link
EP (1) EP0314376B1 (de)
KR (1) KR930000602B1 (de)
DE (1) DE3852692T2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0338817B1 (de) * 1988-04-22 1999-09-08 Fujitsu Limited Integrierte Halbleiterschaltungsanordnung vom "Masterslice"-Typ
JP2731288B2 (ja) * 1990-08-28 1998-03-25 株式会社日立製作所 多層配線方法
US5399517A (en) * 1992-02-19 1995-03-21 Vlsi Technology, Inc. Method of routing three layer metal gate arrays using a channel router

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4197555A (en) * 1975-12-29 1980-04-08 Fujitsu Limited Semiconductor device
JPS6218732A (ja) * 1985-07-15 1987-01-27 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション 集積回路とその個性化方法

Also Published As

Publication number Publication date
KR930000602B1 (ko) 1993-01-25
KR890007379A (ko) 1989-06-19
DE3852692D1 (de) 1995-02-16
EP0314376B1 (de) 1995-01-04
EP0314376A1 (de) 1989-05-03

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD., KADOMA,

8339 Ceased/non-payment of the annual fee