KR890015353A - 도전율 변조 mos 반도체 전력 디바이스(himos) 및 그 제조방법 - Google Patents
도전율 변조 mos 반도체 전력 디바이스(himos) 및 그 제조방법 Download PDFInfo
- Publication number
- KR890015353A KR890015353A KR1019890003978A KR890003978A KR890015353A KR 890015353 A KR890015353 A KR 890015353A KR 1019890003978 A KR1019890003978 A KR 1019890003978A KR 890003978 A KR890003978 A KR 890003978A KR 890015353 A KR890015353 A KR 890015353A
- Authority
- KR
- South Korea
- Prior art keywords
- type
- layer
- manufacturing
- thin
- semiconductor
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000004065 semiconductor Substances 0.000 title claims 8
- 239000002019 doping agent Substances 0.000 claims description 4
- 238000000034 method Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 230000008021 deposition Effects 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 claims 1
- 238000002347 injection Methods 0.000 claims 1
- 239000007924 injection Substances 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/126—Power FETs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Thyristors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3a도 내지 제3e도는 여러 제조 프로세스 단계 중의 본 발명에 따른 구조를 도시한 개략도, 제3f는 본 발명에 따른 제조 프로세스 종료시의 HIMOS트랜지스터의 구조를 도시한 도면, 제4a도 및 제4b도는 종래 방법과 본 발명의 따른 방법으로 얻어질 수 있는 버퍼층내의 도펀트의 농도를 나타내는 곡선을 도시한 도면.
Claims (3)
- N+형(또는 P+형)얇은 "버퍼"층(2) 및 N-형(또는 P-형) 에피택셜층(3)이 위에 배치되는 P+형(또는 N+형) 반도체 기판(1)을 포함하는 드레인과의 직렬 P-N(또는 N-P) 접합부의 소수 캐리어 주입에 의해 드레인 영역의 도전율이 변조되는 형태의 N-채널(또는 P-채널) 도전율 변조 MOS 반도체 전력 디바이스를 제조하기 위한 방법에 있어서, 버퍼층(2) 형성 단계가 반도체 기판(1)상의 얇은 P형(또는 N형) 반도체층(4)에 에피택셜 성장 단계, 얇은 반도체층(4)내의 N형(또는 P형) 도펀트 피착 또는 이온 주입 단계, 및 N+(또는 P+)층을 형성할 수 있도록 충분한 온도 및 충분한 시간 길이에서의 도펀트 확산 단계를 실행하는 단계를 포함하고, 이 단계를 다음에 N-형(또는 P-형)층(3)의 에피택설 성장 단계가 뒤따르는 것을 특징으로 하는 제조방법.
- 제 1 항에 있어서, 최종 발생 N+(또는 P+)층의 두께가 박층(4)의 최초 두께보다 얇게 되도록, 얇은 반도체층(4)내의 도펀트의 학산이 일어나는 온도 및 시간이 제어되는 것을 특징으로 하는 제조방법.
- 제 1 항 또는 제 2 항의 제조 방법에 따라 얻어진 도전율 변조 MOS 반도체 전역 디바이스.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT20005/88A IT1218200B (it) | 1988-03-29 | 1988-03-29 | Procedimento di fabbricazione di un dispositivo semiconduttore mos di poterza a modulazione di conducibilita' (himos) e dispositivi con esso ottenuti |
IT200005A/88 | 1988-03-29 |
Publications (1)
Publication Number | Publication Date |
---|---|
KR890015353A true KR890015353A (ko) | 1989-10-30 |
Family
ID=11163042
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019890003978A KR890015353A (ko) | 1988-03-29 | 1989-03-29 | 도전율 변조 mos 반도체 전력 디바이스(himos) 및 그 제조방법 |
Country Status (6)
Country | Link |
---|---|
US (1) | US5073511A (ko) |
EP (1) | EP0335445B1 (ko) |
JP (1) | JP3012246B2 (ko) |
KR (1) | KR890015353A (ko) |
DE (1) | DE68910360T2 (ko) |
IT (1) | IT1218200B (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20020045241A (ko) * | 2000-12-08 | 2002-06-19 | 윤종용 | 공기조화기의 표시부 전원제어장치 |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5262336A (en) * | 1986-03-21 | 1993-11-16 | Advanced Power Technology, Inc. | IGBT process to produce platinum lifetime control |
JPH0691263B2 (ja) * | 1988-10-19 | 1994-11-14 | 株式会社東芝 | 半導体装置の製造方法 |
IT1241049B (it) * | 1990-03-08 | 1993-12-29 | Cons Ric Microelettronica | Dispositivo a semiconduttore igbt ad elevata tensione di rottura inversa e relativo processo di fabbricazione |
AU2024992A (en) * | 1991-05-07 | 1992-12-21 | Inframetrics Inc. | Apparatus for operating a conventional film camera in an electronic mode operation |
JP2810821B2 (ja) * | 1992-03-30 | 1998-10-15 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
EP0671770B1 (en) * | 1993-02-09 | 2000-08-02 | GENERAL SEMICONDUCTOR, Inc. | Multilayer epitaxy for a silicon diode |
US5892787A (en) * | 1994-10-27 | 1999-04-06 | Hewlett-Packard Company | N-drive, p-common light-emitting devices fabricated on an n-type substrate and method of making same |
EP0725446A1 (en) * | 1995-02-02 | 1996-08-07 | Motorola, Inc. | Insulated gate bipolar semiconductor device and method therefor |
US5770880A (en) * | 1996-09-03 | 1998-06-23 | Harris Corporation | P-collector H.V. PMOS switch VT adjusted source/drain |
US5872028A (en) * | 1996-09-05 | 1999-02-16 | Harris Corporation | Method of forming power semiconductor devices with controllable integrated buffer |
DE19811297B4 (de) | 1997-03-17 | 2009-03-19 | Fuji Electric Co., Ltd., Kawasaki | MOS-Halbleitervorrichtung mit hoher Durchbruchspannung |
JP2006526272A (ja) * | 2003-05-19 | 2006-11-16 | エスティマイクロエレクトロニクス ソシエタ ア レスポンサビリタ リミタータ | 高速切替え速度を有する電源装置及びその製造方法 |
EP4084070A4 (en) * | 2019-12-28 | 2024-02-07 | Keming Wang | NEW PRINCIPLES AND TECHNOLOGY FOR SEMICONDUCTOR ELECTRONICS, AND DEVICE |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4364073A (en) * | 1980-03-25 | 1982-12-14 | Rca Corporation | Power MOSFET with an anode region |
FR2535901A1 (fr) * | 1982-11-10 | 1984-05-11 | Silicium Semiconducteur Ssc | Thyristor asymetrique a forte tenue en tension inverse |
JPS60260152A (ja) * | 1984-06-07 | 1985-12-23 | Nec Corp | 半導体装置 |
JPS6134753A (ja) * | 1984-07-25 | 1986-02-19 | Hitachi Ltd | 回転ヘツド型磁気記録再生装置 |
JPS6134753U (ja) * | 1984-07-31 | 1986-03-03 | 株式会社明電舎 | 半導体装置 |
US4696701A (en) * | 1986-11-12 | 1987-09-29 | Motorola, Inc. | Epitaxial front seal for a wafer |
-
1988
- 1988-03-29 IT IT20005/88A patent/IT1218200B/it active
-
1989
- 1989-03-21 EP EP89200717A patent/EP0335445B1/en not_active Expired - Lifetime
- 1989-03-21 DE DE89200717T patent/DE68910360T2/de not_active Expired - Fee Related
- 1989-03-28 JP JP1074109A patent/JP3012246B2/ja not_active Expired - Fee Related
- 1989-03-29 KR KR1019890003978A patent/KR890015353A/ko not_active Application Discontinuation
- 1989-03-29 US US07/330,182 patent/US5073511A/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20020045241A (ko) * | 2000-12-08 | 2002-06-19 | 윤종용 | 공기조화기의 표시부 전원제어장치 |
Also Published As
Publication number | Publication date |
---|---|
EP0335445A1 (en) | 1989-10-04 |
JPH0210874A (ja) | 1990-01-16 |
IT8820005A0 (it) | 1988-03-29 |
EP0335445B1 (en) | 1993-11-03 |
US5073511A (en) | 1991-12-17 |
DE68910360T2 (de) | 1994-03-31 |
DE68910360D1 (de) | 1993-12-09 |
JP3012246B2 (ja) | 2000-02-21 |
IT1218200B (it) | 1990-04-12 |
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Legal Events
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WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |