KR910005422A - 반도체 집적회로의 i²l게이트 제조방법 - Google Patents
반도체 집적회로의 i²l게이트 제조방법 Download PDFInfo
- Publication number
- KR910005422A KR910005422A KR1019890012026A KR890012026A KR910005422A KR 910005422 A KR910005422 A KR 910005422A KR 1019890012026 A KR1019890012026 A KR 1019890012026A KR 890012026 A KR890012026 A KR 890012026A KR 910005422 A KR910005422 A KR 910005422A
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- integrated circuit
- semiconductor integrated
- gate
- manufacturing
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 3
- 239000004065 semiconductor Substances 0.000 title claims 2
- 238000002955 isolation Methods 0.000 claims 2
- 238000009792 diffusion process Methods 0.000 claims 1
- 238000010438 heat treatment Methods 0.000 claims 1
- 238000000034 method Methods 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 I2L게이트 제조 순서도.
Claims (2)
- P-형 기판(1)위에 N+매입층(2)을 형성시키고 이 N-매입층(2) 위에 P+형 하부 격리층(3)을 매입하여 N-에피층(4)을 성장시킨후 열처리하여 전류 주입기인 래터럴 PNP의 콜렉터와 만나도록 확산시켜 N-에피층(4)에 N+확산층인 에미터(5)을 형성하므로 스위칭 트랜지스터가 N+-P+-N--N+의 수직수조를 갖게함을 특징으로 하는 반도체 집적회로의 I²L게이트 제조방법.
- 제1항에 있어서, P+하부 격리층(3)을 베이스(3a)층으로 이용하여 스위칭 트랜지스터의 베이스 저항을 감소시킴을 특징으로 하는 반도체 집적회로의 I²L게이트 제조방법.※참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019890012026A KR0151125B1 (ko) | 1989-08-23 | 1989-08-23 | 반도체 집적회로의 i2l 게이트 제조방법 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019890012026A KR0151125B1 (ko) | 1989-08-23 | 1989-08-23 | 반도체 집적회로의 i2l 게이트 제조방법 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR910005422A true KR910005422A (ko) | 1991-03-30 |
| KR0151125B1 KR0151125B1 (ko) | 1998-10-01 |
Family
ID=19289181
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019890012026A KR0151125B1 (ko) | 1989-08-23 | 1989-08-23 | 반도체 집적회로의 i2l 게이트 제조방법 |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0151125B1 (ko) |
-
1989
- 1989-08-23 KR KR1019890012026A patent/KR0151125B1/ko not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR0151125B1 (ko) | 1998-10-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20120524 Year of fee payment: 15 |
|
| EXPY | Expiration of term |