KR930001466A - Pnp 디바이스를 위한 p 매립층의 제조방법 - Google Patents
Pnp 디바이스를 위한 p 매립층의 제조방법 Download PDFInfo
- Publication number
- KR930001466A KR930001466A KR1019920009683A KR920009683A KR930001466A KR 930001466 A KR930001466 A KR 930001466A KR 1019920009683 A KR1019920009683 A KR 1019920009683A KR 920009683 A KR920009683 A KR 920009683A KR 930001466 A KR930001466 A KR 930001466A
- Authority
- KR
- South Korea
- Prior art keywords
- buried layer
- manufacturing
- pnp device
- silicon structure
- pnp
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 229910052732 germanium Inorganic materials 0.000 claims description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 claims 1
- 239000012535 impurity Substances 0.000 claims 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/2205—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities from the substrate during epitaxy, e.g. autodoping; Preventing or using autodoping
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8222—Bipolar technology
- H01L21/8228—Complementary devices, e.g. complementary transistors
- H01L21/82285—Complementary vertical transistors
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/058—Ge germanium
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Ceramic Engineering (AREA)
- Bipolar Transistors (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 단독으로 이온주입된 붕소 및 갈륨의 도펀트 농도에 대하여, 그리고 게르마늄 존재하에 이온주입된 붕소 및 갈륨의 도펀트 농도에 대하여 사후-어닐링(post-anneal)프로파일을 도시한 그래프.
제3도에서 제6도까지는 p-매립층을 형성하는 단계를 설명하는 실리콘 웨이퍼 부분의 단면을 도시한 도면들.
제7도는 실선은 게르마늄을 포함한 P-매립층을 표시하며 점선은 게르마늄을 포함하지 않은 층을 표시하는, 제6도의 단계 이후캐리어 농도를 도시한 그래프.
Claims (1)
- 실리콘 구조내의 매립층P-형 활성 불순물들의 외방확산을 지연시키기 위한, 상기 매립층 영역내의 상기 실리콘 구조내로 게르마늄을 결합시키는 단계를 포함하는 프로세스.※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US7/710,646 | 1991-06-05 | ||
US07/710,646 US5137838A (en) | 1991-06-05 | 1991-06-05 | Method of fabricating P-buried layers for PNP devices |
US07/710,646 | 1991-06-05 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR930001466A true KR930001466A (ko) | 1993-01-16 |
KR100272067B1 KR100272067B1 (ko) | 2000-11-15 |
Family
ID=24854933
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920009683A KR100272067B1 (ko) | 1991-06-05 | 1992-06-04 | Pnp 디바이스를 위한 p 매립층의 제조방법 |
Country Status (4)
Country | Link |
---|---|
US (1) | US5137838A (ko) |
EP (1) | EP0536869A3 (ko) |
JP (1) | JP3199452B2 (ko) |
KR (1) | KR100272067B1 (ko) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5296387A (en) * | 1991-03-06 | 1994-03-22 | National Semiconductor Corporation | Method of providing lower contact resistance in MOS transistor structures |
US5792679A (en) * | 1993-08-30 | 1998-08-11 | Sharp Microelectronics Technology, Inc. | Method for forming silicon-germanium/Si/silicon dioxide heterostructure using germanium implant |
US5633177A (en) * | 1993-11-08 | 1997-05-27 | Advanced Micro Devices, Inc. | Method for producing a semiconductor gate conductor having an impurity migration barrier |
US5861321A (en) * | 1995-11-21 | 1999-01-19 | Texas Instruments Incorporated | Method for doping epitaxial layers using doped substrate material |
JPH10261588A (ja) * | 1997-03-19 | 1998-09-29 | Mitsubishi Electric Corp | 半導体装置 |
FR2779005B1 (fr) * | 1998-05-19 | 2000-07-13 | Sgs Thomson Microelectronics | Procede de depot par epitaxie d'une couche de silicium sur un substrat de silicium fortement dope |
JP2003197908A (ja) * | 2001-09-12 | 2003-07-11 | Seiko Instruments Inc | 半導体素子及びその製造方法 |
US8530934B2 (en) | 2005-11-07 | 2013-09-10 | Atmel Corporation | Integrated circuit structures containing a strain-compensated compound semiconductor layer and methods and systems related thereto |
JP4677890B2 (ja) | 2005-11-29 | 2011-04-27 | 信越半導体株式会社 | 埋め込み拡散エピタキシャルウエーハの製造方法および埋め込み拡散エピタキシャルウエーハ |
US20070148890A1 (en) * | 2005-12-27 | 2007-06-28 | Enicks Darwin G | Oxygen enhanced metastable silicon germanium film layer |
US20070262295A1 (en) * | 2006-05-11 | 2007-11-15 | Atmel Corporation | A method for manipulation of oxygen within semiconductor materials |
US7550758B2 (en) | 2006-10-31 | 2009-06-23 | Atmel Corporation | Method for providing a nanoscale, high electron mobility transistor (HEMT) on insulator |
US8159868B2 (en) * | 2008-08-22 | 2012-04-17 | Zeno Semiconductor, Inc. | Semiconductor memory having both volatile and non-volatile functionality including resistance change material and method of operating |
US20090004458A1 (en) * | 2007-06-29 | 2009-01-01 | Memc Electronic Materials, Inc. | Diffusion Control in Heavily Doped Substrates |
US20090004426A1 (en) * | 2007-06-29 | 2009-01-01 | Memc Electronic Materials, Inc. | Suppression of Oxygen Precipitation in Heavily Doped Single Crystal Silicon Substrates |
US20090032885A1 (en) * | 2007-07-31 | 2009-02-05 | Intersil Americas, Inc. | Buried Isolation Layer |
US7868387B2 (en) | 2008-06-13 | 2011-01-11 | Analog Devices, Inc. | Low leakage protection device |
US8828816B2 (en) | 2011-05-25 | 2014-09-09 | Globalfoundries Inc. | PMOS threshold voltage control by germanium implantation |
JP2013058644A (ja) * | 2011-09-08 | 2013-03-28 | Ricoh Co Ltd | 半導体装置の製造方法 |
US10832913B2 (en) * | 2018-02-14 | 2020-11-10 | Taiwan Semiconductor Manufacturing Company Ltd. | Method and apparatus for forming semiconductor structure |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5917243A (ja) * | 1982-07-21 | 1984-01-28 | Hitachi Ltd | 半導体装置の製造方法 |
US4603471A (en) * | 1984-09-06 | 1986-08-05 | Fairchild Semiconductor Corporation | Method for making a CMOS circuit having a reduced tendency to latch by controlling the band-gap of source and drain regions |
US4940671A (en) * | 1986-04-18 | 1990-07-10 | National Semiconductor Corporation | High voltage complementary NPN/PNP process |
US4746964A (en) * | 1986-08-28 | 1988-05-24 | Fairchild Semiconductor Corporation | Modification of properties of p-type dopants with other p-type dopants |
JPS63137414A (ja) * | 1986-11-28 | 1988-06-09 | Nec Corp | 半導体薄膜の製造方法 |
US4728619A (en) * | 1987-06-19 | 1988-03-01 | Motorola, Inc. | Field implant process for CMOS using germanium |
US4835112A (en) * | 1988-03-08 | 1989-05-30 | Motorola, Inc. | CMOS salicide process using germanium implantation |
JPH02102558A (ja) * | 1988-10-12 | 1990-04-16 | Oki Electric Ind Co Ltd | 半導体素子の製造方法 |
WO1990005993A1 (en) * | 1988-11-21 | 1990-05-31 | Micron Technology, Inc. | High performance sub-micron p-channel transistor with germanium implant |
US5134447A (en) * | 1989-09-22 | 1992-07-28 | At&T Bell Laboratories | Neutral impurities to increase lifetime of operation of semiconductor devices |
-
1991
- 1991-06-05 US US07/710,646 patent/US5137838A/en not_active Expired - Lifetime
-
1992
- 1992-05-27 EP EP19920304751 patent/EP0536869A3/en not_active Withdrawn
- 1992-06-04 KR KR1019920009683A patent/KR100272067B1/ko not_active IP Right Cessation
- 1992-06-05 JP JP14595892A patent/JP3199452B2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0536869A3 (en) | 1993-06-23 |
JP3199452B2 (ja) | 2001-08-20 |
KR100272067B1 (ko) | 2000-11-15 |
JPH05183046A (ja) | 1993-07-23 |
EP0536869A2 (en) | 1993-04-14 |
US5137838A (en) | 1992-08-11 |
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