KR900002465A - 반도체장치의 제조방법 - Google Patents

반도체장치의 제조방법 Download PDF

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Publication number
KR900002465A
KR900002465A KR1019880008698A KR880008698A KR900002465A KR 900002465 A KR900002465 A KR 900002465A KR 1019880008698 A KR1019880008698 A KR 1019880008698A KR 880008698 A KR880008698 A KR 880008698A KR 900002465 A KR900002465 A KR 900002465A
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KR
South Korea
Prior art keywords
epitaxial layer
silicon epitaxial
etching
layer
type well
Prior art date
Application number
KR1019880008698A
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English (en)
Other versions
KR910009739B1 (ko
Inventor
강창원
민성기
윤종밀
Original Assignee
강진구
삼성반도체통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 강진구, 삼성반도체통신 주식회사 filed Critical 강진구
Priority to KR1019880008698A priority Critical patent/KR910009739B1/ko
Priority to US07/353,105 priority patent/US4950616A/en
Priority to JP1124662A priority patent/JPH0240947A/ja
Publication of KR900002465A publication Critical patent/KR900002465A/ko
Application granted granted Critical
Publication of KR910009739B1 publication Critical patent/KR910009739B1/ko

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Classifications

    • H01L29/70—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions
    • H01L27/06—
    • H01L29/68—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/009—Bi-MOS

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Bipolar Transistors (AREA)

Abstract

내용 없음

Description

반도체장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 (가)도에서 (자)도는 본 발명 반도체장치의 제조공정을 순차적으로 도시한 절단면도.
제2도는 본 발명에 의하여 완성된 반도체장치의 절단면도.

Claims (2)

  1. 실리콘기판(1)에 매몰층(2)(3)을 형성시키는 공정과, 실리콘 에피텍셜층(4)의 성장후 식각시키는 공정과, pMOS트랜지스터, nMOS트랜지스터, 바이폴라트랜지스터를 형성시키는 공정과로 되고, 실리콘 에피텍셜층(4)을 식각시키는 공정은, 고속바이폴라 트랜지스터가 형성될 웰부위의 실리콘 에피텍셜층이 선택적으로 얇게 되게 식각시키는 공정과, nMOS트랜지스터가 형성될 웰부위의 실리콘 에피텍셜층은 성장된 두께를 그대로 유지되게 하는 공정과로 된 것을 특징으로 하는 반도체장치의 제조방법.
  2. 제1항에 있어서, 실리콘 에피텍셜층(4)의 성장후 식각시키는 공정중 p형 웰(16)이 형성될 영역에는 질화막층(6)이 식각된 상태에서 3가 불순물원소가 이온주입되게 하고 n형 웰(15)이 형성될 부위는 P형 웰(16)이 형성된 후 상부 전표면의 산화막층(9)이 식가되게 한 것을 특징으로 하는 반도체장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880008698A 1988-07-13 1988-07-13 반도체장치의 제조방법 KR910009739B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019880008698A KR910009739B1 (ko) 1988-07-13 1988-07-13 반도체장치의 제조방법
US07/353,105 US4950616A (en) 1988-07-13 1989-05-17 Method for fabricating a BiCMOS device
JP1124662A JPH0240947A (ja) 1988-07-13 1989-05-19 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019880008698A KR910009739B1 (ko) 1988-07-13 1988-07-13 반도체장치의 제조방법

Publications (2)

Publication Number Publication Date
KR900002465A true KR900002465A (ko) 1990-02-28
KR910009739B1 KR910009739B1 (ko) 1991-11-29

Family

ID=19276035

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880008698A KR910009739B1 (ko) 1988-07-13 1988-07-13 반도체장치의 제조방법

Country Status (3)

Country Link
US (1) US4950616A (ko)
JP (1) JPH0240947A (ko)
KR (1) KR910009739B1 (ko)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55156370A (en) * 1979-05-25 1980-12-05 Hitachi Ltd Manufacture of semiconductor device
US5252505A (en) * 1979-05-25 1993-10-12 Hitachi, Ltd. Method for manufacturing a semiconductor device
JP2569171B2 (ja) * 1989-04-12 1997-01-08 株式会社日立製作所 半導体装置
US5102811A (en) * 1990-03-20 1992-04-07 Texas Instruments Incorporated High voltage bipolar transistor in BiCMOS
US5407860A (en) * 1994-05-27 1995-04-18 Texas Instruments Incorporated Method of forming air gap dielectric spaces between semiconductor leads
JP2790084B2 (ja) * 1995-08-16 1998-08-27 日本電気株式会社 半導体装置の製造方法
US5783470A (en) * 1995-12-14 1998-07-21 Lsi Logic Corporation Method of making CMOS dynamic random-access memory structures and the like
KR100261165B1 (ko) 1998-05-14 2000-07-01 김영환 반도체소자 및 그의 제조방법

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5447493A (en) * 1977-09-21 1979-04-14 Hitachi Ltd Semiconductor integrated circuit device and production of the same
JPS55160443A (en) * 1979-05-22 1980-12-13 Semiconductor Res Found Manufacture of semiconductor integrated circuit device
US4425516A (en) * 1981-05-01 1984-01-10 Zytrex Corporation Buffer circuit and integrated semiconductor circuit structure formed of bipolar and CMOS transistor elements
DE3175429D1 (en) * 1981-11-28 1986-11-06 Itt Ind Gmbh Deutsche Process for producing a monolithic integrated circuit having at least one pair of complementary field-effect transistors and at least one bipolar transistor
NL188923C (nl) * 1983-07-05 1992-11-02 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting.
US4536945A (en) * 1983-11-02 1985-08-27 National Semiconductor Corporation Process for producing CMOS structures with Schottky bipolar transistors
FR2571178B1 (fr) * 1984-09-28 1986-11-21 Thomson Csf Structure de circuit integre comportant des transistors cmos a tenue en tension elevee, et son procede de fabrication
JPS61236153A (ja) * 1985-04-12 1986-10-21 Hitachi Ltd 半導体装置
JPS62149163A (ja) * 1985-08-30 1987-07-03 Nec Corp 相補型ｍｏｓ集積回路の製造方法
US4717680A (en) * 1985-10-16 1988-01-05 Harris Corporation Fabrication of vertical NPN and PNP bipolar transistors in monolithic substrate
JPS62154779A (ja) * 1985-12-27 1987-07-09 Hitachi Ltd 半導体集積回路装置
GB2188479B (en) * 1986-03-26 1990-05-23 Stc Plc Semiconductor devices
US4727046A (en) * 1986-07-16 1988-02-23 Fairchild Semiconductor Corporation Method of fabricating high performance BiCMOS structures having poly emitters and silicided bases
JPS6367776A (ja) * 1986-09-09 1988-03-26 Sharp Corp バイポ−ラｉｃの製造方法
US4734382A (en) * 1987-02-20 1988-03-29 Fairchild Semiconductor Corporation BiCMOS process having narrow bipolar emitter and implanted aluminum isolation

Also Published As

Publication number Publication date
US4950616A (en) 1990-08-21
JPH0240947A (ja) 1990-02-09
KR910009739B1 (ko) 1991-11-29

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