KR880014649A - 반도체 장치 및 그 제조방법 - Google Patents

반도체 장치 및 그 제조방법 Download PDF

Info

Publication number
KR880014649A
KR880014649A KR1019880006152A KR880006152A KR880014649A KR 880014649 A KR880014649 A KR 880014649A KR 1019880006152 A KR1019880006152 A KR 1019880006152A KR 880006152 A KR880006152 A KR 880006152A KR 880014649 A KR880014649 A KR 880014649A
Authority
KR
South Korea
Prior art keywords
layer
contact
region
semiconductor
silicon
Prior art date
Application number
KR1019880006152A
Other languages
English (en)
Inventor
페트루스 비데르 쇼펜 프란스시쿠스
Original Assignee
이반 밀러 레르너
엔.브이 필립스 글로아이람펜파브리켄
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 이반 밀러 레르너, 엔.브이 필립스 글로아이람펜파브리켄 filed Critical 이반 밀러 레르너
Publication of KR880014649A publication Critical patent/KR880014649A/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1087—Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78609—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/901—MOSFET substrate bias

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)

Abstract

내용없음

Description

반도체 장치 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 의해 반도체 장치의 개략적인 실시예의 횡단면도, 제2도 내지 4도는 본 발명에 따른 방법의 실시예에 의한 반도체 장치의 연속제조 단계의 개략 횡단면도.

Claims (10)

  1. 절연기판상에 피착된 제1도전형의 실리콘측과, 제2도전형의 반도체 회로소자의 두 영역 및 실리콘층과 동일한 도전형이나 그보다는 도핑농도가 높게 되어 있는 접촉영역을 구비하여 상기 영역들이 실리콘층의 표면과 실제로 접하고 있는 반도체장치에 있어서, 접촉영역이 제2도전형의 반도체 회로소자의 영역밑으로 확장되는 것을 특징으로 하는 반도체 장치.
  2. 제1항에 있어서, 접촉영역이 반도체 회로소자의 전체를 실리콘층에서 감싸고 있는 것을 특징으로 하는 반도체 장치.
  3. 제1항 또는 제2항에 있어서, 접촉영역은 반도체 회로소자의 영역이외의 표면과 접하고 있는 주입영역을 구비하여 이 표면으로부터 실리콘층의 점차 깊어지는 영역의 방향으로 배치되는 것을 특징으로 하는 반도체 장치.
  4. 제1항 또는 제2항에 있어서, 반도체 회로소자가 실리콘층에 배치된 제2전도형의 소스 및 드레인 영역을 가진 전계효과 트랜지스터를 구비하고 있고, 접촉영역이 하부기판 아래에 접하고 있는 것을 특징으로 하는 반도체 장치.
  5. 제4항에 있어서, 소스 및 드레인 영역과 접촉영역과 거리가 0.35μm이상인 것을 특징으로 하는 반도체장치.
  6. 선행항중의 어느 한 항에 있어서, 접촉영역이 다른 지역보다 국부적으로 높은 도핑농도를 가진 표면에 있는 것을 특징으로 하는 반도체 장치.
  7. 절연기판상에 배치된 제1도전형의 실리콘층에서 동일 전형도이나 실리콘층보다 도핑농도가 높은 접촉영역이 형성되고, 제2전도형을 가진 반도체 회로소자의 두 영역이 형성되어 이들 영역이 실리콘층의 표면과 접하는 반도체장치의 제조방법에 있어서, 실리콘층이 마스킹층으로 일부 피복되고, 마스킹층에 의해 피복되지 않은 실리콘층의 일부와 접하는 마스킹층의 가장자리 부분은 경사지며, 마스킹층에 의해 피복되지 않은 실리콘층의 일부와 접하는 마스킹층의 가장가리 부분은 경사지며, 마스킹층에 의해 마스크되는 사이 이온주입에 의해 접촉영역에 형성되고 주입에너지와 마스킹층의 두께가 서로 조화되어 마스킹층에 의해 피복되지 않은 실리콘층의 일부에서 반도체 영역아래로 확장된 접촉영역이 마스킹층의 나머지부분 아래의 표면과 접합고 실리콘층에서 점차 고레벨로 된 가장자리부분 아래에 배치되며, 반도체 회로소자의 영역이 반도체 영역에 형성되는 것을 특징으로 하는 반도체 장치 제조방법.
  8. 제7항에 있어서, 마스킹층이 포토 레지스트층을 구비하고 있고, 그 가장자리 부분이 포토레지스트층을 열처리 하는데 경사지게 된 것을 특징으로 하는 반도체 장치.
  9. 제7항 또는 제8항에 있어서, 반도체 회로소자가 제2도전형의 소스 및 드레인 영역을 가진 전계효과 트랜지스터를 구비하고 있는 방법에 있어서, 마스킹층이 제공되기 이전에, 실리콘층이 산화 실리콘층으로 피복되고, 마스킹층에 의해 피복되지 않은 산화 실리콘층의 일부는 마스킹층에 의해 피복되는 동안 식각되며, 반도체 영역위에 전계효과 트랜지스터의 게이트 전극이 형성되고, 반도체 영역에서 소스 및 드레인영역이 주입에 의해 형성되고 이 주입에 대해 게이트 전극 및 산화 실리콘층이 마스킹 되는 것을 특징으로 하는 반도체 장치 제조방법.
  10. 제9항에 있어서, 소스 및 드레인 전극이 형성된 후 어셈블리상에 절연층이 제공되고, 접촉영역은 그 표면에서 일부 고 도핑농도로 되고 상기 절연층에서 접촉창이 식각되고 연속하여 주입이 실행되는 것을 특징으로 하는 반도체 장치 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880006152A 1987-05-06 1988-05-26 반도체 장치 및 그 제조방법 KR880014649A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NL8701251A NL8701251A (nl) 1987-05-26 1987-05-26 Halfgeleiderinrichting en werkwijze ter vervaardiging daarvan.
NL8701251 1987-05-26

Publications (1)

Publication Number Publication Date
KR880014649A true KR880014649A (ko) 1988-12-24

Family

ID=19850067

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880006152A KR880014649A (ko) 1987-05-06 1988-05-26 반도체 장치 및 그 제조방법

Country Status (5)

Country Link
US (2) US4864377A (ko)
EP (1) EP0294868A1 (ko)
JP (1) JPS63306667A (ko)
KR (1) KR880014649A (ko)
NL (1) NL8701251A (ko)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5231045A (en) * 1988-12-08 1993-07-27 Fujitsu Limited Method of producing semiconductor-on-insulator structure by besol process with charged insulating layers
EP0378906A1 (en) * 1988-12-08 1990-07-25 Fujitsu Limited Method of producing semiconductor-on-insulator structure and semiconductor device having semiconductor-on-insulator structure
US5238857A (en) * 1989-05-20 1993-08-24 Fujitsu Limited Method of fabricating a metal-oxide-semiconductor device having a semiconductor on insulator (SOI) structure
US5449953A (en) * 1990-09-14 1995-09-12 Westinghouse Electric Corporation Monolithic microwave integrated circuit on high resistivity silicon
US5621239A (en) * 1990-11-05 1997-04-15 Fujitsu Limited SOI device having a buried layer of reduced resistivity
USH1435H (en) * 1991-10-21 1995-05-02 Cherne Richard D SOI CMOS device having body extension for providing sidewall channel stop and bodytie
GB9315798D0 (en) * 1993-07-30 1993-09-15 Philips Electronics Uk Ltd Manufacture of electronic devices comprising thin-film transistors
US5360752A (en) * 1993-10-28 1994-11-01 Loral Federal Systems Company Method to radiation harden the buried oxide in silicon-on-insulator structures
JPH08115985A (ja) * 1994-10-17 1996-05-07 Nec Corp 低雑音の半導体集積回路
JP3399119B2 (ja) * 1994-11-10 2003-04-21 富士電機株式会社 半導体装置およびその製造方法
DE4441901C2 (de) * 1994-11-24 1998-07-02 Siemens Ag MOSFET auf SOI-Substrat und Verfahren zu dessen Herstellung
US5608253A (en) * 1995-03-22 1997-03-04 Advanced Micro Devices Inc. Advanced transistor structures with optimum short channel controls for high density/high performance integrated circuits
US5619053A (en) * 1995-05-31 1997-04-08 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having an SOI structure
JP2728070B2 (ja) * 1995-11-30 1998-03-18 日本電気株式会社 電界効果トランジスタ
JPH09248912A (ja) * 1996-01-11 1997-09-22 Canon Inc インクジェットヘッド及びヘッド用基体、インクジェットカートリッジ、並びにインクジェット装置
US5770881A (en) * 1996-09-12 1998-06-23 International Business Machines Coproration SOI FET design to reduce transient bipolar current
KR100248200B1 (ko) * 1996-12-30 2000-03-15 김영환 Soi 반도체 소자 및 그의 제조방법
US5916627A (en) * 1997-12-31 1999-06-29 Kemet Electronics Corp. Conductive polymer using self-regenerating oxidant
DE19844531B4 (de) 1998-09-29 2017-12-14 Prema Semiconductor Gmbh Verfahren zur Herstellung von Transistoren
EP1035566A3 (en) * 1999-03-03 2000-10-04 Infineon Technologies North America Corp. Method for forming a buried doped layer with connecting portions within a semiconductive device
DE60041863D1 (de) * 1999-07-02 2009-05-07 Mitsubishi Material Silicon Herstellungsverfahren eines soi substrats
US8981490B2 (en) * 2013-03-14 2015-03-17 Texas Instruments Incorporated Transistor with deep Nwell implanted through the gate

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3925120A (en) * 1969-10-27 1975-12-09 Hitachi Ltd A method for manufacturing a semiconductor device having a buried epitaxial layer
US3879745A (en) * 1969-11-11 1975-04-22 Philips Corp Semiconductor device
DE2641302A1 (de) * 1976-09-14 1978-03-16 Siemens Ag N-kanal mis-fet in esfi-technik
US4202002A (en) * 1977-01-19 1980-05-06 International Business Machines Corporation Ion-implanted layers with abrupt edges
US4454524A (en) * 1978-03-06 1984-06-12 Ncr Corporation Device having implantation for controlling gate parasitic action
JPS54162980A (en) * 1978-06-14 1979-12-25 Fujitsu Ltd Manufacture of semiconductor device
US4199773A (en) * 1978-08-29 1980-04-22 Rca Corporation Insulated gate field effect silicon-on-sapphire transistor and method of making same
JPS6040710B2 (ja) * 1978-11-14 1985-09-12 富士通株式会社 半導体記憶装置
JPS55113359A (en) * 1979-02-22 1980-09-01 Fujitsu Ltd Semiconductor integrated circuit device
JPS5627942A (en) * 1979-08-15 1981-03-18 Hitachi Ltd Semiconductor device and its manufacturing method
JPS5687340A (en) * 1979-12-19 1981-07-15 Fujitsu Ltd Semiconductor device and manufacture thereof
JPS5687359A (en) * 1979-12-19 1981-07-15 Fujitsu Ltd Manufacture of one transistor type memory cell
JPS5824018B2 (ja) * 1979-12-21 1983-05-18 富士通株式会社 バイポ−ラｉｃの製造方法
JPS5724548A (en) * 1980-07-22 1982-02-09 Nippon Telegr & Teleph Corp <Ntt> Manufacture of semiconductor device
JPS5727069A (en) * 1980-07-25 1982-02-13 Toshiba Corp Mos type simiconductor device
JPS5745947A (en) * 1980-09-03 1982-03-16 Toshiba Corp Mos type semiconductor integrated circuit
JPS59937A (ja) * 1982-06-25 1984-01-06 Nec Corp 半導体装置の製造方法
US4923820A (en) * 1985-09-18 1990-05-08 Harris Corporation IC which eliminates support bias influence on dielectrically isolated components
JPH0748516B2 (ja) * 1986-09-26 1995-05-24 アメリカン テレフォン アンド テレグラフ カムパニー 埋没導電層を有する誘電的に分離されたデバイスの製造方法

Also Published As

Publication number Publication date
NL8701251A (nl) 1988-12-16
US5034335A (en) 1991-07-23
EP0294868A1 (en) 1988-12-14
JPS63306667A (ja) 1988-12-14
US4864377A (en) 1989-09-05

Similar Documents

Publication Publication Date Title
KR880014649A (ko) 반도체 장치 및 그 제조방법
KR950015799A (ko) 플래시메모리 및 그 제조방법
KR930005257A (ko) 박막 전계효과 소자 및 그의 제조방법
KR960036041A (ko) 고내압 트랜지스터 및 그 제조방법
KR930014765A (ko) 전계 효과 트랜지스터를 구비한 반도체 디바이스 및 그 제조 방법
KR950034836A (ko) 절연 게이트 전계 효과 트랜지스터와 그 제조 방법
KR960024604A (ko) 이중 채널 박막트랜지스터 및 그 제조방법
KR890013796A (ko) 반도체장치 및 그 제조방법
KR900013652A (ko) 감소된 온 저항을 가진 soi구조의 고전압 반도체 장치
KR900019261A (ko) 반도체장치
KR940004846A (ko) 반도체장치 및 그 제조방법
KR930005259A (ko) 반도체 장치 및 그 제조 방법
KR910020932A (ko) 반도체장치 및 그 제조방법
KR900003967A (ko) 반도체 장치 및 그 제조 방법
KR970072204A (ko) 적어도 하나의 mos 트랜지스터를 가지는 회로 장치 및 그것의 제조방법
KR950034822A (ko) 고전압 트랜지스터 및 그 제조방법
KR910010731A (ko) 반도체장치 및 그 제조방법
KR970072432A (ko) Mos 커패시터를 갖는 반도체 디바이스 및 제조 방법
KR970004079A (ko) 반도체소자 및 그 제조방법
KR920022563A (ko) 반도체 장치 및 그 제조방법
KR970072491A (ko) 박막트랜지스터 및 그 제조방법
KR960032585A (ko) 반도체장치 및 그의 제조방법
KR910001876A (ko) 반도체 장치 제조방법
KR890001197A (ko) 반도체 장치 제조방법
KR980005890A (ko) 고전압 반도체 소자 및 그의 제조방법

Legal Events

Date Code Title Description
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid