KR880005746A - 반도체집적회로 - Google Patents

반도체집적회로 Download PDF

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Publication number
KR880005746A
KR880005746A KR870010908A KR870010908A KR880005746A KR 880005746 A KR880005746 A KR 880005746A KR 870010908 A KR870010908 A KR 870010908A KR 870010908 A KR870010908 A KR 870010908A KR 880005746 A KR880005746 A KR 880005746A
Authority
KR
South Korea
Prior art keywords
integrated circuit
semiconductor integrated
input signal
capacitor means
generate
Prior art date
Application number
KR870010908A
Other languages
English (en)
Other versions
KR970000560B1 (ko
Inventor
나카이 히로토
히로시 이와하시
마사미치 아사노
시게루 구마가이
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
다케다이 마사다카
도시바 마이콤 엔지니어링 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 아오이 죠이치, 가부시키가이샤 도시바, 다케다이 마사다카, 도시바 마이콤 엔지니어링 가부시끼가이샤 filed Critical 아오이 죠이치
Publication of KR880005746A publication Critical patent/KR880005746A/ko
Application granted granted Critical
Publication of KR970000560B1 publication Critical patent/KR970000560B1/ko

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/26—Time-delay networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H03K5/1252—Suppression or limitation of noise or interference
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00195—Layout of the delay element using FET's

Abstract

내용 없음

Description

반도체집적회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4도는 본 발명의 제1실시에 따라 반도체집적회로에 적용시킬 수 있는 지연회로를 나타낸 도면.
제5도는 제4도에 도시된 지연회로의 신호파형을 나타낸 도면.
제6도는 본 발명의 제2실시예에 따른 반도체집적회로를 나타낸 도면.

Claims (1)

  1. 캐패시터수단을 구비하고 있으면서, 입력신호가 소정의 방향으로 변화하는 경우에는 그 입력신호에 기초해서 상기 캐패시터수단을 충전시키거나 방전시키므로써 그 입력신호에 대하여 소정시간만큼 지연된 출력신호를 발생시키도록 되어 있는 지연수단과; 상기 입력신호가 상기 소정의 방향과 반대방향으로 변화하는 경우에는 상기 캐패시터수단을 충전시키거나 방전시켜서 출력신호를 발생시키도록 되어 있는 제어수단을 포함하여 구성된 것을 특징으로 하는 반도체집적회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019870010908A 1986-10-01 1987-09-30 반도체집적회로 KR970000560B1 (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP23344686 1986-10-01
JP61-233446 1986-10-01
JP233446 1986-10-01
JP62-246763 1987-09-30
JP62246763A JP2557411B2 (ja) 1986-10-01 1987-09-30 半導体集積回路

Publications (2)

Publication Number Publication Date
KR880005746A true KR880005746A (ko) 1988-06-30
KR970000560B1 KR970000560B1 (ko) 1997-01-13

Family

ID=16955170

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019870010908A KR970000560B1 (ko) 1986-10-01 1987-09-30 반도체집적회로

Country Status (3)

Country Link
US (1) US5055706A (ko)
JP (1) JP2557411B2 (ko)
KR (1) KR970000560B1 (ko)

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US5479132A (en) * 1994-06-06 1995-12-26 Ramtron International Corporation Noise and glitch suppressing filter with feedback
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US5764090A (en) * 1996-08-26 1998-06-09 United Microelectronics Corporation Write-control circuit for high-speed static random-access-memory (SRAM) devices
US5896054A (en) * 1996-12-05 1999-04-20 Motorola, Inc. Clock driver
JP3338758B2 (ja) * 1997-02-06 2002-10-28 日本電気株式会社 遅延回路
JPH10303709A (ja) * 1997-04-25 1998-11-13 Advantest Corp パルス幅整形回路
JP3926011B2 (ja) 1997-12-24 2007-06-06 株式会社ルネサステクノロジ 半導体装置の設計方法
US6573772B1 (en) * 2000-06-30 2003-06-03 Intel Corporation Method and apparatus for locking self-timed pulsed clock
JP3866594B2 (ja) * 2002-03-15 2007-01-10 Ｎｅｃエレクトロニクス株式会社 遅延回路と半導体記憶装置及び半導体記憶装置の制御方法
US20070106375A1 (en) * 2005-11-07 2007-05-10 Carlos Vonderwalde Bifurcated stent assembly
JP6297575B2 (ja) * 2013-08-19 2018-03-20 国立研究開発法人科学技術振興機構 再構成可能な遅延回路、並びにその遅延回路を用いた遅延モニタ回路、ばらつき補正回路、ばらつき測定方法及びばらつき補正方法

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Also Published As

Publication number Publication date
KR970000560B1 (ko) 1997-01-13
US5055706A (en) 1991-10-08
JP2557411B2 (ja) 1996-11-27
JPS63226111A (ja) 1988-09-20

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