KR900002552A - 출력회로 - Google Patents
출력회로 Download PDFInfo
- Publication number
- KR900002552A KR900002552A KR1019890010199A KR890010199A KR900002552A KR 900002552 A KR900002552 A KR 900002552A KR 1019890010199 A KR1019890010199 A KR 1019890010199A KR 890010199 A KR890010199 A KR 890010199A KR 900002552 A KR900002552 A KR 900002552A
- Authority
- KR
- South Korea
- Prior art keywords
- transistor
- potential
- control signal
- gate
- output terminal
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/02—Shaping pulses by amplifying
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
- H03K19/09448—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET in combination with bipolar transistors [BIMOS]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
- H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
- H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
- H03K5/134—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices with field-effect transistors
Abstract
내용 없음.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 1실시예의 따른 회로구성도.
Claims (1)
- 드레인·소오스가 제1전위와 출력단자간에 접속된 제1MOS 트랜지스터(8)와, 상기 제1전위와 상기 제1MOS 트랜지스터(8)의 게이트간에 접속된 레벨시프트용 트랜지스터(1), 드레인·소오스가 상기 레벨시프트용 트랜지스터(1)의 제어단자와 제2전위간에 접속되고 게이트에 제1제어신호가 공급되는 제2MOS 트랜지스터(3), 상기 제1MOS 트랜지스터(8)의 게이트와 상기 출력단자에 접속된 정전압소자(10), 드레인·소오스가 상기 정전압소자(10)를 매개로 상기 출력단자와 상기 제2전위간에 접속되고 게이트에 상기 제1제어신호와는 역위상인 제2제어신호가 공급되는 제3MOS 트랜지스터(7), 상기 제2제어신호를 소정시간 지연시켜서 제3제어신호를 출력하는 신호지연제어회로(12) 및, 드레인·소오스가 상기 출력단자와 상기 제2전위간에 접속되고 게이트에 상기 제3제어신호가 공급되는 제4MOS 트랜지스터(11)를 구비하여 구성되고, 상기 제3MOS 트랜지스터(7)의 소자치수가 상기 제4MOS 트랜지스터(11)의 소자치수보다도 작게 설정된 것을 특징으로 하는 출력회로.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63179682A JPH0229115A (ja) | 1988-07-19 | 1988-07-19 | 出力回路 |
JP88-179682 | 1988-07-19 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR900002552A true KR900002552A (ko) | 1990-02-28 |
KR920005354B1 KR920005354B1 (ko) | 1992-07-02 |
Family
ID=16070029
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019890010199A KR920005354B1 (ko) | 1988-07-19 | 1989-07-19 | 출력회로 |
Country Status (5)
Country | Link |
---|---|
US (1) | US4996449A (ko) |
EP (1) | EP0351820B1 (ko) |
JP (1) | JPH0229115A (ko) |
KR (1) | KR920005354B1 (ko) |
DE (1) | DE68915351T2 (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20170118683A (ko) * | 2015-02-25 | 2017-10-25 | 니폰 덴키 가라스 가부시키가이샤 | 유리 필름의 할단 방법 |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5015889A (en) * | 1989-02-23 | 1991-05-14 | Reay Robert L | Schottky enhanced CMOS output circuit |
JP2761136B2 (ja) * | 1991-10-14 | 1998-06-04 | シャープ株式会社 | 出力回路 |
US5233237A (en) * | 1991-12-06 | 1993-08-03 | National Semiconductor Corporation | Bicmos output buffer noise reduction circuit |
US5258665A (en) * | 1992-05-12 | 1993-11-02 | National Semiconductor Corporation | AC Miller-Killer circuit for L→Z transitions |
US5543746A (en) * | 1993-06-08 | 1996-08-06 | National Semiconductor Corp. | Programmable CMOS current source having positive temperature coefficient |
KR100302890B1 (ko) * | 1993-06-08 | 2001-11-22 | 클라크 3세 존 엠. | 프로그램가능한cmos버스및전송라인드라이버 |
WO1994029962A1 (en) * | 1993-06-08 | 1994-12-22 | National Semiconductor Corporation | Cmos btl compatible bus and transmission line driver |
US5557223A (en) * | 1993-06-08 | 1996-09-17 | National Semiconductor Corporation | CMOS bus and transmission line driver having compensated edge rate control |
US5539341A (en) * | 1993-06-08 | 1996-07-23 | National Semiconductor Corporation | CMOS bus and transmission line driver having programmable edge rate control |
US5483184A (en) * | 1993-06-08 | 1996-01-09 | National Semiconductor Corporation | Programmable CMOS bus and transmission line receiver |
US5811990A (en) | 1993-10-15 | 1998-09-22 | Micron Technology, Inc. | Voltage pump and a level translator circuit |
US5818260A (en) * | 1996-04-24 | 1998-10-06 | National Semiconductor Corporation | Transmission line driver having controllable rise and fall times with variable output low and minimal on/off delay |
FR2763735B1 (fr) * | 1997-05-22 | 1999-08-13 | Sgs Thomson Microelectronics | Etage de sortie de puissance pour la commande de cellules d'ecran a plasma |
JP2000307406A (ja) * | 1999-04-22 | 2000-11-02 | Denso Corp | 負荷駆動回路 |
FR2849536B1 (fr) * | 2002-12-27 | 2007-02-23 | St Microelectronics Sa | Circuit d'interface de fourniture de tension |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4339676A (en) * | 1979-08-13 | 1982-07-13 | Texas Instruments Incorporated | Logic circuit having a selectable output mode |
US4263534A (en) * | 1980-01-08 | 1981-04-21 | International Business Machines Corporation | Single sided sustain voltage generator |
US4425517A (en) * | 1981-03-31 | 1984-01-10 | Rca Corporation | Fail soft tri-state logic circuit |
US4347447A (en) * | 1981-04-16 | 1982-08-31 | Mostek Corporation | Current limiting MOS transistor driver circuit |
JPS57181231A (en) * | 1981-05-01 | 1982-11-08 | Oki Electric Ind Co Ltd | Semiconductor integrated circuit |
JPS60198620A (ja) * | 1984-03-21 | 1985-10-08 | Sharp Corp | Lsi化したタイミング発生回路 |
US4612466A (en) * | 1984-08-31 | 1986-09-16 | Rca Corporation | High-speed output driver |
US4638187A (en) * | 1985-10-01 | 1987-01-20 | Vtc Incorporated | CMOS output buffer providing high drive current with minimum output signal distortion |
IT1204808B (it) * | 1986-02-18 | 1989-03-10 | Sgs Microelettronica Spa | Circuito di reset all'accensione per reti logiche in tecnologia mos,particolarmente per periferiche di microprocessori |
JPS62220026A (ja) * | 1986-03-20 | 1987-09-28 | Toshiba Corp | 出力バツフア回路 |
JPS62230221A (ja) * | 1986-03-31 | 1987-10-08 | Toshiba Corp | バツフア回路 |
EP0264614A1 (en) * | 1986-09-11 | 1988-04-27 | Matsushita Electric Industrial Co., Ltd. | Mos fet drive circuit providing protection against transient voltage breakdown |
JPS63234622A (ja) * | 1987-03-23 | 1988-09-29 | Toshiba Corp | デ−タ出力回路 |
JPH01117518A (ja) * | 1987-10-30 | 1989-05-10 | Toshiba Corp | 半導体装置の出力回路 |
JPH0693615B2 (ja) * | 1988-05-16 | 1994-11-16 | 株式会社東芝 | ドライバ回路 |
-
1988
- 1988-07-19 JP JP63179682A patent/JPH0229115A/ja active Granted
-
1989
- 1989-07-17 US US07/380,335 patent/US4996449A/en not_active Expired - Lifetime
- 1989-07-19 DE DE68915351T patent/DE68915351T2/de not_active Expired - Fee Related
- 1989-07-19 EP EP89113244A patent/EP0351820B1/en not_active Expired - Lifetime
- 1989-07-19 KR KR1019890010199A patent/KR920005354B1/ko not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20170118683A (ko) * | 2015-02-25 | 2017-10-25 | 니폰 덴키 가라스 가부시키가이샤 | 유리 필름의 할단 방법 |
Also Published As
Publication number | Publication date |
---|---|
JPH0563962B2 (ko) | 1993-09-13 |
US4996449A (en) | 1991-02-26 |
EP0351820B1 (en) | 1994-05-18 |
DE68915351T2 (de) | 1994-09-29 |
KR920005354B1 (ko) | 1992-07-02 |
EP0351820A2 (en) | 1990-01-24 |
EP0351820A3 (en) | 1990-05-30 |
DE68915351D1 (de) | 1994-06-23 |
JPH0229115A (ja) | 1990-01-31 |
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Legal Events
Date | Code | Title | Description |
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A201 | Request for examination | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20030701 Year of fee payment: 12 |
|
LAPS | Lapse due to unpaid annual fee |