KR870003561A - 반도체장치 - Google Patents

반도체장치 Download PDF

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Publication number
KR870003561A
KR870003561A KR1019860008071A KR860008071A KR870003561A KR 870003561 A KR870003561 A KR 870003561A KR 1019860008071 A KR1019860008071 A KR 1019860008071A KR 860008071 A KR860008071 A KR 860008071A KR 870003561 A KR870003561 A KR 870003561A
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KR
South Korea
Prior art keywords
conductive layer
layer
thin film
semiconductor device
polysilicon
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KR1019860008071A
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English (en)
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KR900002084B1 (ko
Inventor
히로시 모모세
히데키 시바타
히로시 노자와
Original Assignee
와타리 스기이키로
가부시키가이샤 도시바
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Application filed by 와타리 스기이키로, 가부시키가이샤 도시바 filed Critical 와타리 스기이키로
Publication of KR870003561A publication Critical patent/KR870003561A/ko
Application granted granted Critical
Publication of KR900002084B1 publication Critical patent/KR900002084B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

내용 없음

Description

반도체장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 2 도는 제 1 도의 하부도전층이 얇은 경우에 접합영역에서 발생되는 결함을 나타낸 단면도.
제 3 도는 본 발명의 반도체장치에 따른 일실시예를 나타낸 단면도이다.
* 도면의 주요부분에 대한 부호의 설명
1,11 : 반도체기판 2,12 : 절연막
3,3A : 제 1 도전층 4,15 : 절연층
5,5A : 제 2 도전층 6 : 접합부
13 : 다결정실리콘도전층 14 : 박막 제 1 도전층
16 : Al도선층

Claims (5)

  1. 반도체기판(11)과, 상기 반도체기판(11)상에 형성된 제 1 절연막(12), 상기 제1절연막(12)상에 형성된 다결정실리콘도전층(13)과 박막 제1도전층(14), 상기 다결정실리콘도전층(13)과 박막 제1도전층(14)에 도달되게 접합영역에 형성된 접합구, 상기 제1절연막(12)과 다결정실리콘도전층(13) 및 박막 제1도전층(14)상에 형성된 제 2 절연층(15) 및, 상기 다결정실리콘도전층(13)과 박막 제1도전층(14) 및 절연층(15)상에 형성된 도선층(16)을 구비하면서 접합영역에서 상기 제1절연막(12)상에 다결정실리콘도전층(13)이 형성되고, 상기 제1절연막(12)과 다결정실리콘도전층(13)상에 박막 제1도전층(14)이 형성된 것을 특징으로 하는 반도체 장치.
  2. 제 1 항에 있어서, 다결정실리콘도전층(13)과 박막 제1도전층(14) 및 도선층(16)이 실리콘과 다결정실리콘, 비정질실리콘, 단결정실리콘, 텅스텐, 몰리브덴, 몰리브덴실리사이드 및 다결정실리콘/MOSi2의 2중층구조중 선택된 재료로 구성된 것을 특징으로 하는 반도체장치.
  3. 제2항에 있어서, 다결정실리콘도전층(13)이 박막 제1도전층(14)과 도선층(16)에 대해서 양호한 저항성접합 특성을 갖는 재료로 구성된 것을 특징으로 하는 반도체장치.
  4. 제 2 항에 있어서, 박막제1도전층(14)이 도선층(16)과 양호한 저항성접합특성을 갖는 재료로 구성된것을 특징으로 하는 반도체장치.
  5. 제 1 항에 있어서, 다결정실리콘도전층(13)과 박막제1도전층(14) 및 도선층(16)중 적어도 2개가 같은 형의 불순물이 주입된 실리콘층으로 구성된 것을 특징으로 하는 반도체장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019860008071A 1985-09-30 1986-09-26 반도체장치 KR900002084B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP60-216594 1985-09-30
JP60216594A JPS6276653A (ja) 1985-09-30 1985-09-30 半導体集積回路

Publications (2)

Publication Number Publication Date
KR870003561A true KR870003561A (ko) 1987-04-18
KR900002084B1 KR900002084B1 (ko) 1990-03-31

Family

ID=16690865

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019860008071A KR900002084B1 (ko) 1985-09-30 1986-09-26 반도체장치

Country Status (5)

Country Link
US (1) US4754318A (ko)
EP (1) EP0220517B1 (ko)
JP (1) JPS6276653A (ko)
KR (1) KR900002084B1 (ko)
DE (1) DE3676942D1 (ko)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63268258A (ja) * 1987-04-24 1988-11-04 Nec Corp 半導体装置
JPH0680733B2 (ja) * 1987-11-12 1994-10-12 株式会社東芝 半導体装置の配線接続部
JPH02105519A (ja) * 1988-10-14 1990-04-18 Nec Corp 半導体集積回路の製造方法
JPH04212426A (ja) * 1990-06-21 1992-08-04 Mitsubishi Electric Corp 半導体装置およびその製造方法
JPH0465167A (ja) * 1990-07-05 1992-03-02 Mitsubishi Electric Corp 半導体装置
US5243219A (en) * 1990-07-05 1993-09-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having impurity diffusion region formed in substrate beneath interlayer contact hole
KR940000504B1 (ko) * 1991-03-20 1994-01-21 삼성전자 주식회사 반도체장치의 층간콘택구조 및 그 제조방법
JPH05267621A (ja) * 1991-12-27 1993-10-15 Nippon Steel Corp 半導体装置のコンタクト構造及びその製造方法
JP2944840B2 (ja) * 1993-03-12 1999-09-06 株式会社日立製作所 電力用半導体装置
KR0138308B1 (ko) 1994-12-14 1998-06-01 김광호 층간접촉구조 및 그 방법
KR0161379B1 (ko) * 1994-12-23 1999-02-01 윤종용 반도체 소자의 다층배선 및 그 제조방법
WO1996027901A1 (en) 1995-03-07 1996-09-12 Micron Technology, Inc. Improved semiconductor contacts to thin conductive layers
US5966592A (en) * 1995-11-21 1999-10-12 Tessera, Inc. Structure and method for making a compliant lead for a microelectronic device
TW409194B (en) 1995-11-28 2000-10-21 Sharp Kk Active matrix substrate and liquid crystal display apparatus and method for producing the same
JPH08236627A (ja) * 1995-12-28 1996-09-13 Nippon Precision Circuits Kk 半導体装置の製造方法
US6331680B1 (en) * 1996-08-07 2001-12-18 Visteon Global Technologies, Inc. Multilayer electrical interconnection device and method of making same
TW375805B (en) * 1997-04-14 1999-12-01 Nanya Technology Co Ltd Process for preparing contact window in the semiconductor device and its structure

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Publication number Priority date Publication date Assignee Title
NL7302767A (ko) * 1973-02-28 1974-08-30
JPS5810855B2 (ja) * 1975-01-29 1983-02-28 株式会社日立製作所 タソウハイセンコウゾウノセイホウ
US4110776A (en) * 1976-09-27 1978-08-29 Texas Instruments Incorporated Semiconductor integrated circuit with implanted resistor element in polycrystalline silicon layer
US4172004A (en) * 1977-10-20 1979-10-23 International Business Machines Corporation Method for forming dense dry etched multi-level metallurgy with non-overlapped vias
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JPS58215055A (ja) * 1982-06-08 1983-12-14 Nec Corp 半導体集積回路装置
GB2137808A (en) * 1983-04-06 1984-10-10 Plessey Co Plc Integrated circuit processing method
US4507852A (en) * 1983-09-12 1985-04-02 Rockwell International Corporation Method for making a reliable ohmic contact between two layers of integrated circuit metallizations
JPS60136337A (ja) * 1983-12-22 1985-07-19 モノリシツク・メモリ−ズ・インコ−ポレイテツド ２重層処理においてヒロツク抑制層を形成する方法及びその構造物
JPS60138940A (ja) * 1983-12-27 1985-07-23 Toshiba Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
EP0220517A2 (en) 1987-05-06
EP0220517B1 (en) 1991-01-16
US4754318A (en) 1988-06-28
EP0220517A3 (en) 1987-09-02
KR900002084B1 (ko) 1990-03-31
DE3676942D1 (de) 1991-02-21
JPS6276653A (ja) 1987-04-08

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