KR860001378A - 모놀리딕 세미-커스텀 lsi - Google Patents

모놀리딕 세미-커스텀 lsi Download PDF

Info

Publication number
KR860001378A
KR860001378A KR1019850004512A KR850004512A KR860001378A KR 860001378 A KR860001378 A KR 860001378A KR 1019850004512 A KR1019850004512 A KR 1019850004512A KR 850004512 A KR850004512 A KR 850004512A KR 860001378 A KR860001378 A KR 860001378A
Authority
KR
South Korea
Prior art keywords
microcells
custom lsi
bus controller
monolithic semi
various
Prior art date
Application number
KR1019850004512A
Other languages
English (en)
Other versions
KR900000177B1 (ko
Inventor
쯔네오(외 1) 기노시다
Original Assignee
사바 쇼오이찌
가부시끼가이샤 도오시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 사바 쇼오이찌, 가부시끼가이샤 도오시바 filed Critical 사바 쇼오이찌
Publication of KR860001378A publication Critical patent/KR860001378A/ko
Application granted granted Critical
Publication of KR900000177B1 publication Critical patent/KR900000177B1/ko

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/923—Active solid-state devices, e.g. transistors, solid-state diodes with means to optimize electrical conductor current carrying capacity, e.g. particular conductor aspect ratio

Abstract

내용 없음

Description

모놀로딕 세미-커미텀 LSI
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 종래의 개인용 컴퓨터 시스템의 블록 구성도.
제2도는 본 발명의 일실시예에 관계되는 시스템 LSI의 개략구성을 나타내는 평면도.
제3도는 제2도의 시스템 LSI를 개인용 컴퓨터의 시스템에 적용시킨 경우의 블록 구성도.
* 도면의 주요부분에 대한 부호의 설명
10, 80 : 마이크로 프로세서 11 : 수정발진기
12, 57 : 클럭발생회로 13, 61 : 버스콘트롤러
14, 62 : 인터럽트 콘트롤러 15, 63 : DMA콘트롤러
18, 60, 66 : CRT 콘트롤러 19, 67 : 플로피디스크콘트롤러
20, 70 : I/O칩 선택회로 21 : RAM
22 : 어드레스디코더 23 : ROM
24 : ROM디코더 25 : I/O포트디코더
26 : 타이밍과 디코더 27, 69 : 패리터회로
28, 71 : DMA페이지레지스터 29, 36 : 버퍼레지스터
41 : 반도체기판 42 : 마이크로셀
43, 44 : 본딩패드 45 : A1배선
46 : 보충회로 50 : 시스템 LSI
51 : 클럭버스 52 : 로컬버스
53 : 시스템버스 54 : 콘트롤버스
55 : 어드레스버스 55, 56 : 데이터버스
58 : WS논리회로 59 : 어드레스 래치
60 : 데이터버퍼 68 : 메모리 콘트롤러논리회로
72 : DMA어드레스래치 73 : 데이터버스 이네이블디코더
74 : 직렬/병렬변환기 75 : NMT 논리회로

Claims (5)

  1. 소정의 시스템이 구성 가능한 여러 종류의 독립된 LSI에 대응되는 1개층의 배선으로 이루어진 여러 종류의 마이크로셀(42)에 의해 구성되고 있는 모놀리틱 세미-커스텀 LSI에 있어서, 대응되는 상기 독립한 LSI의 주요회로와 동일 주요회로를 갖고 주요회로의 패턴 구성에다 상기 독립한 LSI패턴 배열을 적용하여 이루어지는 여러 종류의 마이크로셀(42), 상기 여러 종류의 마이크로셀(42)과 공통된 반도체기판에다 형성시켜 상기 여러 종류의 마이크로셀(42)의 기능을 보충하는 보충회로(46), 상기 여러 종류의 마이크로셀(42)사이, 상기 마이크로셀(42)과 보충회로(46)사이를 필요에 따라서 2개층의 배선으로 상호접속하는 수단(45)을 구비한 것을 특징으로 하는 모놀리딕 세미-커스텀 LSI.
  2. 제1항에 있어서, 수정 발진기(81)가 상기 모놀리딕 세미 커스팀 LSI외부에 부착된 것.
  3. 제1항에 있어서, 마이크로프로세서(80)가 상기 모놀리딕 세미 커스팀 LSI외부에 부착된 것.
  4. 제1항에 있어서, 상기 여러 종류의 마이크로셀(42)이 전부 CMOS로 구성된 것.
  5. 제1항에 있어서, 상기 여러 종류의 마이크로셀(42)의 하나가 버스콘트롤러(61)이고, 상기 버스 콘트롤러는 각종 제어신호용 풀업저항을 버스콘트롤러내에 설치된 것.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019850004512A 1984-07-02 1985-06-25 모놀로딕 세미-커미텀 lsi KR900000177B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP59136940A JPH0673363B2 (ja) 1984-07-02 1984-07-02 システムｌｓｉの設計方法
JP59-136940 1984-07-02

Publications (2)

Publication Number Publication Date
KR860001378A true KR860001378A (ko) 1986-02-26
KR900000177B1 KR900000177B1 (ko) 1990-01-23

Family

ID=15187090

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019850004512A KR900000177B1 (ko) 1984-07-02 1985-06-25 모놀로딕 세미-커미텀 lsi

Country Status (4)

Country Link
US (1) US4839820A (ko)
JP (1) JPH0673363B2 (ko)
KR (1) KR900000177B1 (ko)
DE (1) DE3523621C2 (ko)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2214334B (en) * 1988-01-05 1992-05-06 Texas Instruments Ltd Integrated circuit
IT1218104B (it) * 1986-06-27 1990-04-12 Sgs Microelettronica Spa Metodo di progettazione di microcalcolatori integrati e microcalcolatore integrato a struttura modulare ottenuto con il metodo suddetto
JPH01260275A (ja) * 1988-04-11 1989-10-17 Narasaki Sangyo Kk 農産物などの立体自動差圧予冷設備
US5124273A (en) * 1988-06-30 1992-06-23 Kabushiki Kaisha Toshiba Automatic wiring method for semiconductor integrated circuit devices
JP2539058B2 (ja) * 1989-03-30 1996-10-02 三菱電機株式会社 デ―タプロセッサ
JPH07111971B2 (ja) * 1989-10-11 1995-11-29 三菱電機株式会社 集積回路装置の製造方法
US5119158A (en) * 1989-11-21 1992-06-02 Nec Corporation Gate array semiconductor integrated circuit device
JPH0410624A (ja) * 1990-04-27 1992-01-14 Hitachi Ltd 半導体集積回路
JPH04256338A (ja) * 1991-02-08 1992-09-11 Nec Corp 集積回路の自動レイアウト方式
US5694328A (en) * 1992-08-06 1997-12-02 Matsushita Electronics Corporation Method for designing a large scale integrated (LSI) layout
JP3904244B2 (ja) * 1993-09-17 2007-04-11 株式会社ルネサステクノロジ シングル・チップ・データ処理装置
JP3272200B2 (ja) * 1994-07-15 2002-04-08 インターナショナル・ビジネス・マシーンズ・コーポレーション カスタマイザブル集積回路デバイス
US5860013A (en) * 1996-07-26 1999-01-12 Zilog, Inc. Flexible interrupt system for an integrated circuit
JP3777768B2 (ja) * 1997-12-26 2006-05-24 株式会社日立製作所 半導体集積回路装置およびセルライブラリを記憶した記憶媒体および半導体集積回路の設計方法
US6678645B1 (en) * 1999-10-28 2004-01-13 Advantest Corp. Method and apparatus for SoC design validation
JP3420195B2 (ja) * 2000-09-26 2003-06-23 エヌイーシーマイクロシステム株式会社 クロック配線の設計方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5591853A (en) * 1978-12-29 1980-07-11 Fujitsu Ltd Semiconductor device
US4479088A (en) * 1981-01-16 1984-10-23 Burroughs Corporation Wafer including test lead connected to ground for testing networks thereon
JPH0666366B2 (ja) * 1981-06-24 1994-08-24 株式会社日立製作所 半導体集積回路装置の製造方法
JPH077825B2 (ja) * 1981-08-13 1995-01-30 富士通株式会社 ゲートアレイの製造方法
JPS59119925A (ja) * 1982-12-27 1984-07-11 Toshiba Corp 論理回路
US4584653A (en) * 1983-03-22 1986-04-22 Fujitsu Limited Method for manufacturing a gate array integrated circuit device
EP0127100B1 (en) * 1983-05-24 1990-04-11 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device
US4612618A (en) * 1983-06-10 1986-09-16 Rca Corporation Hierarchical, computerized design of integrated circuits
US4577276A (en) * 1983-09-12 1986-03-18 At&T Bell Laboratories Placement of components on circuit substrates

Also Published As

Publication number Publication date
DE3523621C2 (de) 1995-11-02
KR900000177B1 (ko) 1990-01-23
US4839820A (en) 1989-06-13
JPH0673363B2 (ja) 1994-09-14
DE3523621A1 (de) 1986-01-23
JPS6115348A (ja) 1986-01-23

Similar Documents

Publication Publication Date Title
KR860001378A (ko) 모놀리딕 세미-커스텀 lsi
US6467004B1 (en) Pipelined semiconductor devices suitable for ultra large scale integration
US7109779B2 (en) Semiconductor integrated circuit and a burn-in method thereof
JPH0221145B2 (ko)
KR860002875A (ko) 반주문형 시스템 lsi
JPH03203363A (ja) 半導体装置
KR900008795B1 (ko) 반주문형 시스템 lsi
JPS59149033A (ja) 半導体集積回路装置
JP2737689B2 (ja) 半導体装置
JP2562406B2 (ja) 半導体装置
KR900008796B1 (ko) 반주문형 시스템 lsi
JPH01293647A (ja) 半導体装置
JP2527723B2 (ja) 半導体集積回路装置
JPH09148545A (ja) 半導体装置
JP2560813B2 (ja) 半導体集積回路
JPH0513582A (ja) 半導体装置の電源配線
JPH1041398A (ja) 半導体集積回路装置
JPS63161655A (ja) 半導体集積回路
JP2000138289A (ja) 半導体集積回路装置
JPS61190958A (ja) 半導体集積回路
JPS62107362A (ja) システム構成用ｌｓｉ
JP2564570B2 (ja) 半導体メモリ
JPH0514428B2 (ko)
JP2977138B2 (ja) 半導体装置
JPS60177650A (ja) 半導体装置およびその製造方法

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 19971222

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee