KR20220034051A - 주상 반도체 장치와, 그 제조 방법 - Google Patents

주상 반도체 장치와, 그 제조 방법 Download PDF

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KR20220034051A
KR20220034051A KR1020217042116A KR20217042116A KR20220034051A KR 20220034051 A KR20220034051 A KR 20220034051A KR 1020217042116 A KR1020217042116 A KR 1020217042116A KR 20217042116 A KR20217042116 A KR 20217042116A KR 20220034051 A KR20220034051 A KR 20220034051A
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impurity
semiconductor pillar
band
forming
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Korean (ko)
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후지오 마스오카
노조무 하라다
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유니산티스 일렉트로닉스 싱가포르 프라이빗 리미티드
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Publication of KR20220034051A publication Critical patent/KR20220034051A/ko
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H01L27/1104—
    • H01L29/66666—
    • H01L29/7827—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/025—Manufacture or treatment of FETs having insulated gates [IGFET] of vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/63—Vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/694—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials

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  • Semiconductor Memories (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1020217042116A 2019-07-11 2019-07-11 주상 반도체 장치와, 그 제조 방법 Pending KR20220034051A (ko)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2019/027541 WO2021005789A1 (ja) 2019-07-11 2019-07-11 柱状半導体装置と、その製造方法

Publications (1)

Publication Number Publication Date
KR20220034051A true KR20220034051A (ko) 2022-03-17

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Family Applications (2)

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KR1020217042116A Pending KR20220034051A (ko) 2019-07-11 2019-07-11 주상 반도체 장치와, 그 제조 방법
KR1020217042121A Active KR102689607B1 (ko) 2019-07-11 2020-03-19 주상 반도체 장치와, 그 제조 방법

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KR1020217042121A Active KR102689607B1 (ko) 2019-07-11 2020-03-19 주상 반도체 장치와, 그 제조 방법

Country Status (6)

Country Link
US (2) US12127385B2 (https=)
JP (2) JP7369471B2 (https=)
KR (2) KR20220034051A (https=)
CN (2) CN114127916A (https=)
TW (2) TWI742750B (https=)
WO (2) WO2021005789A1 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022234655A1 (ja) 2021-05-07 2022-11-10 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 柱状半導体の製造方法
KR102784170B1 (ko) * 2021-09-06 2025-03-19 유니산티스 일렉트로닉스 싱가포르 프라이빗 리미티드 반도체 소자를 사용한 메모리 장치
JP2023128046A (ja) * 2022-03-02 2023-09-14 キオクシア株式会社 半導体装置およびその製造方法
WO2024116244A1 (ja) * 2022-11-28 2024-06-06 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド メモリ素子を有した半導体装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02188966A (ja) 1989-01-17 1990-07-25 Toshiba Corp Ｍｏｓ型半導体装置
US20100219483A1 (en) 2008-01-29 2010-09-02 Fujio Masuoka Semiconductor storage device
US8530960B2 (en) 2010-12-07 2013-09-10 Unisantis Electronics Singapore Pte. Ltd. Semiconductor device

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4077951B2 (ja) 1998-01-14 2008-04-23 株式会社ルネサステクノロジ 欠陥解析方法、記録媒体及び工程管理方法
JP2009177200A (ja) * 1998-05-01 2009-08-06 Sony Corp 半導体記憶装置
JP3148745B2 (ja) * 1999-08-20 2001-03-26 昭幸 木村 オープンショーケース用シャッタ装置
US7098502B2 (en) * 2003-11-10 2006-08-29 Freescale Semiconductor, Inc. Transistor having three electrically isolated electrodes and method of formation
US7241655B2 (en) * 2004-08-30 2007-07-10 Micron Technology, Inc. Method of fabricating a vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array
US7425491B2 (en) * 2006-04-04 2008-09-16 Micron Technology, Inc. Nanowire transistor with surrounding gate
WO2009096001A1 (ja) * 2008-01-29 2009-08-06 Unisantis Electronics (Japan) Ltd. 半導体記憶装置およびメモリ混載半導体装置、並びにそれらの製造方法
US8598650B2 (en) * 2008-01-29 2013-12-03 Unisantis Electronics Singapore Pte Ltd. Semiconductor device and production method therefor
WO2009095999A1 (ja) * 2008-01-29 2009-08-06 Unisantis Electronics (Japan) Ltd. 半導体記憶装置
WO2009095998A1 (ja) * 2008-01-29 2009-08-06 Unisantis Electronics (Japan) Ltd. 半導体記憶装置
WO2009095997A1 (ja) * 2008-01-29 2009-08-06 Unisantis Electronics (Japan) Ltd. 半導体装置およびその製造方法
KR100949265B1 (ko) * 2008-04-01 2010-03-25 주식회사 하이닉스반도체 반도체 소자 제조 방법
WO2009153880A1 (ja) * 2008-06-20 2009-12-23 日本ユニサンティスエレクトロニクス株式会社 半導体記憶装置
JP2013069770A (ja) * 2011-09-21 2013-04-18 Elpida Memory Inc 半導体装置及びその製造方法
KR20140009509A (ko) * 2012-05-18 2014-01-22 유니산티스 일렉트로닉스 싱가포르 프라이빗 리미티드 반도체 장치의 제조 방법 및 반도체 장치
JP5973665B2 (ja) * 2013-06-13 2016-08-23 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． Ｓｇｔを有する半導体装置とその製造方法
WO2015022744A1 (ja) * 2013-08-15 2015-02-19 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド Ｓｇｔを有する半導体装置の製造方法
JP2015061038A (ja) * 2013-09-20 2015-03-30 マイクロン テクノロジー， インク． 半導体装置
KR20150101726A (ko) * 2014-02-27 2015-09-04 에스케이하이닉스 주식회사 터널링 트랜지스터, 그를 포함하는 저항 변화 메모리 장치 및 그 제조방법
WO2015162682A1 (ja) * 2014-04-22 2015-10-29 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体装置
KR20150139255A (ko) * 2014-06-03 2015-12-11 에스케이하이닉스 주식회사 반도체 장치 및 그 제조방법
JP6297430B2 (ja) * 2014-06-30 2018-03-20 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP5692884B1 (ja) * 2014-08-19 2015-04-01 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. Ｓｇｔを有する半導体装置の製造方法
JP6104477B2 (ja) * 2015-04-06 2017-03-29 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． 柱状半導体メモリ装置と、その製造方法
JP6378826B2 (ja) 2015-04-06 2018-08-22 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． Ｓｇｔを有する柱状半導体装置と、その製造方法
KR20180095836A (ko) * 2015-12-18 2018-08-28 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 상기 반도체 장치를 포함한 표시 장치
US9530863B1 (en) * 2016-04-13 2016-12-27 Globalfoundries Inc. Methods of forming vertical transistor devices with self-aligned replacement gate structures
US10312229B2 (en) * 2016-10-28 2019-06-04 Synopsys, Inc. Memory cells including vertical nanowire transistors
JP6850659B2 (ja) * 2017-03-31 2021-03-31 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US10236379B2 (en) * 2017-05-12 2019-03-19 Globalfoundries Inc. Vertical FET with self-aligned source/drain regions and gate length based on channel epitaxial growth process
JP2019009382A (ja) * 2017-06-28 2019-01-17 東芝メモリ株式会社 半導体装置
US10388766B2 (en) * 2017-10-23 2019-08-20 International Business Machines Corporation Vertical transport FET (VFET) with dual top spacer
US10319833B1 (en) * 2017-12-04 2019-06-11 International Business Machines Corporation Vertical transport field-effect transistor including air-gap top spacer
US10777658B2 (en) * 2018-04-17 2020-09-15 International Business Machines Corporation Method and structure of fabricating I-shaped silicon vertical field-effect transistors
US10439044B1 (en) * 2018-04-17 2019-10-08 International Business Machines Corporation Method and structure of fabricating I-shaped silicon germanium vertical field-effect transistors

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02188966A (ja) 1989-01-17 1990-07-25 Toshiba Corp Ｍｏｓ型半導体装置
US20100219483A1 (en) 2008-01-29 2010-09-02 Fujio Masuoka Semiconductor storage device
US8530960B2 (en) 2010-12-07 2013-09-10 Unisantis Electronics Singapore Pte. Ltd. Semiconductor device

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
A. Raley, S. Thibaut, N. Mohanty, K. Subhadeep, S. Nakamura, et al. : "Self-aligned quadruple patterning integration using spacer on spacer pitch splitting at the resist level for sub-32nm pitch applications" Proc. Of SPIE Vol.9782, 2016
C. Y. Ting, V. J. Vivalda, and H. G. Schaefer : "Study of planarized sputter-deposited SiO2", J. Vac. Sci. Technol. 15(3), p.p.1105 - 1112, May/June (1978)
Hiroshi Takato, Kazumasa Sunouchi, Naoko Okabe, Akihiro Nitayama, Katsuhiko Hieda, Fumio Horiguchi, and Fujio Masuoka : IEEE Transaction on Electron Devices, Vol.38, No.3, pp.573 - 578 (1991)

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US12127386B2 (en) 2024-10-22
KR102689607B1 (ko) 2024-07-29
WO2021005842A1 (ja) 2021-01-14
US20220130842A1 (en) 2022-04-28
TW202121655A (zh) 2021-06-01
US12127385B2 (en) 2024-10-22
CN114127916A (zh) 2022-03-01
JPWO2021005842A1 (https=) 2021-01-14
WO2021005789A8 (ja) 2021-06-10
CN114127917A (zh) 2022-03-01
TWI742750B (zh) 2021-10-11
US20220139928A1 (en) 2022-05-05
TW202121654A (zh) 2021-06-01
JP7357387B2 (ja) 2023-10-06
KR20220012325A (ko) 2022-02-03
JPWO2021005789A1 (https=) 2021-01-14
TWI750729B (zh) 2021-12-21
WO2021005789A1 (ja) 2021-01-14
JP7369471B2 (ja) 2023-10-26

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