KR20140105394A - 반도체 칩 및 반도체 장치 - Google Patents

반도체 칩 및 반도체 장치 Download PDF

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Publication number
KR20140105394A
KR20140105394A KR1020140019303A KR20140019303A KR20140105394A KR 20140105394 A KR20140105394 A KR 20140105394A KR 1020140019303 A KR1020140019303 A KR 1020140019303A KR 20140019303 A KR20140019303 A KR 20140019303A KR 20140105394 A KR20140105394 A KR 20140105394A
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KR
South Korea
Prior art keywords
substrate
pad
pads
input
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR1020140019303A
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English (en)
Korean (ko)
Inventor
다까시 아베마쯔
다까후미 베쯔이
아쯔시 구로다
Original Assignee
르네사스 일렉트로닉스 가부시키가이샤
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Application filed by 르네사스 일렉트로닉스 가부시키가이샤 filed Critical 르네사스 일렉트로닉스 가부시키가이샤
Publication of KR20140105394A publication Critical patent/KR20140105394A/ko
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H10W70/687—Shapes or dispositions thereof comprising multiple insulating layers characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/12—Containers or parts thereof characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/271—Configurations of stacked chips the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
KR1020140019303A 2013-02-22 2014-02-19 반도체 칩 및 반도체 장치 Ceased KR20140105394A (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2013033097 2013-02-22
JPJP-P-2013-033097 2013-02-22
JP2013126533A JP6118652B2 (ja) 2013-02-22 2013-06-17 半導体チップ及び半導体装置
JPJP-P-2013-126533 2013-06-17

Publications (1)

Publication Number Publication Date
KR20140105394A true KR20140105394A (ko) 2014-09-01

Family

ID=51346595

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020140019303A Ceased KR20140105394A (ko) 2013-02-22 2014-02-19 반도체 칩 및 반도체 장치

Country Status (4)

Country Link
US (2) US20140239493A1 (https=)
JP (1) JP6118652B2 (https=)
KR (1) KR20140105394A (https=)
CN (2) CN203746832U (https=)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6118652B2 (ja) * 2013-02-22 2017-04-19 ルネサスエレクトロニクス株式会社 半導体チップ及び半導体装置
JP6342221B2 (ja) 2014-06-02 2018-06-13 ルネサスエレクトロニクス株式会社 半導体装置
WO2016063459A1 (ja) * 2014-10-24 2016-04-28 株式会社ソシオネクスト 半導体集積回路装置
US9929095B2 (en) 2014-11-06 2018-03-27 Qualcomm Incorporated IO power bus mesh structure design
KR102264548B1 (ko) 2014-11-21 2021-06-16 삼성전자주식회사 반도체 패키지 및 그 제조 방법
WO2020079830A1 (ja) * 2018-10-19 2020-04-23 株式会社ソシオネクスト 半導体チップ
US20200335463A1 (en) * 2019-04-22 2020-10-22 Mikro Mesa Technology Co., Ltd. Electrical binding structure and method of forming the same
CN114203681A (zh) * 2021-12-08 2022-03-18 通富微电子股份有限公司 防止热压焊空洞形成的基板及多层堆叠存储器

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US5028986A (en) * 1987-12-28 1991-07-02 Hitachi, Ltd. Semiconductor device and semiconductor module with a plurality of stacked semiconductor devices
US5796171A (en) * 1996-06-07 1998-08-18 Lsi Logic Corporation Progressive staggered bonding pads
JP2781787B2 (ja) * 1996-08-29 1998-07-30 日本電気アイシーマイコンシステム株式会社 半導体チップのボンディングパッド配置構成及びその最適化方法
JPH10173087A (ja) 1996-12-09 1998-06-26 Hitachi Ltd 半導体集積回路装置
US6031258A (en) * 1998-03-06 2000-02-29 S3 Incorporated High DC current stagger power/ground pad
JP3407025B2 (ja) * 2000-06-08 2003-05-19 Ｎｅｃエレクトロニクス株式会社 半導体装置及びその製造方法
US6404043B1 (en) * 2000-06-21 2002-06-11 Dense-Pac Microsystems, Inc. Panel stacking of BGA devices to form three-dimensional modules
JP2002270779A (ja) * 2001-03-14 2002-09-20 Kawasaki Microelectronics Kk 半導体装置
JP2002280453A (ja) * 2001-03-19 2002-09-27 Mitsubishi Electric Corp 半導体集積回路
US6977440B2 (en) * 2001-10-09 2005-12-20 Tessera, Inc. Stacked packages
JP2004095923A (ja) * 2002-09-02 2004-03-25 Murata Mfg Co Ltd 実装基板およびこの実装基板を用いた電子デバイス
JP3986989B2 (ja) * 2003-03-27 2007-10-03 松下電器産業株式会社 半導体装置
US8574959B2 (en) * 2003-11-10 2013-11-05 Stats Chippac, Ltd. Semiconductor device and method of forming bump-on-lead interconnection
JP2005294406A (ja) * 2004-03-31 2005-10-20 Nec Electronics Corp 半導体集積回路装置および半導体集積回路装置の配線方法
CN100474576C (zh) * 2004-07-26 2009-04-01 株式会社理技独设计系统 半导体装置
JP2006237459A (ja) * 2005-02-28 2006-09-07 Matsushita Electric Ind Co Ltd 配線基板およびそれを用いた半導体装置
US8841779B2 (en) * 2005-03-25 2014-09-23 Stats Chippac, Ltd. Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate
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JP2009164195A (ja) * 2007-12-28 2009-07-23 Panasonic Corp 半導体チップ
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JP5503466B2 (ja) * 2010-08-31 2014-05-28 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
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JP5727288B2 (ja) * 2011-04-28 2015-06-03 ルネサスエレクトロニクス株式会社 半導体装置、半導体装置の設計方法、半導体装置設計装置、及びプログラム
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KR20140143567A (ko) * 2013-06-07 2014-12-17 삼성전기주식회사 반도체 패키지 기판 및 반도체 패키지 기판 제조 방법

Also Published As

Publication number Publication date
US9190378B2 (en) 2015-11-17
CN203746832U (zh) 2014-07-30
US20140284818A1 (en) 2014-09-25
JP2014187343A (ja) 2014-10-02
JP6118652B2 (ja) 2017-04-19
CN104009012A (zh) 2014-08-27
CN104009012B (zh) 2018-04-13
US20140239493A1 (en) 2014-08-28

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