CN117558703A - 电子封装件 - Google Patents

电子封装件 Download PDF

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Publication number
CN117558703A
CN117558703A CN202210967252.6A CN202210967252A CN117558703A CN 117558703 A CN117558703 A CN 117558703A CN 202210967252 A CN202210967252 A CN 202210967252A CN 117558703 A CN117558703 A CN 117558703A
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Prior art keywords
pad
wire bonding
bonding pad
distance
bonding
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Inventor
林庆治
王汶鑫
谢志毅
王馨妤
黄怡倩
简秀芳
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Publication of CN117558703A publication Critical patent/CN117558703A/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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Abstract

一种电子封装件，包括于一表面上布设有多个打线垫的承载结构上设置一电子元件，且以多个焊线连接该电子元件的多个电极垫与该多个打线垫，并于该多个打线垫的相邻三者中，依据相距该电子元件的远近定义出长距的第一打线垫、中距的第二打线垫及短距的第三打线垫，故当封装层的流动胶材包覆该电子元件与多个焊线时，即使该第一至第三打线垫上的焊线受胶材冲击而产生偏位现象，该些焊线仍不会相互接触，避免发生短路问题。

Description

电子封装件
技术领域
本发明有关一种半导体装置，尤指一种打线封装形式的电子封装件。
背景技术
随着半导体制程技术的进步，更多电子元件整合于半导体芯片中，因而芯片上所设置的输入/输出连接端(I/O connections)数目渐多，同样地，承载半导体芯片用的封装基板上需密集地布设多个与所述输入/输出连接端电性连通的打线垫，作为半导体芯片的接点。
如图1所示的半导体封装件1，其于一封装基板10上承载一半导体芯片11，且该半导体芯片11的电极垫110通过多个焊线12电性连接该封装基板10的打线垫100，再形成封装胶体13于该封装基板10上，以包覆该半导体芯片11与焊线12，其中，于半导体封装件轻、薄、短、小的需求下，该半导体芯片11的电极垫110尺寸极小，因而需极小尺寸的焊线12及更小的打线垫100的间距进行打线制程，故于该封装基板10的表面上会呈现出布满打线垫100的高密度接点区及零星布设打线垫100的空旷区(如角落处)。
然而，于形成该封装胶体13的过程中，对应该空旷区中的该些焊线12容易受到该封装胶体13的流动胶材的冲击而产生焊线偏位(wire sweep)现象，故当该焊线12的偏位距离过大，将会造成相邻的焊线12相接触(如图1所示的连接处k)而发生短路，致使该半导体封装件1的品质及可靠度不佳。
因此，如何克服上述现有技术的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺陷，本发明提供一种电子封装件，包括：承载结构，其于一表面上布设有顶面呈对称形状的多个打线垫，以令该多个打线垫依其顶面的几何形状定义垫长与垫宽；电子元件，其设于该承载结构上，其中，于该多个打线垫的任三相邻者中，依据相距该电子元件的远近定义出长距的第一打线垫、中距的第二打线垫及短距的第三打线垫；以及多个焊线，其分别连接于该电子元件与各该多个打线垫之间。
前述的电子封装件中，该第一打线垫的中心点与该第二打线垫的中心点之间沿水平方向定义有第一间距，且该第一间距大于或等于该垫长。
前述的电子封装件中，该第二打线垫的中心点与该第三打线垫的中心点之间沿水平方向定义有第二间距，且该第二间距大于或等于该垫长。
前述的电子封装件中，该第二打线垫的边缘与该第三打线垫的边缘之间定义有一令一直径为两倍该垫宽的假想圆可调整至不会重叠于该第二与第三打线垫任一者上的第三间距。
前述的电子封装件中，该第一打线垫的边缘与该第二打线垫的边缘之间定义有一令一直径为1.5倍该垫宽的假想圆可调整至不会重叠于该第一与第二打线垫任一者上的第四间距。
前述的电子封装件中，该第三打线垫于相对该第二打线垫的另一侧间隔布设有另一相邻的第四打线垫，且该第三打线垫与该第四打线垫之间于垂直方向上的最小间距作为第五间距。例如，该第五间距为该垫宽的至少七倍。
前述的电子封装件中，还包括包覆该电子元件及该多个焊线的封装层。
前述的电子封装件中，该承载结构于相对该置晶区的另一表面上形成有多个导电元件。
由上可知，本发明的电子封装件中，主要通过将该多个打线垫的任三相邻者依据相距该电子元件的远近定义出长距的第一打线垫、中距的第二打线垫及短距的第三打线垫，故相比于现有技术，当该封装层的流动胶材的冲击而使该第一至第三打线垫上的焊线产生偏位现象时，即使该第一至第三打线垫上的焊线的偏位距离过大，该些焊线仍不会相互接触，因而不会发生短路的问题。
附图说明
图1为现有半导体封装件的剖视示意图。
图2为本发明的电子封装件的剖视示意图。
图2A为图2的上视平面示意图。
图2B为图2A的另一实施例的上视平面示意图。
图2C为图2A的局部放大示意图。
图3A及图3B为本发明的电子封装件的不同实施例的上视平面示意图。
图4为本发明的电子封装件的另一实施例的上视平面示意图。
主要组件符号说明
1 半导体封装件
10 封装基板
100,200 打线垫
11 半导体芯片
110,210 电极垫
12,22 焊线
13 封装胶体
2 电子封装件
20 承载结构
20a 第一表面
20b 第二表面
200a 顶面
201 第一打线垫
202,402 第二打线垫
203,403 第三打线垫
204,404 第四打线垫
21 电子元件
21a 作用面
21b 非作用面
22a 第一焊线
22b 第二焊线
23 封装层
24 导电元件
A 置晶区
C,C1,C2 假想圆
k 连接处
L 垫长
L1,L2 投影长度
R 直径
t 最小间距
t1 第一间距
t2 第二间距
t3 第三间距
t4 第四间距
t5 第五间距
W 垫宽
X 第一方向
Y 第二方向。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书附图所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”、“一”等的用语，亦仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当亦视为本发明可实施的范畴。
图2为本发明的电子封装件2的剖面示意图。于本实施例中，所述的电子封装件2为打线封装实施例。
如图2所示，该电子封装件2包含一承载结构20、至少一电子元件21、多个焊线22以及一封装层23。
所述的承载结构20具有一置晶区A，其周围布设有多个相同形体的打线垫200，且该打线垫200的顶面200a呈对称形状，以令该打线垫200依其顶面200a的几何形状(如图2A所示的矩形或图2B所示的指节形)定义出最长边缘作为垫长L与最短边缘作为垫宽W，且该垫长L大于该垫宽W。所述的打线垫200的几何形状为一沿由电子元件21(或置晶区A)朝外的放射方向(如图2A所示的第一方向X)延伸的对称图形(如图2A所示的长方形)，以定义该对称图形沿该放射方向有一最长边距(两相对边缘的最大距离，如图2A所示的两短边之间的最大距离)，且定义该图形沿该放射方向的垂直方向(如图2A所示的第一方向Y)亦有一最长边距(两相对边缘的最大距离，如图2A所示的两长边之间的最大距离)，例如，于该放射方向上所对应的最长边距为垫长L，而于该垂直方向上所对应的最长边距为垫宽W。
于本实施例中，该承载结构20如具有核心层与线路层的封装基板(substrate)或无核心层(coreless)的封装基板，其包含至少一介电层及结合该介电层的线路层，且最外层的线路层布设有该些打线垫。例如，以线路重布层(redistribution layer，简称RDL)的制作方式制作该封装基板，其中，形成该线路层的材料为铜，且形成该介电层的材料为如聚对二唑苯(Polybenzoxazole，简称PBO)、聚酰亚胺(Polyimide，简称PI)、预浸材(Prepreg，简称PP)等的介电材。应可理解地，该承载结构20亦可为其它可供承载如芯片等电子元件21的载板，并不限于上述。
再者，该承载结构20具有相对的第一表面20a与第二表面20b，以令该第一表面20a作为置晶侧，供形成该置晶区A及该些打线垫200，以配置该电子元件21，而该承载结构20的第二表面20b则作为植球侧，供形成多个如焊球的导电元件24，以将该电子封装件2结合至一电路板(图略)上。
另外，基于该置晶区A(如矩形或其它几何形状)，该第一表面20a定义有垂直邻接的第一方向X与第二方向Y，其中，第一方向X与第二方向Y分别平行于置晶区A的相邻两边，如图2A或图2B所示。
另外，该些打线垫200于该第一表面20a上相互间隔排布，且由于该打线垫200的顶面200a呈对称形状，使任两相邻的打线垫200的边缘之间产生最小间距t，如图2C所示，其令一直径R为该垫宽W的假想圆C可调整至不会重叠于该两相邻的打线垫200的任一者上。
所述的电子元件21设于该承载结构20的第一表面20a的置晶区A上。
于本实施例中，该电子元件21为主动元件、被动元件或其二者组合等，其中，该主动元件为例如半导体芯片，且该被动元件为例如电阻、电容及电感。例如，该电子元件21具有相对的作用面21a与非作用面21b，且该作用面21a具有多个电极垫210，并使该电子元件21以其非作用面21b通过粘着层(图略)结合该承载结构20，其中，该作用面21a与该电极垫210可呈任意形状，如图3A所示的矩形。
再者，于该多个打线垫200的任三相邻者中，依据相距该电子元件21的远近定义出长距的第一打线垫201、中距的第二打线垫202及短距的第三打线垫203，如图3A所示，以令该第一打线垫201的中心点与该第二打线垫202的中心点之间沿该第一方向X(或水平方向)定义有第一间距t1、该第二打线垫202的中心点与该第三打线垫203的中心点之间沿该第一方向X(或水平方向)定义有第二间距t2、该第二打线垫202的边缘与该第三打线垫203的边缘之间定义有令一直径为该垫宽W的假想圆C1可调整至不会重叠于该第二与第三打线垫202,203任一者上的第三间距t3、及该第一打线垫201的边缘与该第二打线垫202的边缘之间定义有令一直径为该垫宽W的假想圆C2可调整至不会重叠于该第一与第二打线垫201,202任一者上的第四间距t4。
例如，该第一间距t1大于或等于该打线垫200的垫长L(如该垫长L的至少一倍)，而该第二间距t2大于或等于该打线垫200的垫长L(如该垫长L的至少一倍)。
另外，该第三打线垫203于相对该第二打线垫202的另一侧间隔布设有另一相邻的打线垫200，其定义为第四打线垫204，且该第三打线垫203的边缘与该第四打线垫204的边缘之间于垂直方向(如第二方向Y)上的最小间距t作为第五间距t5。例如，该第五间距t5为该打线垫200的垫宽W的至少七倍(即t5≧7W)。
另外，可依需求调整间距。例如，如图3B所示，使该第二打线垫202的边缘与该第三打线垫203的边缘之间的第三间距t3容许一直径至少为两倍该垫宽W的假想圆C1可调整至不会重叠于该第二与第三打线垫202,203任一者上，且该第一打线垫201的边缘与该第二打线垫202的边缘之间的第四间距t4容许一直径至少为1.5倍该垫宽W的假想圆C2可调整至不会重叠于该第一与第二打线垫201,202任一者上。
所述的多个焊线22连接多个电极垫210与多个打线垫200，以电性导通该电子元件21与该承载结构20。
于本实施例中，该些焊线22为金线或其它适当材料，且任二相邻的焊线22可依据打线距离定义为第一焊线22a与第二焊线22b，如图3A所示。例如，该第一焊线22a为长弧线，其连接该第四打线垫204与该电极垫210，且第二焊线22b为短弧线，其连接该第三打线垫203与该电极垫210。
再者，该第一焊线22a(长弧线)相对该第一表面20a的投影长度L1及/或该第二焊线22b(短弧线)相对该第一表面20a的投影长度L2与该第五间距t5的比值至少为7(L1/t5≧7及/或L2/t5≧7)。
所述的封装层23形成于该承载结构20的第一表面20a上以包覆该电子元件21与焊线22。
于本实施例中，该封装层23为绝缘材，如聚酰亚胺(polyimide，简称PI)、干膜(dryfilm)、如环氧树脂(epoxy)的封装胶体或封装材(molding compound)。例如，该封装层23的制程可选择液态封胶(liquid compound)、喷涂(injection)、压合(lamination)或模压(compression molding)等方式形成于该承载结构20上。
因此，本发明的电子封装件2主要通过将连续相邻的三个打线垫200分别位于相距该电子元件21的长距、中距及短距的位置上，以当该封装层23的流动胶材的冲击而使焊线22产生偏位现象时(尤其是该承载结构20的第一表面20a的角落处或布设打线垫200的空旷区)，即使该些焊线22的偏位距离过大，相邻的两焊线22仍不会相互接触，因而不会发生短路的问题。
进一步，该第五间距t5为该打线垫200的垫宽W的至少七倍(即t5≧7W)；该第一焊线22a相对该第一表面20a的投影长度L1及/或该第二焊线22b相对该第一表面20a的投影长度L2与该第五间距t5的比值至少为7(L1/t5≧7及/或L2/t5≧7)；该第一间距t1大于或等于该打线垫200的垫长L(如该垫长L的至少一倍)，而该第二间距t2大于或等于该打线垫200的垫长L(如该垫长L的至少一倍)；或者，该第三间距t3为该垫宽W的两倍(即t3＝2W)，而该第四间距t4为该垫宽W的1.5倍(即t4＝1.5W)等四种布设打线垫200的方式的任一者均更有效避免相邻的两焊线22相互接触的发生。
应可理解地，该第一打线垫201、第二打线垫202及第三打线垫203(甚至第四打线垫204)为相互平行排设，以利于设计间距。然而，若该第一打线垫201、第二打线垫402及第三打线垫403(甚至第四打线垫404)的至少二者相互非平行排设，则以两者最接近的边缘之间令一直径大于或等于该垫宽W的假想圆C1,C2可调整至不会重叠于任一者上的距离作为第三及第四间距t3,t4，如图4所示，甚至于第三打线垫403与第四打线垫404以最接近的边缘之间作为第五间距t5。
综上所述，本发明的电子封装件，通过调整该打线垫的位置与各打线垫之间的间距，以避免因该封装层的流动胶材的冲击而产生焊线偏位现象所发生的短路问题，故相比于现有技术，本发明的电子封装件能有效提升其品质及可靠度。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (10)

1.一种电子封装件，包括：
承载结构，其于一表面上布设有顶面呈对称形状的多个打线垫，以令该多个打线垫依其顶面的几何形状定义出垫长与垫宽；
电子元件，其设于该承载结构上，其中，于该多个打线垫的任三相邻者中，依据相距该电子元件的远近定义出长距的第一打线垫、中距的第二打线垫及短距的第三打线垫；以及
多个焊线，其分别连接于该电子元件与各该多个打线垫之间。
2.如权利要求1所述的电子封装件，其中，该第一打线垫的中心点与该第二打线垫的中心点之间沿水平方向定义有第一间距，且该第一间距大于或等于该垫长。
3.如权利要求1所述的电子封装件，其中，该第二打线垫的中心点与该第三打线垫的中心点之间沿水平方向定义有第二间距，且该第二间距大于或等于该垫长。
4.如权利要求1所述的电子封装件，其中，该第二打线垫的边缘与该第三打线垫的边缘之间定义有一令一直径至少为两倍该垫宽的假想圆可调整至不会重叠于该第二与第三打线垫任一者上的第三间距。
5.如权利要求1所述的电子封装件，其中，该第一打线垫的边缘与该第二打线垫的边缘之间定义有一令一直径至少为1.5倍该垫宽的假想圆可调整至不会重叠于该第一与第二打线垫任一者上的第四间距。
6.如权利要求1所述的电子封装件，其中，该第三打线垫于相对该第二打线垫的另一侧间隔布设有另一相邻的第四打线垫，且该第三打线垫与该第四打线垫之间于垂直方向上的最小间距作为第五间距。
7.如权利要求6所述的电子封装件，其中，该第五间距为该垫宽的至少七倍。
8.如权利要求6所述的电子封装件，其中，该焊线相对该承载结构的表面的投影长度与该第五间距的比值至少为7。
9.如权利要求1所述的电子封装件，其中，该电子封装件还包括包覆该电子元件及该多个焊线的封装层。
10.如权利要求1所述的电子封装件，其中，该承载结构于相对该置晶区的另一表面上形成有多个导电元件。
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