TWI816499B - 電子封裝件 - Google Patents

電子封裝件 Download PDF

Info

Publication number
TWI816499B
TWI816499B TW111129166A TW111129166A TWI816499B TW I816499 B TWI816499 B TW I816499B TW 111129166 A TW111129166 A TW 111129166A TW 111129166 A TW111129166 A TW 111129166A TW I816499 B TWI816499 B TW I816499B
Authority
TW
Taiwan
Prior art keywords
pad
wiring
bonding
spacing
pads
Prior art date
Application number
TW111129166A
Other languages
English (en)
Other versions
TW202407928A (zh
Inventor
林慶治
王汶鑫
謝志毅
王馨妤
黃怡倩
簡秀芳
Original Assignee
矽品精密工業股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW111129166A priority Critical patent/TWI816499B/zh
Priority to CN202210967252.6A priority patent/CN117558703A/zh
Priority to US17/981,763 priority patent/US20240047336A1/en
Application granted granted Critical
Publication of TWI816499B publication Critical patent/TWI816499B/zh
Publication of TW202407928A publication Critical patent/TW202407928A/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H01L2224/05012—Shape in top view
    • H01L2224/05013—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/0805—Shape
    • H01L2224/08052—Shape in top view
    • H01L2224/08054—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4801—Structure
    • H01L2224/48011—Length
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901—Structure
    • H01L2224/4903—Connectors having different sizes, e.g. different diameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4905—Shape
    • H01L2224/49051—Connectors having different shapes
    • H01L2224/49052—Different loop heights
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H01L2224/49176—Wire connectors having the same loop shape and height
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/182—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/386—Wire effects
    • H01L2924/3862—Sweep

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Control And Other Processes For Unpacking Of Materials (AREA)

Abstract

一種電子封裝件，係於一表面上佈設有複數打線墊之承載結構上設置一電子元件，且以複數銲線連接該電子元件之複數電極墊與該複數打線墊，並於該複數打線墊之相鄰三者中，依據相距該電子元件之遠近定義出長距之第一打線墊、中距之第二打線墊及短距之第三打線墊，故當封裝層之流動膠材包覆該電子元件與複數銲線時，即使該第一至第三打線墊上之銲線受膠材沖擊而產生偏位現象，該些銲線仍不會相互接觸，避免發生短路問題。

Description

電子封裝件
本發明係有關一種半導體裝置，尤指一種打線封裝形式之電子封裝件。
隨著半導體製程技術的進步，更多電子元件整合於半導體晶片中，因而晶片上所設置的輸入/輸出連接端(I/O connections)數目漸多，同樣地，承載半導體晶片用之封裝基板上需密集地佈設複數個與該等輸入/輸出連接端電性連通之打線墊，作為半導體晶片之接點。
如圖1所示之半導體封裝件1，其係於一封裝基板10上承載一半導體晶片11，且該半導體晶片11之電極墊110透過複數銲線12電性連接該封裝基板10之打線墊100，再形成封裝膠體13於該封裝基板10上，以包覆該半導體晶片11與銲線12，其中，於半導體封裝件輕、薄、短、小之需求下，該半導體晶片11之電極墊110尺寸極小，因而需極小尺寸的銲線12及更小的打線墊100之間距進行打線製程，故於該封裝基板10之表面上會呈現出佈滿打線墊100之高密度接點區及零星佈設打線墊100之空曠區(如角落處)。
然而，於形成該封裝膠體13之過程中，對應該空曠區中之該些銲線12容易受到該封裝膠體13之流動膠材的沖擊而產生銲線偏位(wire sweep)現象，故當該銲線12之偏位距離過大，將會造成相鄰之銲線12相接觸(如圖1所示之連接處k)而發生短路，致使該半導體封裝件1之品質及可靠度不佳。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種電子封裝件，係包括：承載結構，係於一表面上佈設有頂面呈對稱形狀之複數打線墊，以令該複數打線墊依其頂面之幾何形狀定義墊長與墊寬；電子元件，係設於該承載結構上，其中，於該複數打線墊之任三相鄰者中，依據相距該電子元件之遠近係定義出長距之第一打線墊、中距之第二打線墊及短距之第三打線墊；以及複數銲線，係分別連接於該電子元件與各該複數打線墊之間。
前述之電子封裝件中，該第一打線墊之中心點與該第二打線墊之中心點之間沿水平方向定義有第一間距，且該第一間距係大於或等於該墊長。
前述之電子封裝件中，該第二打線墊之中心點與該第三打線墊之中心點之間沿水平方向定義有第二間距，且該第二間距係大於或等於該墊長。
前述之電子封裝件中，該第二打線墊之邊緣與該第三打線墊之邊緣之間係定義有一令一直徑為兩倍該墊寬的假想圓可調整至不會重疊於該第二與第三打線墊任一者上的第三間距。
前述之電子封裝件中，該第一打線墊之邊緣與該第二打線墊之邊緣之間係定義有一令一直徑為1.5倍該墊寬的假想圓可調整至不會重疊於該第一與第二打線墊任一者上的第四間距。
前述之電子封裝件中，該第三打線墊於相對該第二打線墊之另一側係間隔佈設有另一相鄰之第四打線墊，且該第三打線墊與該第四打線墊之間於垂直方向上的最小間距係作為第五間距。例如，該第五間距係為該墊寬之至少七倍。
前述之電子封裝件中，復包括包覆該電子元件及該複數銲線之封裝層。
前述之電子封裝件中，該承載結構於相對該置晶區之另一表面上係形成有複數導電元件。
由上可知，本發明之電子封裝件中，主要藉由將該複數打線墊之任三相鄰者依據相距該電子元件之遠近定義出長距之第一打線墊、中距之第二打線墊及短距之第三打線墊，故相較於習知技術，當該封裝層之流動膠材的沖擊而使該第一至第三打線墊上之銲線產生偏位現象時，即使該第一至第三打線墊上之銲線之偏位距離過大，該些銲線仍不會相互接觸，因而不會發生短路之問題。
1:半導體封裝件
10:封裝基板
100,200:打線墊
11:半導體晶片
110,210:電極墊
12,22:銲線
13:封裝膠體
2:電子封裝件
20:承載結構
20a:第一表面
20b:第二表面
200a:頂面
201:第一打線墊
202,402:第二打線墊
203,403:第三打線墊
204,404:第四打線墊
21:電子元件
21a:作用面
21b:非作用面
22a:第一銲線
22b:第二銲線
23:封裝層
24:導電元件
A:置晶區
C,C1,C2:假想圓
k:連接處
L:墊長
L1,L2:投影長度
R:直徑
t:最小間距
t1:第一間距
t2:第二間距
t3:第三間距
t4:第四間距
t5:第五間距
W:墊寬
X:第一方向
Y:第二方向
圖1係為習知半導體封裝件之剖視示意圖。
圖2係為本發明之電子封裝件之剖視示意圖。
圖2A係為圖2之上視平面示意圖。
圖2B係為圖2A之另一態樣之上視平面示意圖。
圖2C係為圖2A之局部放大示意圖。
圖3A及圖3B係為本發明之電子封裝件之不同態樣之上視平面示意圖。
圖4係為本發明之電子封裝件之另一實施例之上視平面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「第一」、「第二」、「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
圖2係為本發明之電子封裝件2的剖面示意圖。於本實施例中，所述之電子封裝件2係為打線封裝態樣。
如圖2所示，該電子封裝件2係包含一承載結構20、至少一電子元件21、複數銲線22以及一封裝層23。
所述之承載結構20係具有一置晶區A，其周圍佈設有複數相同形體之打線墊200，且該打線墊200之頂面200a係呈對稱形狀，以令該打線墊200依其頂面200a之幾何形狀(如圖2A所示之矩形或圖2B所示之指節形)定義出最長邊緣作為墊長L與最短邊緣作為墊寬W，且該墊長L係大於該墊寬W。所述之打線墊200之幾何形狀為一沿由電子元件21(或置晶區A)朝外之放射方向(如圖2A所示之第一方向X)延伸之對稱圖形(如圖2A所示之長方形)，以定義該對稱圖形沿該放射方向有一最長邊距(兩相對邊緣的最大距離，如圖2A所示之兩短邊之間的最大距離)，且定義該圖形沿該放射方向之垂直方向(如圖2A所示之第二方向Y)亦有一最長邊距(兩相對邊緣的最大距離，如圖2A所示之兩長邊之間的最大距離)，例如，於該放射方向上所對應之最長邊距為墊長L，而於該垂直方向上所對應之最長邊距為墊寬W。
於本實施例中，該承載結構20係如具有核心層與線路層之封裝基板(substrate)或無核心層(coreless)之封裝基板，其包含至少一介電層及結合該介電層之線路層，且最外層之線路層係佈設有該些打線墊。例如，以線路重佈層(redistribution layer，簡稱RDL)之製作方式製作該封裝基板，其中，形成該線路層之材質係為銅，且形成該介電層之材質係為如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)等之介電材。應可理解地，該承載結構20亦可為其它可供承載如晶片等電子元件21之載板，並不限於上述。
再者，該承載結構20係具有相對之第一表面20a與第二表面20b，以令該第一表面20a作為置晶側，供形成該置晶區A及該些打線 墊200，以配置該電子元件21，而該承載結構20之第二表面20b則作為植球側，供形成複數如銲球之導電元件24，以將該電子封裝件2結合至一電路板(圖略)上。
又，基於該置晶區A(如矩形或其它幾何形狀)，該第一表面20a係定義有垂直鄰接之第一方向X與第二方向Y，其中，第一方向X與第二方向Y係分別平行於置晶區A之相鄰兩邊，如圖2A或圖2B所示。
另外，該些打線墊200於該第一表面20a上係相互間隔排佈，且由於該打線墊200之頂面200a係呈對稱形狀，使任兩相鄰之打線墊200之邊緣之間係產生最小間距t，如圖2C所示，其令一直徑R為該墊寬W的假想圓C可調整至不會重疊於該兩相鄰之打線墊200之任一者上。
所述之電子元件21係設於該承載結構20之第一表面20a之置晶區A上。
於本實施例中，該電子元件21係為主動元件、被動元件或其二者組合等，其中，該主動元件係例如半導體晶片，且該被動元件係例如電阻、電容及電感。例如，該電子元件21係具有相對之作用面21a與非作用面21b，且該作用面21a具有複數電極墊210，並使該電子元件21以其非作用面21b藉由黏著層(圖略)結合該承載結構20，其中，該作用面21a與該電極墊210可呈任意形狀，如圖3A所示之矩形。
再者，於該複數打線墊200之任三相鄰者中，依據相距該電子元件21之遠近係定義出長距之第一打線墊201、中距之第二打線墊202及短距之第三打線墊203，如圖3A所示，以令該第一打線墊201之中心點與該第二打線墊202之中心點之間沿該第一方向X(或水平方向)定義有第一間距t1、該第二打線墊202之中心點與該第三打線墊203之中心點之間沿該第一方向X(或水平方向)定義有第二間距t2、該第二打線墊202 之邊緣與該第三打線墊203之邊緣之間係定義有令一直徑為該墊寬W的假想圓C1可調整至不會重疊於該第二與第三打線墊202,203任一者上的第三間距t3、及該第一打線墊201之邊緣與該第二打線墊202之邊緣之間係定義有令一直徑為該墊寬W的假想圓C2可調整至不會重疊於該第一與第二打線墊201,202任一者上的第四間距t4。
例如，該第一間距t1係大於或等於該打線墊200之墊長L(如該墊長L之至少一倍)，而該第二間距t2係大於或等於該打線墊200之墊長L(如該墊長L之至少一倍)。
又，該第三打線墊203於相對該第二打線墊202之另一側係間隔佈設有另一相鄰之打線墊200，其定義為第四打線墊204，且該第三打線墊203之邊緣與該第四打線墊204之邊緣之間於垂直方向(如第二方向Y)上的最小間距t係作為第五間距t5。例如，該第五間距t5係為該打線墊200之墊寬W之至少七倍(即t5≧7W)。
另外，可依需求調整間距。例如，如圖3B所示，使該第二打線墊202之邊緣與該第三打線墊203之邊緣之間的第三間距t3容許一直徑至少為兩倍該墊寬W的假想圓C1可調整至不會重疊於該第二與第三打線墊202,203任一者上，且該第一打線墊201之邊緣與該第二打線墊202之邊緣之間的第四間距t4容許一直徑至少為1.5倍該墊寬W的假想圓C2可調整至不會重疊於該第一與第二打線墊201,202任一者上。
所述之複數銲線22係連接複數電極墊210與複數打線墊200，以電性導通該電子元件21與該承載結構20。
於本實施例中，該些銲線22係為金線或其它適當材料，且任二相鄰之銲線22可依據打線距離定義為第一銲線22a與第二銲線22b，如圖3A所示。例如，該第一銲線22a係為長弧線，其連接該第四打線墊204 與該電極墊210，且第二銲線22b係為短弧線，其連接該第三打線墊203與該電極墊210。
再者，該第一銲線22a(長弧線)相對該第一表面20a之投影長度L1及/或該第二銲線22b(短弧線)相對該第一表面20a之投影長度L2與該第五間距t5的比值係至少為7(L1/t5≧7及/或L2/t5≧7)。
所述之封裝層23係形成於該承載結構20之第一表面20a上以包覆該電子元件21與銲線22。
於本實施例中，該封裝層23係為絕緣材，如聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、如環氧樹脂(epoxy)之封裝膠體或封裝材(molding compound)。例如，該封裝層23之製程可選擇液態封膠(liquid compound)、噴塗(injection)、壓合(lamination)或模壓(compression molding)等方式形成於該承載結構20上。
因此，本發明之電子封裝件2主要藉由將連續相鄰之三個打線墊200分別位於相距該電子元件21之長距、中距及短距之位置上，以當該封裝層23之流動膠材的沖擊而使銲線22產生偏位現象時(尤其是該承載結構20之第一表面20a之角落處或佈設打線墊200之空曠區)，即使該些銲線22之偏位距離過大，相鄰之兩銲線22仍不會相互接觸，因而不會發生短路之問題。
進一步，該第五間距t5係為該打線墊200之墊寬W之至少七倍(即t5≧7W)；該第一銲線22a相對該第一表面20a之投影長度L1及/或該第二銲線22b相對該第一表面20a之投影長度L2與該第五間距t5的比值係至少為7(L1/t5≧7及/或L2/t5≧7)；該第一間距t1係大於或等於該打線墊200之墊長L(如該墊長L之至少一倍)，而該第二間距t2係大於或等於該打線墊200之墊長L(如該墊長L之至少一倍)；或者，該 第三間距t3係為該墊寬W之兩倍(即t3=2W)，而該第四間距t4係為該墊寬W之1.5倍(即t4=1.5W)等四種佈設打線墊200之方式之任一者均更有效避免相鄰之兩銲線22相互接觸之發生。
應可理解地，該第一打線墊201、第二打線墊202及第三打線墊203(甚至第四打線墊204)係相互平行排設，以利於設計間距。然而，若該第一打線墊201、第二打線墊402及第三打線墊403(甚至第四打線墊404)之至少二者係相互非平行排設，則以兩者最接近的邊緣之間令一直徑大於或等於該墊寬W的假想圓C1,C2可調整至不會重疊於任一者上的距離作為第三及第四間距t3,t4，如圖4所示，甚至於第三打線墊403與第四打線墊404以最接近的邊緣之間作為第五間距t5。
綜上所述，本發明之電子封裝件，係藉由調整該打線墊之位置與各打線墊之間的間距，以避免因該封裝層之流動膠材的沖擊而產生銲線偏位現象所發生之短路問題，故相較於習知技術，本發明之電子封裝件能有效提升其品質及可靠度。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
20:承載結構
20a:第一表面
200:打線墊
201:第一打線墊
202:第二打線墊
203:第三打線墊
200a:頂面
A:置晶區
L:墊長
W:墊寬
X:第一方向
Y:第二方向

Claims (9)

  1. 一種電子封裝件，係包括：承載結構，係於一表面上佈設有頂面呈對稱形狀之複數打線墊，以令該複數打線墊依其頂面之幾何形狀定義出墊長與墊寬；電子元件，係設於該承載結構上，其中，於該複數打線墊之任三相鄰者中，依據相距該電子元件之遠近係定義出長距之第一打線墊、中距之第二打線墊及短距之第三打線墊；以及複數銲線，係分別連接於該電子元件與各該複數打線墊之間，其中，該第一打線墊之邊緣與該第二打線墊之邊緣之間係定義有一令一直徑至少為1.5倍該墊寬的假想圓可調整至不會重疊於該第一打線墊與該第二打線墊任一者上的第四間距。
  2. 如請求項1所述之電子封裝件，其中，該第一打線墊之中心點與該第二打線墊之中心點之間沿水平方向定義有第一間距，且該第一間距係大於或等於該墊長。
  3. 如請求項1所述之電子封裝件，其中，該第二打線墊之中心點與該第三打線墊之中心點之間沿水平方向定義有第二間距，且該第二間距係大於或等於該墊長。
  4. 如請求項1所述之電子封裝件，其中，該第二打線墊之邊緣與該第三打線墊之邊緣之間係定義有一令一直徑至少為兩倍該墊寬的假想圓可調整至不會重疊於該第二與第三打線墊任一者上的第三間距。
  5. 如請求項1所述之電子封裝件，其中，該第三打線墊於相對該第二打線墊之另一側係間隔佈設有另一相鄰之第四打線墊，且該第三打線墊與該第四打線墊之間於垂直方向上的最小間距係作為第五間距。
  6. 如請求項5所述之電子封裝件，其中，該第五間距係為該墊寬之至少七倍。
  7. 如請求項5所述之電子封裝件，其中，該銲線相對該承載結構之表面之投影長度與該第五間距的比值係至少為7。
  8. 如請求項1所述之電子封裝件，復包括包覆該電子元件及該複數銲線之封裝層。
  9. 如請求項1所述之電子封裝件，其中，該承載結構之該表面係具有一設置該電子元件之置晶區，且該承載結構於相對該置晶區之另一表面上係形成有複數導電元件。
TW111129166A 2022-08-03 2022-08-03 電子封裝件 TWI816499B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
TW111129166A TWI816499B (zh) 2022-08-03 2022-08-03 電子封裝件
CN202210967252.6A CN117558703A (zh) 2022-08-03 2022-08-12 电子封装件
US17/981,763 US20240047336A1 (en) 2022-08-03 2022-11-07 Electronic package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW111129166A TWI816499B (zh) 2022-08-03 2022-08-03 電子封裝件

Publications (2)

Publication Number Publication Date
TWI816499B true TWI816499B (zh) 2023-09-21
TW202407928A TW202407928A (zh) 2024-02-16

Family

ID=88966357

Family Applications (1)

Application Number Title Priority Date Filing Date
TW111129166A TWI816499B (zh) 2022-08-03 2022-08-03 電子封裝件

Country Status (3)

Country Link
US (1) US20240047336A1 (zh)
CN (1) CN117558703A (zh)
TW (1) TWI816499B (zh)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200725764A (en) * 2005-12-23 2007-07-01 Advanced Semiconductor Eng Method of wire bonding the chip with a plurality of solder pads
TW202115853A (zh) * 2019-10-04 2021-04-16 瑞昱半導體股份有限公司 晶片封裝模組

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200725764A (en) * 2005-12-23 2007-07-01 Advanced Semiconductor Eng Method of wire bonding the chip with a plurality of solder pads
TW202115853A (zh) * 2019-10-04 2021-04-16 瑞昱半導體股份有限公司 晶片封裝模組

Also Published As

Publication number Publication date
US20240047336A1 (en) 2024-02-08
TW202407928A (zh) 2024-02-16
CN117558703A (zh) 2024-02-13

Similar Documents

Publication Publication Date Title
US11469201B2 (en) Semiconductor package and method for fabricating base for semiconductor package
US8084869B2 (en) Semiconductor device and method for manufacturing the same
KR20220085624A (ko) 인터포저 및 이를 포함하는 반도체 패키지
JP2014096547A (ja) 半導体装置及びその製造方法
TWI566352B (zh) 封裝基板及封裝件
TW201806039A (zh) 電子堆疊結構及其製法
TWI816499B (zh) 電子封裝件
TWI763337B (zh) 封裝載板及應用其的晶片封裝結構
TWI796180B (zh) 電子封裝件及其製法
TWI819582B (zh) 電子封裝件及其基板結構
TWI805216B (zh) 電子封裝件及其基板結構
TWI832508B (zh) 電子封裝件
US20240145372A1 (en) Electronic package and manufacturing method thereof, and substrate structure
KR100776130B1 (ko) 적층형 반도체 패키지
US20240079301A1 (en) Electronic package and manufacturing method thereof
US11437325B2 (en) Electronic device, electronic package and packaging substrate thereof
TWI834356B (zh) 承載結構
TWI418276B (zh) 導電凸塊無翼部的封裝基板之製法
US20230369268A1 (en) Electronic package and electronic structure thereof
US20240234272A9 (en) Electronic package
US20220199505A1 (en) Semiconductor device
KR20230068244A (ko) 재배선 기판 및 이를 포함하는 반도체 패키지
TW202418485A (zh) 承載結構
TW202335224A (zh) 電子封裝件及其製法
TWM642378U (zh) 半導體封裝載板結構