TW202117970A - 晶片封裝元件 - Google Patents

晶片封裝元件 Download PDF

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TW202117970A
TW202117970A TW108142006A TW108142006A TW202117970A TW 202117970 A TW202117970 A TW 202117970A TW 108142006 A TW108142006 A TW 108142006A TW 108142006 A TW108142006 A TW 108142006A TW 202117970 A TW202117970 A TW 202117970A
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Taiwan
Prior art keywords
pads
conductive layer
chip
chip package
wiring
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TW108142006A
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English (en)
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TWI716198B (zh
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楊吳德
尤俊煌
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南亞科技股份有限公司
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Publication of TWI716198B publication Critical patent/TWI716198B/zh
Publication of TW202117970A publication Critical patent/TW202117970A/zh

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Abstract

晶片封裝元件包括基板、第一晶片、第一導電層、第一接線以及第二接線。基板包括第一上表面以及配置於第一上表面的第一接墊。第一晶片配置在第一上表面，且第一晶片包括第二上表面以及配置在第二上表面的第二接墊。第一導電層配置在第二上表面。第一接線連接第一接墊以及第一導電層的一側，第二接線連接第二接墊以及第一導電層的另一側。每個第一接線和每個第二接線連接各自第一導電層的相反側。

Description

晶片封裝元件
本發明有關於一種晶片封裝元件，特別是有關於一種加強連接方式的晶片封裝元件。
積體電路(Integrated circuit)是一組設置在通常是矽的半導體材料晶片的電子電路。將大量的微型金屬氧化物半導體(metal oxide semiconductor,MOS)電晶體整合至一個微小晶片，可以使電路的尺寸比獨立設置的電子元件尺寸小、快且便宜。然而，由於晶片需要更小且更快的元件，對於電流的要求也隨之提高。當晶片的細小金屬線以大電流傳輸信號時，會導致不希望的信號失真(distortion)以及IR壓降(IR drop)，並在晶片的接地線路和電源線路所傳遞的訊號造成更多雜訊。
本發明有關於一種晶片封裝元件。
本發明實施例所提出的晶片封裝元件包括基板、第一晶片、第一導電層、多個第一接線以及多個第二接線。基板，包括一第一上表面以及多個配置於第一上表面的第一接墊。第一晶片配置於第一上表面，且第一晶片包括一第二上表 面以及多個配置於第二上表面的第二接墊。第一導電層配置於第二上表面。這些第一接線連接這些第一接墊至第一導電層。這些第二接線連接這些第二接墊至第一導電層。每個第一接線和每個第二接線各自連接第一導電層的相對兩側。
在本發明的一實施例中，上述的晶片封裝元件還包括多個第三接線。這些第三接線連接這些第一接墊和這些第二接墊，且這些第三接線繞過第一導電層。
在本發明的一實施例中，上述的第一導電層在第二上表面的投影區域與這些第一接線在第二上表面的投影區域重疊。
在本發明的一實施例中，上述的部分這些第三接線位於第一導電層以及第二上表面之間。
在本發明的一實施例中，上述的這些第三接線位於第一導電層上，且第一導電層配置於第三接線以及第二上表面之間。
在本發明的一實施例中，上述的晶片封裝元件還包括一黏接層。黏接層配置在第一導電層以及這些第三接線之間，且黏接層形成第一導電層以及這些第三接線之間的絕緣。
在本發明的一實施例中，上述的晶片封裝元件，還包括多個重新佈線層(redistribution layer,RDL)。這些重新佈線層配置於第二上表面，且每個重新佈線層連接這些第三接線的其中之一至這些第二接墊的其中之一。
在本發明的一實施例中，上述的這些第一接墊接地，且這些第二接墊為第一晶片的接地接墊。
在本發明的一實施例中，上述的這些第一接墊連接至供應電源，且這些第二接墊為第一晶片的電源接墊。
在本發明的一實施例中，上述的這些第二接墊沿著第二上表面的一中間線配置。
在本發明的一實施例中，上述的第一晶片包括多個配置於第二上表面的第四接墊。晶片封裝元件包括多個第三接墊、一第二導電層、多個第四接線以及多個第五接線。這些第三接墊配置於第一上表面。第二導電層配置於第二上表面。這些第四接線連接第二導電層至這些第三接墊。這些第五接線連接第二導電層至這些第四接墊。每個第四接線以及每個第五接線各自連接第二導電層的相對兩側。
在本發明的一實施例中，上述的晶片封裝元件還包括多個第六接線。這些第六接線連接這些第三接墊以及這些第四接墊，且這些第六接墊繞過第二導電層。
在本發明的一實施例中，上述的這些第二接墊以及這些第四接墊位於第一導電層以及第二導電層之間。
在本發明的一實施例中，上述的這些第四接墊實質上與這些第二接墊對齊。
在本發明的一實施例中，上述的這些第一接墊接地，且這些第二接墊為第一晶片的接地接墊。這些第三接墊連接至供應電源，且這些第四接墊為第一晶片的電源接墊。
在本發明的一實施例中，上述的晶片封裝元件還包括一第二晶片、一第三導電層、多個第七接線、多個第八接線以及多個第九接線。第二晶片配置於第一晶片上，且第二晶 片包括一第三上表面以及多個配置於第三上表面的第五接墊。第三導電層配置於第三上表面。這些第七接線連接這些第一接墊至這些第五接墊，且這些第七接線繞過第三導電層。這些第八接線連接這些第一接墊至第三導電層。這些第九接線連接這些第五接墊至第一導電層。每個第八接線以及每個第九接線各自連接第三導電層的相對兩側。
由上述可知，在本發明實施例的晶片封裝元件中，由於第一導電層透過這些第一接線以及這些第二接線連接這些第一接墊至這些第二接墊，基板和第一晶片之間的電性連接可以進一步加強，進而避免訊號的雜訊以及失真。
50‧‧‧供應電源
100‧‧‧晶片封裝元件
100A‧‧‧晶片封裝元件
100B‧‧‧晶片封裝元件
100C‧‧‧晶片封裝元件
100D‧‧‧晶片封裝元件
100E‧‧‧晶片封裝元件
110‧‧‧基板
111‧‧‧第一上表面
112‧‧‧第一接墊
113‧‧‧接墊
114‧‧‧第三接墊
120‧‧‧第一晶片
121‧‧‧第二上表面
122‧‧‧第二接墊
124‧‧‧第四接墊
130‧‧‧第一導電層
131‧‧‧導電上表面
140‧‧‧第三接線
142‧‧‧重新佈線層
144‧‧‧第七接線
150‧‧‧第一接線
152‧‧‧第八接線
160‧‧‧第二接線
162‧‧‧第九接線
170‧‧‧黏接層
172‧‧‧黏接層
174‧‧‧黏接層
180‧‧‧第二導電層
190‧‧‧第六接線
200‧‧‧第四接線
210‧‧‧第五接線
220‧‧‧第二晶片
221‧‧‧第三上表面
222‧‧‧第五接墊
230‧‧‧第三導電層
第1圖是本發明一實施例中晶片封裝元件的上視示意圖；
第2圖是根據第1圖中割面線2所繪之剖面示意圖；
第3圖是本發明另一實施例中晶片封裝元件的剖面示意圖；
第4圖是本發明再一實施例中晶片封裝元件的上視示意圖；
第5圖是根據第4圖中割面線5所繪之剖面示意圖；
第6圖是根據本發明又一實施例中晶片封裝元件的上視示意圖；
第7圖是根據第6圖中割面線7所繪之剖面示意圖；
第8圖是根據第6圖中割面線8所繪之剖面示意圖；
第9圖是本發明另一實施例中晶片封裝元件的剖面示意圖；
第10圖是本發明再一實施例中晶片封裝元件的剖面示意圖。
在附加圖式中，為了清楚起見，放大了層、膜、面板、區域等厚度。在本說明書中，相同的圖標標示相同的元件。應當理解，當諸如層、膜、區域或基板的元件被稱為在另一元件「上」或「連接到」另一元件時，其可以直接在另一元件上與另一元件連接，或者可以存在中間元件。相對而言，當元件被稱為「直接在另一元件上」或「直接連接到」另一元件時，不存在中間元件。如本文所使用的，「連接」可以指物理及/或電性連接。再者，「電性連接」或「耦合」係可為二元件間存在其他元件。
第1圖是本發明一實施例中晶片封裝元件100的上視示意圖。第2圖是根據第1圖中割面線2繪示的剖面示意圖。請參照第1圖以及第2圖，晶片封裝元件100包括一基板110、一第一晶片120以及一第一導電層130。第一晶片120配置在基板110上，且第一導電層130配置在第一晶片120上。亦即第一晶片120位於第一導電層130以及基板110之間。
舉例而言，本實施例的第一晶片120可以是動態隨機存取記憶體(dynamic random access memory,DRAM)晶片，基板110可以是印刷電路板(printed-circuit board, PCB)。然而，本發明並不限於此。請參照第2圖，基板110包括第一上表面111以及第一接墊112，且第一接墊112配置在第一上表面111。基板110的第一上表面111面朝上並機構上之稱第一晶片120。
基板110的第一上表面111電性連接配置其上的第一晶片120。晶片封裝元件100更包含第一接線150以及第二接線160。第一晶片120包括第二上表面121以及配置於第二上表面121的第二接墊122。進一步而言，在本實施例中，第一導電層130配置在第二上表面121，且第一接線150以及第二接線160各自連接在第一導電層130的相對兩側。
參照第2圖，第一接線150連接第一接墊112以及第一導電層130，且第二接線160連接第一導電層130以及第二接墊122，且第一導電層130的導電上表面131提供一個寬廣的連接區域給第一接線150以及第二接線160。此外，在本實施例的晶片封裝元件100中，大電流訊號可以經由第一導電層130傳輸，因此可以避免訊號的失真以及雜訊。
在本發明的一些實施例中，晶片封裝元件100還可以包括第三接線140。每個第三接線140具有兩個彼此相反的端點，其各自連接至第一上表面111的這些第一接墊112的其中之一以及第二上表面121上的這些第二接墊122的其中之一。第三接線140可以例如是由黃金所製成的細線，且第一導電層130的材質可以包含例如是銅或鋁的金屬，或是任何其他具有低阻抗的材質，且第一導電層130的厚度落在60微米(micrometer,μm)至100微米的範圍。因此，本實施例的第 一導電層130可以加強基板110以及第一晶片120之間的連接。換句話說，第三接線140是第一接墊112和第二接墊122之間的並聯線路的一分支，而第一接線150、第一導電層130以及第二接線160組成並聯線路的另一分支。進一步而言，相較於厚度較低的第三接線140，第一導電層130提供阻抗較低的電性連接。藉由上述設置，本實施例的晶片封裝元件100可以進一步避免IR壓降。
具體而言，在本實施例中，第二接墊122沿著第二上表面121的中間線排列。第一導電層130在第二上表面121的投影區域和第三接線140在第二上表面121的投影區域彼此重疊。
舉例而言，請參照第1圖，第三接線140還連接提供與第一接墊112所提供的訊號不同的接墊113。
相較於第三接線140，第一導電層130在第一晶片120的第二上表面121上具有寬度更大的較大分布區域，因此可以提升第一接墊112和第二接墊122之間的連接。
請參照第2圖，在本實施例中，製作晶片封裝元件100包括配置第一晶片120在基板110上；形成連接第一接墊112和第二接墊122的第三接線140；配置第一導電層130在第一晶片120上；形成連接第一接墊112和第一導電層130的第一接線150；形成連接第一導電層130和第二接墊122的第二接線160。
進一步而言，本實施例的晶片封裝元件100包括黏接層170，且黏接層170在配置第一導電層130之前設置於晶 片封裝元件100。請參照第2圖，黏接層170設置在第一導電層130和第三接線140之間，且黏接層170形成第一導電層130和第三接線140之間的絕緣。換句話說，黏接層170包括絕緣材料，且黏接層170在第一導電層130和第三接線140之間可以避免短路。
因此，本實施例的第三接線140穿過第一導電層130和第二上表面121之間的區域，且黏接層170在第一導電層130下覆蓋第三接線140。換句話說，本實施例的各第三接線140有一部分位於第一導電層130和第二上表面121之間。然而，本發明並不限於此。
第3圖是本發明另一實施例中晶片封裝元件100A的剖面示意圖。請參照第3圖，本實施例製作晶片封裝元件100A的方法包括配置第一晶片120在基板110上；配置第一導電層130在第一晶片120上；形成多個連接第一接墊112和第一導電層130的第一接線150；形成多個連接第一導電層130和第二接墊122的第二接線160；形成連接第一接墊112和第二接墊122的第三接線140。
因此，晶片封裝元件100A的第三接線140跨過第一導電層130，且第一導電層130配置在第三接線140和第一晶片120的第二上表面121之間。換句話說，第三接線140位於第一導電層130的上方。在本實施例中，黏接層170可以配置在第一導電層130的導電上表面131，藉以在第一導電層130和第三接線140之間形成絕緣。
參照第1圖，在本實施例中，第一接墊112接地或 是連接到一供應電源的接地電壓，且第二接墊122是第一晶片120的接地接墊，因此可以避免IR壓降或失真。換句話說，本實施例的第一導電層130可以在基板110和第一晶片120之間傳遞接地訊號。
在本發明的另一實施例中，第一導電層130也可以在基板110和第一晶片120之間傳遞例如是Vdd的電源訊號。第4圖是本發明再一實施例中晶片封裝元件100B的上視示意圖。第5圖是根據第4圖中割面線5所繪之晶片封裝元件100B的剖面示意圖。晶片封裝元件100B包括基板110、位於第一上表面111的第一接墊112、第一晶片120、位於第二上表面121的第二接墊122、第一導電層130、第三接線140、第一接線150以及第二接線160，上述元件類似於上述實施例中的晶片封裝元件100。此外，晶片封裝元件100B的黏接層170可以配置在第一導電層130和第二上表面121之間，以形成第一導電層130和第三接線140之間的絕緣。
進一步而言，晶片封裝元件100B的第一導電層130配置在第一晶片120的第二上表面121的另一區域，對應至第一接墊112的位置。在本實施例中，每個第一接墊112連接至供應電源50，且第二接墊122為第一晶片120的電源供應接墊。換句話說，在基板110和第一晶片120之間，第一導電層130、第一接線150以及第二接線160可以傳遞Vdd訊號，藉以避免IR壓降以及訊號失真。
在本發明的又一實施例中，晶片封裝元件還可以包括另外一個導電層配置在第一晶片上。第6圖是根據本發明 又一實施例中晶片封裝元件100C的上視示意圖。第7圖是根據第6圖中割面線7所繪之晶片封裝元件100C的剖面示意圖。第8圖是根據第6圖中割面線8所繪之晶片封裝元件100C的剖面示意圖。在本實施例中，晶片封裝元件100C包括基板110、第一接墊112、第一晶片120、第二接墊122、第三接線140、第一接線150以及第二接線160，上述元件類似於上述實施例中的晶片封裝元件100。
進一步而言，晶片封裝元件100C更包括第二導電層180，其配置在第一晶片120的第二上表面121，且第一晶片120包括配置在第二上表面121的第四接墊124。參照第6圖，第二接墊122配置在第二上表面121的中間，且第二接墊122和第四接墊124的分布區域位於第一導電層130在第二上表面121的投影區域以及第二導電層180在第二上表面121的投影區域之間。
換句話說，在第一晶片120上的第二接墊122和第四接墊124位於第一導電層130和第二導電層180之間，且第四接墊124和第二接墊122對齊排列。具體而言，本實施例中第一導電層130和第二導電層180的分布區域彼此不覆蓋。換句話說，第一導電層130和第二導電層180之間間隔一距離。
此外，晶片封裝元件100C還包括第三接墊114、第六接線190、第四接線200以及第五接線210。晶片封裝元件100C的第三接墊114配置在基板110的第一上表面111，且每個第六接線190連接這些第三接墊114的其中之一以及這些第四接墊124的其中之一。第四接線200連接第三接墊114以及第 二導電層180的一側，而第五接線210連接第四接墊124以及第二導電層180的另一側。換句話說，第六接線190以及由第四接線200、第二導電層180以及第五接線210組成的線路形成一並聯電路連接在第三接墊114和第四接墊124之間。因此，晶片封裝元件100C的第一導電層130和第二導電層180都可以提供良好的電性連接，且可以各自傳輸不同的訊號。
舉例而言，在本實施例中，第一接墊112接地，且第二接墊122是第一晶片120的接地接墊。每個第三接墊114連接至供應電源50，且第四接墊124是第一晶片120的電源接墊。換句話說，在本實施例中，第一導電層130可以在基板110和第一晶片120傳遞接地訊號(GND)，且第二導電層180可以在基板110和第一晶片120之間傳遞電源訊號(Vdd)，藉以避免兩個訊號的IR壓降以及訊號失真。
在本發明的另一實施例中，晶片封裝元件可以包含重新佈線層(RDL)。在本實施例中，重新佈線層是第一晶片上外加的金屬層，使第一晶片的第二接墊可以延伸至第一晶片的其他位置，以便在必要時在其他位置可以輕易連接第二接墊。第9圖是本發明另一實施例中晶片封裝元件100D的剖面示意圖。晶片封裝元件100D包括基板110、第一晶片120、第一導電層130、第一接線150以及第二接線160，上述元件類似於上述實施例中的晶片封裝元件100。此外，晶片封裝元件100D包括重新佈線層142，其配置在第一晶片120的第二上表面121，且重新佈線層142連接第三接線140以及第二接墊122。本實施例的每個重新佈線層142連接這些第一接墊112的其中 之一至這些第二接墊122的其中之一時，具有較大面積的第一導電層130可以在基板110和第一晶片120之間提供較佳的連接。
本發明實施例的再一實施例的晶片封裝元件可以應用至堆疊型晶片封裝元件。堆疊型晶片封裝元件是半導體封裝裝置，其利用三維封裝技術來垂直堆疊多個晶片。舉例而言，上述裝置可以應用於例如是記憶體模組、記憶卡、可攜式儲存碟等儲存裝置。
第10圖是本發明再一實施例中晶片封裝元件100E的剖面示意圖。請參照第10圖，晶片封裝元件100E包括基板110、第一接墊112、第一晶片120、第二接墊122、第一導電層130、第三接線140、第一接線150以及第二接線160，上述元件類似於上述實施例的晶片封裝元件100。進一步而言，晶片封裝元件100E更包括第二晶片220、第三導電層230、第七接線144、第八接線152以及第九接線162。
在本實施例中，第二晶片220配置在第一晶片120上，且第二晶片220包括第三上表面221以及配置於第二晶片220的第三上表面221的第五接墊222。第三導電層230配置在第二晶片220的第三上表面221。進一步而言，黏接層174設置在第二晶片220上，位於第三上表面221以及第三導電層230之間。黏接層172設置在第一導電層130上，位於導電上表面131以及第二晶片220之間。
參照第10圖，第七接線144連接第一接墊112以及第五接墊222，且第八接線152連接第一接墊112以及第三導電 層230的一側，且第九接線162連接第五接墊222以及第三導電層230的另一側，已同時提供加強的電性連接至第一晶片120以及第二晶片220。
100‧‧‧晶片封裝元件
110‧‧‧基板
111‧‧‧第一上表面
112‧‧‧第一接墊
120‧‧‧第一晶片
121‧‧‧第二上表面
122‧‧‧第二接墊
130‧‧‧第一導電層
131‧‧‧導電上表面
140‧‧‧第三接線
150‧‧‧第一接線
160‧‧‧第二接線
170‧‧‧黏接層

Claims (16)

  1. 一種晶片封裝元件，包括：
    一基板，包括一第一上表面以及多個第一接墊，其中該些第一接墊配置於該第一上表面；
    一第一晶片，配置於該第一上表面，該第一晶片包括一第二上表面以及多個第二接墊，其中該些第二接墊配置於該第二上表面；
    一第一導電層，配置於該第二上表面；
    多個第一接線，連接該些第一接墊至該第一導電層；以及
    多個第二接線，連接該些第二接墊至該第一導電層，其中每個該第一接線和每個該第二接線各自連接該第一導電層的相對兩側。
  2. 如申請專利範圍第1項所述之晶片封裝元件，還包括：
    多個第三接線，連接該些第一接墊和該些第二接墊，且該些第三接線繞過該第一導電層。
  3. 如申請專利範圍第2項所述之晶片封裝元件，其中該第一導電層在該第二上表面的投影區域與該些第一接線在該第二上表面的投影區域重疊。
  4. 如申請專利範圍第2項所述之晶片封裝元件，其中部分該些第三接線位於該第一導電層以及該第二上表面 之間。
  5. 如申請專利範圍第2項所述之晶片封裝元件，其中該些第三接線位於該第一導電層上，該第一導電層配置於該第三接線以及該第二上表面之間。
  6. 如申請專利範圍第2項所述之晶片封裝元件，還包括：
    一黏接層，配置在該第一導電層以及該些第三接線之間，其中該黏接層形成該第一導電層以及該些第三接線之間的絕緣。
  7. 如申請專利範圍第2項所述之晶片封裝元件，還包括：
    多個重新佈線層，配置於該第二上表面，其中每個該重新佈線層連接該些第三接線的其中之一至該些第二接墊的其中之一。
  8. 如申請專利範圍第1項所述之晶片封裝元件，其中該些第一接墊接地，且該些第二接墊為該第一晶片的接地接墊。
  9. 如申請專利範圍第1項所述之晶片封裝元件，其中該些第一接墊連接至供應電源，且該些第二接墊為該第一晶片的電源接墊。
  10. 如申請專利範圍第1項所述之晶片封裝元件，其中該些第二接墊沿著該第二上表面的一中間線配置。
  11. 如申請專利範圍第1項所述之晶片封裝元件，其中該第一晶片包括：
    多個第四接墊，配置於該第二上表面，
    該晶片封裝元件包括：
    多個第三接墊，配置於該第一上表面；
    一第二導電層，配置於該第二上表面；
    多個第四接線，連接該第二導電層至該些第三接墊；以及
    多個第五接線，連接該第二導電層至該些第四接墊，
    其中每個該第四接線以及每個該第五接線各自連接該第二導電層的相對兩側。
  12. 如申請專利範圍第11項所述之晶片封裝元件，還包括：
    多個第六接線，連接該些第三接墊以及該些第四接墊，且該些第六接墊繞過該第二導電層。
  13. 如申請專利範圍第11項所述之晶片封裝元件，其中該些第二接墊以及該些第四接墊位於該第一導電層以及該第二導電層之間。
  14. 如申請專利範圍第11項所述之晶片封裝元 件，其中該些第四接墊實質上與該些第二接墊對齊。
  15. 如申請專利範圍第11項所述之晶片封裝元件，其中該些第一接墊接地，且該些第二接墊為該第一晶片的接地接墊，且該些第三接墊連接至供應電源，且該些第四接墊為該第一晶片的電源接墊。
  16. 如申請專利範圍第1項所述的晶片封裝元件，還包括：
    一第二晶片，配置於該第一晶片上，該第二晶片包括一第三上表面以及多個第五接墊，該些第五接墊配置於該第三上表面；
    一第三導電層，配置於該第三上表面；
    多個第七接線，連接該些第一接墊至該些第五接墊，且該些第七接線繞過該第三導電層；
    多個第八接線，連接該些第一接墊至該第三導電層；以及
    多個第九接線，連接該些第五接墊至該第一導電層，
    其中每個該第八接線以及每個該第九接線各自連接該第三導電層的相對兩側。
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