CN112670259B - 晶圆封装元件 - Google Patents
晶圆封装元件 Download PDFInfo
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- CN112670259B CN112670259B CN201911170992.1A CN201911170992A CN112670259B CN 112670259 B CN112670259 B CN 112670259B CN 201911170992 A CN201911170992 A CN 201911170992A CN 112670259 B CN112670259 B CN 112670259B
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- pads
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Abstract
本发明公开了一种晶圆封装元件,包括基板、第一晶圆、第一导电层、第一接线以及第二接线。基板包括第一上表面以及配置于第一上表面的第一接垫。第一晶圆配置在第一上表面,且第一晶圆包括第二上表面以及配置在第二上表面的第二接垫。第一导电层配置在第二上表面。第一接线连接第一接垫以及第一导电层的一侧,第二接线连接第二接垫以及第一导电层的另一侧。每个第一接线和每个第二接线连接各自第一导电层的相反侧。第一导电层使晶圆封装元件具有较佳的电性连接。
Description
技术领域
本发明有关于一种晶圆封装元件,特别是有关于一种加强连接方式的晶圆封装元件。
背景技术
集成电路(Integrated circuit)是一组设置在通常是硅的半导体材料晶圆的电子电路。将大量的微型金属氧化物半导体(metal oxide semiconductor,MOS)晶体管整合至一个微小晶圆,可以使电路的尺寸比独立设置的电子元件尺寸小、快且便宜。然而,由于晶圆需要更小且更快的元件,对于电流的要求也随之提高。当晶圆的细小金属线以大电流传输信号时,会导致不希望的信号失真(distortion)以及IR压降(IR drop),并在晶圆的接地线路和电源线路所传递的信号造成更多噪声。
发明内容
本发明的目的在于提供一种晶圆封装元件,其第一导电层使晶圆封装元件具有较佳的电性连接。
本发明实施例所提出的晶圆封装元件包括基板、第一晶圆、第一导电层、多个第一接线以及多个第二接线。基板,包括第一上表面以及多个配置于第一上表面的第一接垫。第一晶圆配置于第一上表面,且第一晶圆包括第二上表面以及多个配置于第二上表面的第二接垫。第一导电层配置于第二上表面。这些第一接线连接这些第一接垫至第一导电层。这些第二接线连接这些第二接垫至第一导电层。每个第一接线和每个第二接线各自连接第一导电层的相对两侧。
在本发明的一实施例中,上述的晶圆封装元件还包括多个第三接线。这些第三接线连接这些第一接垫和这些第二接垫,且这些第三接线绕过第一导电层。
在本发明的一实施例中,上述的第一导电层在第二上表面的投影区域与这些第一接线在第二上表面的投影区域重叠。
在本发明的一实施例中,上述的部分这些第三接线位于第一导电层以及第二上表面之间。
在本发明的一实施例中,上述的这些第三接线位于第一导电层上,且第一导电层配置于第三接线以及第二上表面之间。
在本发明的一实施例中,上述的晶圆封装元件还包括粘接层。粘接层配置在第一导电层以及这些第三接线之间,且粘接层形成第一导电层以及这些第三接线之间的绝缘。
在本发明的一实施例中,上述的晶圆封装元件,还包括多个重新布线层(redistribution layer,RDL)。这些重新布线层配置于第二上表面,且每个重新布线层连接这些第三接线的其中之一至这些第二接垫的其中之一。
在本发明的一实施例中,上述的这些第一接垫接地,且这些第二接垫为第一晶圆的接地接垫。
在本发明的一实施例中,上述的这些第一接垫连接至供应电源,且这些第二接垫为第一晶圆的电源接垫。
在本发明的一实施例中,上述的这些第二接垫沿着第二上表面的中间线配置。
在本发明的一实施例中,上述的第一晶圆包括多个配置于第二上表面的第四接垫。晶圆封装元件包括多个第三接垫、第二导电层、多个第四接线以及多个第五接线。这些第三接垫配置于第一上表面。第二导电层配置于第二上表面。这些第四接线连接第二导电层至这些第三接垫。这些第五接线连接第二导电层至这些第四接垫。每个第四接线以及每个第五接线各自连接第二导电层的相对两侧。
在本发明的一实施例中,上述的晶圆封装元件还包括多个第六接线。这些第六接线连接这些第三接垫以及这些第四接垫,且这些第六接垫绕过第二导电层。
在本发明的一实施例中,上述的这些第二接垫以及这些第四接垫位于第一导电层以及第二导电层之间。
在本发明的一实施例中,上述的这些第四接垫实质上与这些第二接垫对齐。
在本发明的一实施例中,上述的这些第一接垫接地,且这些第二接垫为第一晶圆的接地接垫。这些第三接垫连接至供应电源,且这些第四接垫为第一晶圆的电源接垫。
在本发明的一实施例中,上述的晶圆封装元件还包括第二晶圆、第三导电层、多个第七接线、多个第八接线以及多个第九接线。第二晶圆配置于第一晶圆上,且第二晶圆包括第三上表面以及多个配置于第三上表面的第五接垫。第三导电层配置于第三上表面。这些第七接线连接这些第一接垫至这些第五接垫,且这些第七接线绕过第三导电层。这些第八接线连接这些第一接垫至第三导电层。这些第九接线连接这些第五接垫至第一导电层。每个第八接线以及每个第九接线各自连接第三导电层的相对两侧。
由上述可知,在本发明实施例的晶圆封装元件中,由于第一导电层通过这些第一接线以及这些第二接线连接这些第一接垫至这些第二接垫,基板和第一晶圆之间的电性连接可以进一步加强,进而避免信号的噪声以及失真。
附图说明
图1是本发明一实施例中晶圆封装元件的俯视示意图;
图2是根据图1中割面线2所绘的剖面示意图;
图3是本发明另一实施例中晶圆封装元件的剖面示意图;
图4是本发明再一实施例中晶圆封装元件的俯视示意图;
图5是根据图4中割面线5所绘的剖面示意图;
图6是根据本发明又一实施例中晶圆封装元件的俯视示意图;
图7是根据图6中割面线7所绘的剖面示意图;
图8是根据图6中割面线8所绘的剖面示意图;
图9是本发明另一实施例中晶圆封装元件的剖面示意图;
图10是本发明再一实施例中晶圆封装元件的剖面示意图。
主要附图标记说明:
50-供应电源,100-晶圆封装元件,100A-晶圆封装元件,100B-晶圆封装元件,100C-晶圆封装元件,100D-晶圆封装元件,100E-晶圆封装元件,110-基板,111-第一上表面,112-第一接垫,113-接垫,114-第三接垫,120-第一晶圆,121-第二上表面,122-第二接垫,124-第四接垫,130-第一导电层,131-导电上表面,140-第三接线,142-重新布线层,144-第七接线,150-第一接线,152-第八接线,160-第二接线,162-第九接线,170-粘接层,172-粘接层,174-粘接层,180-第二导电层,190-第六接线,200-第四接线,210-第五接线,220-第二晶圆,221-第三上表面,222-第五接垫,230-第三导电层。
具体实施方式
在附图中,为了清楚起见,放大了层、膜、面板、区域等厚度。在本说明书中,相同的图标标示相同的元件。应当理解,当诸如层、膜、区域或基板的元件被称为在另一元件”上”或”连接到”另一元件时,其可以直接在另一元件上与另一元件连接,或者可以存在中间元件。相对而言,当元件被称为”直接在另一元件上”或”直接连接到”另一元件时,不存在中间元件。如本文所使用的,”连接”可以指物理及/或电性连接。再者,”电性连接”或”耦合”是可为二元件间存在其他元件。
图1是本发明一实施例中晶圆封装元件100的俯视示意图。图2是根据图1中割面线2绘示的剖面示意图。请参照图1以及图2,晶圆封装元件100包括基板110、第一晶圆120以及第一导电层130。第一晶圆120配置在基板110上,且第一导电层130配置在第一晶圆120上。亦即第一晶圆120位于第一导电层130以及基板110之间。
举例而言,本实施例的第一晶圆120可以是动态随机存取内存(dynamic randomaccess memory,DRAM)晶圆,基板110可以是印刷电路板(printed-circuit board,PCB)。然而,本发明并不限于此。请参照图2,基板110包括第一上表面111以及第一接垫112,且第一接垫112配置在第一上表面111。基板110的第一上表面111面朝上并机构上支撑第一晶圆120。
基板110的第一上表面111电性连接配置其上的第一晶圆120。晶圆封装元件100更包含第一接线150以及第二接线160。第一晶圆120包括第二上表面121以及配置于第二上表面121的第二接垫122。进一步而言,在本实施例中,第一导电层130配置在第二上表面121,且第一接线150以及第二接线160各自连接在第一导电层130的相对两侧。
参照图2,第一接线150连接第一接垫112以及第一导电层130,且第二接线160连接第一导电层130以及第二接垫122,且第一导电层130的导电上表面131提供一个宽广的连接区域给第一接线150以及第二接线160。此外,在本实施例的晶圆封装元件100中,大电流信号可以经由第一导电层130传输,因此可以避免信号的失真以及噪声。
在本发明的一些实施例中,晶圆封装元件100还可以包括第三接线140。每个第三接线140具有两个彼此相反的端点,其各自连接至第一上表面111的这些第一接垫112的其中之一以及第二上表面121上的这些第二接垫122的其中之一。第三接线140可以例如是由黄金所制成的细线,且第一导电层130的材质可以包含例如是铜或铝的金属,或是任何其他具有低阻抗的材质,且第一导电层130的厚度落在60微米(micrometer,μm)至100微米的范围。因此,本实施例的第一导电层130可以加强基板110以及第一晶圆120之间的连接。换句话说,第三接线140是第一接垫112和第二接垫122之间的并联线路的一个分支,而第一接线150、第一导电层130以及第二接线160组成并联线路的另一分支。进一步而言,相较于厚度较低的第三接线140,第一导电层130提供阻抗较低的电性连接。通过上述设置,本实施例的晶圆封装元件100可以进一步避免IR压降。
具体而言,在本实施例中,第二接垫122沿着第二上表面121的中间线排列。第一导电层130在第二上表面121的投影区域和第三接线140在第二上表面121的投影区域彼此重叠。
举例而言,请参照图1,第三接线140还连接提供与第一接垫112所提供的信号不同的接垫113。
相较于第三接线140,第一导电层130在第一晶圆120的第二上表面121上具有宽度更大的较大分布区域,因此可以提升第一接垫112和第二接垫122之间的连接。
请参照图2,在本实施例中,制作晶圆封装元件100包括配置第一晶圆120在基板110上;形成连接第一接垫112和第二接垫122的第三接线140;配置第一导电层130在第一晶圆120上;形成连接第一接垫112和第一导电层130的第一接线150;形成连接第一导电层130和第二接垫122的第二接线160。
进一步而言,本实施例的晶圆封装元件100包括粘接层170,且粘接层170在配置第一导电层130之前设置于晶圆封装元件100。请参照图2,粘接层170设置在第一导电层130和第三接线140之间,且粘接层170形成第一导电层130和第三接线140之间的绝缘。换句话说,粘接层170包括绝缘材料,且粘接层170在第一导电层130和第三接线140之间可以避免短路。
因此,本实施例的第三接线140穿过第一导电层130和第二上表面121之间的区域,且粘接层170在第一导电层130下覆盖第三接线140。换句话说,本实施例的各第三接线140有一部分位于第一导电层130和第二上表面121之间。然而,本发明并不限于此。
图3是本发明另一实施例中晶圆封装元件100A的剖面示意图。请参照图3,本实施例制作晶圆封装元件100A的方法包括配置第一晶圆120在基板110上;配置第一导电层130在第一晶圆120上;形成多个连接第一接垫112和第一导电层130的第一接线150;形成多个连接第一导电层130和第二接垫122的第二接线160;形成连接第一接垫112和第二接垫122的第三接线140。
因此,晶圆封装元件100A的第三接线140跨过第一导电层130,且第一导电层130配置在第三接线140和第一晶圆120的第二上表面121之间。换句话说,第三接线140位于第一导电层130的上方。在本实施例中,粘接层170可以配置在第一导电层130的导电上表面131,借以在第一导电层130和第三接线140之间形成绝缘。
参照图1,在本实施例中,第一接垫112接地或是连接到一供应电源的接地电压,且第二接垫122是第一晶圆120的接地接垫,因此可以避免IR压降或失真。换句话说,本实施例的第一导电层130可以在基板110和第一晶圆120之间传递接地信号。
在本发明的另一实施例中,第一导电层130也可以在基板110和第一晶圆120之间传递例如是Vdd的电源信号。图4是本发明再一实施例中晶圆封装元件100B的俯视示意图。图5是根据图4中割面线5所绘的晶圆封装元件100B的剖面示意图。晶圆封装元件100B包括基板110、位于第一上表面111的第一接垫112、第一晶圆120、位于第二上表面121的第二接垫122、第一导电层130、第三接线140、第一接线150以及第二接线160,上述元件类似于上述实施例中的晶圆封装元件100。此外,晶圆封装元件100B的粘接层170可以配置在第一导电层130和第二上表面121之间,以形成第一导电层130和第三接线140之间的绝缘。
进一步而言,晶圆封装元件100B的第一导电层130配置在第一晶圆120的第二上表面121的另一区域,对应至第一接垫112的位置。在本实施例中,每个第一接垫112连接至供应电源50,且第二接垫122为第一晶圆120的电源供应接垫。换句话说,在基板110和第一晶圆120之间,第一导电层130、第一接线150以及第二接线160可以传递Vdd信号,借以避免IR压降以及信号失真。
在本发明的又一实施例中,晶圆封装元件还可以包括另外一个导电层配置在第一晶圆上。图6是根据本发明又一实施例中晶圆封装元件100C的俯视示意图。图7是根据图6中割面线7所绘的晶圆封装元件100C的剖面示意图。图8是根据图6中割面线8所绘的晶圆封装元件100C的剖面示意图。在本实施例中,晶圆封装元件100C包括基板110、第一接垫112、第一晶圆120、第二接垫122、第三接线140、第一接线150以及第二接线160,上述元件类似于上述实施例中的晶圆封装元件100。
进一步而言,晶圆封装元件100C还包括第二导电层180,其配置在第一晶圆120的第二上表面121,且第一晶圆120包括配置在第二上表面121的第四接垫124。参照图6,第二接垫122配置在第二上表面121的中间,且第二接垫122和第四接垫124的分布区域位于第一导电层130在第二上表面121的投影区域以及第二导电层180在第二上表面121的投影区域之间。
换句话说,在第一晶圆120上的第二接垫122和第四接垫124位于第一导电层130和第二导电层180之间,且第四接垫124和第二接垫122对齐排列。具体而言,本实施例中第一导电层130和第二导电层180的分布区域彼此不覆盖。换句话说,第一导电层130和第二导电层180之间间隔一顶距离。
此外,晶圆封装元件100C还包括第三接垫114、第六接线190、第四接线200以及第五接线210。晶圆封装元件100C的第三接垫114配置在基板110的第一上表面111,且每个第六接线190连接这些第三接垫114的其中之一以及这些第四接垫124的其中之一。第四接线200连接第三接垫114以及第二导电层180的一侧,而第五接线210连接第四接垫124以及第二导电层180的另一侧。换句话说,第六接线190以及由第四接线200、第二导电层180以及第五接线210组成的线路形成并联电路连接在第三接垫114和第四接垫124之间。因此,晶圆封装元件100C的第一导电层130和第二导电层180都可以提供良好的电性连接,且可以各自传输不同的信号。
举例而言,在本实施例中,第一接垫112接地,且第二接垫122是第一晶圆120的接地接垫。每个第三接垫114连接至供应电源50,且第四接垫124是第一晶圆120的电源接垫。换句话说,在本实施例中,第一导电层130可以在基板110和第一晶圆120传递接地信号(GND),且第二导电层180可以在基板110和第一晶圆120之间传递电源信号(Vdd),借以避免两个信号的IR压降以及信号失真。
在本发明的另一实施例中,晶圆封装元件可以包含重新布线层(RDL)。在本实施例中,重新布线层是第一晶圆上外加的金属层,使第一晶圆的第二接垫可以延伸至第一晶圆的其他位置,以便在必要时在其他位置可以轻易连接第二接垫。图9是本发明另一实施例中晶圆封装元件100D的剖面示意图。晶圆封装元件100D包括基板110、第一晶圆120、第一导电层130、第一接线150以及第二接线160,上述元件类似于上述实施例中的晶圆封装元件100。此外,晶圆封装元件100D包括重新布线层142,其配置在第一晶圆120的第二上表面121,且重新布线层142连接第三接线140以及第二接垫122。本实施例的每个重新布线层142连接这些第一接垫112的其中之一至这些第二接垫122的其中之一时,具有较大面积的第一导电层130可以在基板110和第一晶圆120之间提供较佳的连接。
本发明实施例的再一实施例的晶圆封装元件可以应用至堆栈型晶圆封装元件。堆栈型晶圆封装元件是半导体封装装置,其利用三维封装技术来垂直堆栈多个晶圆。举例而言,上述装置可以应用于例如是内存模块、记忆卡、可携式储存碟等储存装置。
图10是本发明再一实施例中晶圆封装元件100E的剖面示意图。请参照图10,晶圆封装元件100E包括基板110、第一接垫112、第一晶圆120、第二接垫122、第一导电层130、第三接线140、第一接线150以及第二接线160,上述元件类似于上述实施例的晶圆封装元件100。进一步而言,晶圆封装元件100E还包括第二晶圆220、第三导电层230、第七接线144、第八接线152以及第九接线162。
在本实施例中,第二晶圆220配置在第一晶圆120上,且第二晶圆220包括第三上表面221以及配置于第二晶圆220的第三上表面221的第五接垫222。第三导电层230配置在第二晶圆220的第三上表面221。进一步而言,粘接层174设置在第二晶圆220上,位于第三上表面221以及第三导电层230之间。粘接层172设置在第一导电层130上,位于导电上表面131以及第二晶圆220之间。
参照图10,第七接线144连接第一接垫112以及第五接垫222,且第八接线152连接第一接垫112以及第三导电层230的一侧,且第九接线162连接第五接垫222以及第三导电层230的另一侧,已同时提供加强的电性连接至第一晶圆120以及第二晶圆220。
Claims (12)
1.一种晶圆封装元件,其特征在于,所述晶圆封装元件包括:
基板,包括第一上表面以及多个第一接垫,其中所述多个第一接垫配置于所述第一上表面;
第一晶圆,配置于所述第一上表面,所述第一晶圆包括第二上表面以及多个第二接垫,其中所述多个第二接垫配置于所述第二上表面;
第一导电层,配置于所述第二上表面;
多个第一接线,连接所述多个第一接垫至所述第一导电层;
多个第二接线,连接所述多个第二接垫至所述第一导电层,其中每个所述第一接线和每个所述第二接线各自连接所述第一导电层的相对两侧;以及
多个第三接线,连接所述多个第一接垫和所述多个第二接垫,且所述多个第三接线绕过所述第一导电层,其中所述多个第三接线各自具有位于所述第一导电层以及所述第二上表面之间的部分,所述多个第三接线各自具有两端点分别连接所述多个第一接垫的相应一者与所述多个第二接垫的相应一者,其中连接所述多个第三接线的每一所述第一接垫分别通过所述多个第一接线的相应一者连接该第一导电层,连接所述多个第三接线的每一所述第二接垫分别通过所述多个第二接线的相应一者连接该第一导电层。
2.如权利要求1所述的晶圆封装元件,其特征在于,所述第一导电层在所述第二上表面的投影区域与所述多个第一接线在所述第二上表面的投影区域重叠。
3.如权利要求1所述的晶圆封装元件,其特征在于,还包括:
粘接层,配置在所述第一导电层以及所述多个第三接线之间,其中所述粘接层形成所述第一导电层以及所述多个第三接线之间的绝缘。
4.如权利要求1所述的晶圆封装元件,其特征在于,所述多个第一接垫接地,且所述多个第二接垫为所述第一晶圆的接地接垫。
5.如权利要求1所述的晶圆封装元件,其特征在于,所述多个第一接垫连接至供应电源,且所述多个第二接垫为所述第一晶圆的电源接垫。
6.如权利要求1所述的晶圆封装元件,其特征在于,所述多个第二接垫沿着所述第二上表面的中间线配置。
7.如权利要求1所述的晶圆封装元件,其特征在于,所述第一晶圆包括:
多个第四接垫,配置于所述第二上表面,
所述晶圆封装元件包括:
多个第三接垫,配置于所述第一上表面;
第二导电层,配置于所述第二上表面;
多个第四接线,连接所述第二导电层至所述多个第三接垫;以及
多个第五接线,连接所述第二导电层至所述多个第四接垫,
其中每个所述第四接线以及每个所述第五接线各自连接所述第二导电层的相对两侧。
8.如权利要求7所述的晶圆封装元件,其特征在于,还包括:
多个第六接线,连接所述多个第三接垫以及所述多个第四接垫,且所述多个第六接垫绕过所述第二导电层。
9.如权利要求7所述的晶圆封装元件,其特征在于,所述多个第二接垫以及所述多个第四接垫位于所述第一导电层以及所述第二导电层之间。
10.如权利要求7所述的晶圆封装元件,其特征在于,所述多个第四接垫实质上与所述多个第二接垫对齐。
11.如权利要求7所述的晶圆封装元件,其特征在于,所述多个第一接垫接地,且所述多个第二接垫为所述第一晶圆的接地接垫,且所述多个第三接垫连接至供应电源,且所述多个第四接垫为所述第一晶圆的电源接垫。
12.如权利要求1所述的晶圆封装元件,其特征在于,还包括:
第二晶圆,配置于所述第一晶圆上,所述第二晶圆包括第三上表面以及多个第五接垫,所述多个第五接垫配置于所述第三上表面;
第三导电层,配置于所述第三上表面;
多个第七接线,连接所述多个第一接垫至所述多个第五接垫,且所述多个第七接线绕过所述第三导电层;
多个第八接线,连接所述多个第一接垫至所述第三导电层;以及
多个第九接线,连接所述多个第五接垫至所述第三导电层,
其中每个所述第八接线以及每个所述第九接线各自连接所述第三导电层的相对两侧。
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TW406342B (en) * | 1998-01-02 | 2000-09-21 | Texas Instruments Inc | Thin chip-size integrated circuit package and method of fabrication |
US20090032973A1 (en) * | 2007-07-31 | 2009-02-05 | Elpida Memory, Inc. | Semiconductor stack package having wiring extension part which has hole for wiring |
US20120068338A1 (en) * | 2010-09-16 | 2012-03-22 | Tessera Research Llc | Impedance controlled packages with metal sheet or 2-layer rdl |
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JP2005277356A (ja) * | 2004-03-26 | 2005-10-06 | Sanyo Electric Co Ltd | 回路装置 |
US7786572B2 (en) * | 2005-09-13 | 2010-08-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | System in package (SIP) structure |
US8084849B2 (en) * | 2007-12-12 | 2011-12-27 | Stats Chippac Ltd. | Integrated circuit package system with offset stacking |
TWI446504B (zh) * | 2010-04-20 | 2014-07-21 | Silergy Corp | Chip package structure and packaging method thereof |
CN109891584A (zh) * | 2017-09-14 | 2019-06-14 | 深圳市汇顶科技股份有限公司 | 芯片封装结构及方法、电子设备 |
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2019
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TW406342B (en) * | 1998-01-02 | 2000-09-21 | Texas Instruments Inc | Thin chip-size integrated circuit package and method of fabrication |
US20090032973A1 (en) * | 2007-07-31 | 2009-02-05 | Elpida Memory, Inc. | Semiconductor stack package having wiring extension part which has hole for wiring |
US20120068338A1 (en) * | 2010-09-16 | 2012-03-22 | Tessera Research Llc | Impedance controlled packages with metal sheet or 2-layer rdl |
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US20230207512A1 (en) | 2023-06-29 |
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