1282133 九、發明說明： 【發明所屬之技術領域】 本發明係有關於-種打線方式，特別 ::?打線方式’其可以改善内外層導線交錯甚至造 【先前技術】 在-般的封裝餘巾，積體電路晶#必需要與魏 導 架做-電路的聯接才能發揮電子峨傳遞的雜。_般=:綠 #^(Wire Bonding) ^ #^^#^(Tape Aut〇mated ^ 與覆晶接合(Fiip chip)為半導體封裝製程中的電路連線方/而= 以打線接合最為普紐H了線接合係在麵電路晶^ 電路板齡狀彳4 ’將金祕歧金料依„錢魏^依^ 在積體電路晶片與導縣或是縣基板的齡上而形成電路聯结 達到傳遞電子訊號的功能。 第-A圖為-以打線方式形成電路聯結的傳統雖結構1〇。此一 封裝結構ίο係由一具有内層銲墊14與外層銲墊16之積體電路晶片12 • 與一封裝基板18黏結而成。一接地環20、-電源環22與數個訊號接 墊或金手指（finger)24依序由内向外設置於封裝基板18上積體電路晶 片12周圍。參照第一 B圖，其打線方式為先將外層銲墊16依產品之 電路設計打線形成金屬線26連接到接地環2〇或是電源環22上。接著， 如第一 C圖所示，將内層銲墊14打線形成金屬線28連接到封裝基板 18上對應的訊號接墊24上而完成積體電路晶片12與封裝基板18之電 路聯結。此一打線方式具有一通則，稱為打線接合設計規則（wire bonding design rule)，即外層銲墊16皆設計為與接地環20或電源 環22聯結，並且需先打線聯結；内層銲墊μ則皆設計與訊號接墊24 做電路聯結，並且其打線順序在外層銲墊16之後。在封裝製程中，遵 1282133 f1282133 IX. Description of the invention: [Technical field of the invention] The present invention relates to a type of wire bonding, in particular:: a wire-punching method which can improve the inner and outer wire wires to be staggered or even [previously] in a general package , integrated circuit crystal # must be connected with the Wei guide - circuit to play the electronic 峨 transmission of impurities. _般=:绿#^(Wire Bonding) ^ #^^#^(Tape Aut〇mated ^ and FIP chip are the circuit connection in the semiconductor packaging process / and = wire bonding H wire bonding system in the surface circuit crystal circuit board age 彳 4 'Golding the secret gold material according to the "Qian Wei ^ ^ ^ in the integrated circuit chip and the county or county substrate age to form a circuit connection The function of transmitting the electronic signal is achieved. The first-A diagram is a conventional structure for forming a circuit connection by wire bonding. The package structure is formed by an integrated circuit chip 12 having an inner pad 14 and an outer pad 16. • Bonded to a package substrate 18. A ground ring 20, a power ring 22 and a plurality of signal pads or fingers 24 are disposed from the inside to the outside on the package substrate 18 around the integrated circuit wafer 12. Referring to FIG. B, the wire bonding method is to first connect the outer pad 16 to the grounding ring 2 or the power ring 22 according to the circuit design of the product. Then, as shown in FIG. The inner pad 14 is wired to form a metal line 28 connected to the corresponding signal pad 24 on the package substrate 18 to complete The integrated circuit chip 12 is coupled to the circuit of the package substrate 18. This wire bonding method has a general rule called a wire bonding design rule, that is, the outer pad 16 is designed to be connected to the ground ring 20 or the power ring 22 Bonding, and need to be wire bonding first; the inner pad μ is designed to be circuit-coupled with the signal pad 24, and its wire bonding sequence is after the outer pad 16. In the packaging process, according to 1282133 f
I 循此打線接δ ό又计規則（wire b〇n(jing design rule)，將使得内層 録塾14上之金屬線26與外層銲墊16上之金屬線28彼此之間不會接 觸而發生短路，如第一 C圖所示。 然而’此一打線方式與通則僅僅是用於理想狀態，實際上，許多的 積體電路晶片在設計或製作時，或因應電路設計的需要，或不了解上 述打限制成之通則’往往並未將欲與接地環2〇或電源環22之銲墊製 作於外側而是製作於内側。因此，如同第二圖所示，積體電路上有一 内層銲塾14與外層銲墊16 一樣分別打線形成金屬線沈與金屬線26 . 聯結接地環20或電源環22。如此一來，將造成金屬線28與金屬線26 接觸而造成短路，即使在打線時金屬線28與金屬線26並未接觸，但 其彼此之間距離甚近容易造成在其後的封膠製程中，金屬線28與金屬 線26夂壓迫而接觸造成短路。此一因金屬線接觸所照成的短路將造成 封裝產品的損壞，以及封裝良率的降低。 鑑於上述問題，通常封裝厥在遇到此一問題時大多數的做法是改 變封裝基板上的電路配置以解決此一問題，或是直接退貨廠商。然而， 無論是採取哪一種方法都無可避免的造成成本或收入的損失。因此， 需要一種打線方式，特別是一種多層銲墊之打線方式，來解決因為 运反上述打線接合設計規則（wire bonding design rule)所引起金屬 導線相接觸而導致短路問題，進而減少產品的損失並且增加打線製程 的可變性。 【發明内容】 鑑於上述的問題，本發明之一目的為提供一改良的多層 知墊之打線方式。此一多層録墊之打線方式可以改善因為積體 電路晶片上銲墊為因應設計需要，或因設計錯誤而違反打線接 合设计規則(wire bonding design rule)導致金屬導線或在其後之 封膠製程中相接觸造成短路問題，以及減少因短路所造成產品 1282133 的品質不良，產品損失以及良率減低等問題。 本發明之另一目的，在提供一改良的多層銲墊之打線方 式，以解決因為積體電路晶片上銲墊為因應設計需要，或因設 计錯誤而違反打線接合設計規則（wire bonding design rule)導致需 變更封裝基版或重新製作封裝基板的問題，以及因需變更或重新製 作封裝基板而導致成本增加，製成時間延長等問題。 本發明之另一目的，在提供一改良的多層銲墊之打線方 式’其不會大幅地受限於打線接合設計規則（wire bonding design > rule)，從而增加積體電路晶片上銲墊設計的可變性，以及減 少積體電路晶片的電路佈局受限於銲墊配置的幅度而擁有更 多的可變性。 根據上述目的，本發明提供一改良的多層銲墊之打線方 式。首先，提供一具有複數個外層銲墊與複數個内層銲墊之晶 片，這些内層銲墊包含一第一銲墊，該些外層銲墊包含一第二 銲墊，且第一銲墊與第二銲墊具相同電性功能。接著，提供一 具有一置晶區、複數個第一接墊及複數個第二接墊之基板，並 | 且第二接墊相對於第一接墊離置晶區較遠。固定此一晶片於基 板的置晶區中之後，打線接合晶片上之第一銲墊與第二銲墊形 成一電路聯結。接著，打線接合晶片上之第二銲墊與基板上其 中^個第一接墊打線’然後，打線接合晶片上之其它外層銲墊 與基板紹其它第一接墊’以及打線接合晶片上之其它内層銲墊 與基板上其他第二接塾。 利用上述本發明之多層銲墊之打線方式，可使得即使在 違反打線接合設計規則（wire bonding design rule)下進行打線製 成，仍然可以使各個金屬導線不會相接觸或在其後之封膠製程 中而造成短路問題，並且無需變更或重新製作封裝基板，故不 會橡得成本增加。 【實施方式】 本發明的一些實施例詳細描述如下。然而，除了該詳細描 述外，本發明還可以廣泛地在其他的實施例施行。亦即，本發 明的範圍不受已提出之實施例的限制，而以本發明提出之申請 專刺範圍為準。其次，當本發明之實施例圖示中的各元件或結 構以單一元件或結構描述說明時，不應以此作為有限定的認 知，即如下之說明未特別強調數目上的限制時本發明之精神與 應用範圍可推及多數個元件或結構並存的結構與方法上。再 I，在本說明書中，各元件之不同部分並沒有完全依照尺寸繪 圖’某些尺度與其他相關尺度相比或有被誇張或是簡化，以提 供更清楚的描述以增進對本發明的理解。而本發明所沿用的現 有技薺，在此僅做重點式的引用，以助本發明的闡述。 參照第三A圖至第三D圖，其展示了本發明之一較佳實 施例之打線方式及製程。首先，如第三A圖所示，提供> 晶片 102與一具一置晶區hi之基板11Q，並且將晶片1〇2固定於 基板111的置晶區内。此一晶片1〇2上有數個内層銲墊1〇4與 數個外層銲墊108，這些内層銲墊1〇4至少有一個為第一銲墊 106，以及這些外層銲墊1〇8至少一個為第二銲墊1〇7，並且 第一銲墊106與第二銲墊1〇7具有相同的電性功能。另外，基 板110上除了有置晶區111外，並且在置晶區ln外為設置有 數個第一接墊112、1U與數個第二接墊ία，第二接墊116 相較於第一接墊112、Π4距離置晶區比較遠。參照第三b圖， 其中所展示的為第三A圖之晶片102與基板11〇接合之側視 圖’並且可以由其中得之上述第一銲墊1〇6、第二銲墊1〇7、 第一接墊112、114以及第二接墊Π6分別在晶片1〇2與基板 1282133 . 1 110上之相對位置。 接著’參照第三c圖，以打線接合方式形成一金屬導線 118電性連接第一銲塾1〇6與第二鲜墊1〇7。然後，如同第三 D圖所示，同樣則了線接合方式形成—金屬導線⑽電性連接 第二銲墊107與第一接墊112。接著，先打線結合晶片1〇2上 其餘外層銲墊108與基板11〇上第一接墊112、114,以形成 金屬導線122電性連接其餘外層銲墊1〇8與基板11〇上第一接 墊112、114，但是再其他實施例中，也可以依產品設計與需 求將邛伤外層#塾108與部份第二接塾IK打線接合。雖然在 第二D圖中所示之金屬導線丨22為電性連接外層銲墊1〇8與第 一接墊112，但實際上，仍有其他外層銲墊1〇8依產品需求或 设计分別與第一接墊112或Π4電性連接，因第三D圖為一側 視圖而被遮住無法顯示出來。然後再打線結合晶片1〇2上其餘 内層銲墊104與基板11〇上第二接墊116，以形成金脣導線124 電性連接其餘内層銲墊1〇4與基板11〇上第二接墊116。如此 了來，將可以使得内層銲墊可以依產品設計或是需求電性連接 第一銲墊，增加各種打線製程之可能性與變化性。 上述晶片10上之第一銲墊106與第二銲墊1〇7係為接地 /電源銲墊，而其餘内層銲墊104與外層銲墊log分別為气號 銲墊以及接地/電源銲墊。此外，基板11〇上之第一接墊 與第一接墊114分別為接地接墊與電源接墊，此一接地接塾與 電源接墊可以同本實施例於第三A圖所示，係分別為一框型^ 連貫結構，或是如同本發明之其它實施例中，為數個分離不連 貫且圍繞置晶區111周圍之接墊結構。再者，基板11〇上之第 二接塾116為訊號銲塾用以傳遞外界與晶片間之訊贫。 此外，上述所述之打線接合方式可以採用超音波接合 9 1282133 vI 循 打 ό 规则 规则 jing jing jing jing jing jing jing jing jing jing jing jing jing jing jing jing jing jing jing jing jing jing jing jing jing jing jing jing jing jing jing jing jing jing jing jing jing jing jing jing jing jing jing jing jing jing Short circuit, as shown in Figure C. However, 'this line method and general rule are only used for ideal conditions. In fact, many integrated circuit chips are designed or manufactured, or need to meet the needs of circuit design, or do not understand The general rule of the above limitation is that the solder pads of the grounding ring 2 or the power supply ring 22 are not formed on the outer side but are formed on the inner side. Therefore, as shown in the second figure, the integrated circuit has an inner layer soldering pad. 14, as with the outer pad 16, respectively, to form a metal wire sink and a metal wire 26. The grounding ring 20 or the power ring 22 is connected. As a result, the metal wire 28 is brought into contact with the metal wire 26 to cause a short circuit even when the wire is wired. The wire 28 is not in contact with the metal wire 26, but the distance between them is very close to each other, so that in the subsequent sealing process, the wire 28 and the wire 26 are pressed and contacted to cause a short circuit. This is due to the metal wire contact. The short circuit will be made Damage to packaged products, as well as reduced package yield. In view of the above problems, most of the problems encountered in packaging this problem are to change the circuit configuration on the package substrate to solve this problem, or to directly return the manufacturer. However, no matter which method is adopted, it inevitably causes cost or income loss. Therefore, a wire bonding method, especially a multi-layer soldering wire bonding method, is required to solve the above-mentioned wire bonding design rule (wire bonding). The design rule) causes the metal wires to contact to cause a short circuit problem, thereby reducing the loss of the product and increasing the variability of the wire bonding process. SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide an improved multilayered pad. Wire-laying method. The wiring method of this multi-layer recording pad can be improved because the pad on the integrated circuit chip is designed to meet the design requirements, or the wire bonding design rule is caused by the design error, resulting in or behind the wire bonding design rule. Contact in the encapsulation process causes short circuit problems and reduces short circuit The product 1282133 has poor quality, product loss and yield reduction. Another object of the present invention is to provide an improved multi-layer pad bonding method to solve the problem because the pad on the integrated circuit wafer is designed accordingly. Or, due to a design error, a violation of the wire bonding design rule, the problem of changing the package base or re-creating the package substrate, and the cost increase due to the need to change or re-make the package substrate, and the production time is prolonged. A further object of the present invention is to provide an improved method of wire bonding a multilayer pad which is not significantly limited by wire bonding design > rule, thereby increasing the integrated circuit die. The variability of the pad design and the reduced circuit layout of the integrated circuit die are limited by the extent of the pad configuration and have more variability. In accordance with the above objects, the present invention provides an improved wiring pattern for a multilayer pad. First, a wafer having a plurality of outer pads and a plurality of inner pads is provided. The inner pads include a first pad, the outer pads include a second pad, and the first pad and the second pad The pads have the same electrical function. Next, a substrate having a crystallographic region, a plurality of first pads, and a plurality of second pads is provided, and the second pads are far apart from the first pads. After the wafer is fixed in the seeding region of the substrate, the first pad on the wire bonding wafer forms a circuit connection with the second pad. Then, bonding the second pad on the wafer to the first pad on the substrate and then bonding the other outer pads on the wafer to the other first pads on the substrate and the other on the bonding die The inner pad is connected to the other second substrate on the substrate. By using the above-mentioned multi-layer soldering pad of the present invention, the wire bonding can be made even in violation of the wire bonding design rule, and the metal wires can not be contacted or sealed behind. The short circuit problem occurs in the process, and there is no need to change or re-create the package substrate, so the cost of the rubber is not increased. [Embodiment] Some embodiments of the present invention are described in detail below. However, the present invention may be widely practiced in other embodiments in addition to the detailed description. That is, the scope of the present invention is not limited by the embodiments which have been proposed, and the scope of the application of the present invention is subject to the scope of the application. In the following, when the elements or structures in the embodiments of the present invention are described in terms of a single element or structure, the present invention should not be construed as limited. The spirit and scope of application can be derived from the structure and method in which many components or structures coexist. Further, in the present specification, the various components of the various components are not fully described in terms of the dimensions. Some of the dimensions are exaggerated or simplified in comparison with other related dimensions to provide a clearer description to enhance the understanding of the present invention. The prior art, which is used in the present invention, is only referred to herein by reference to the accompanying drawings. Referring to Figures 3A through 3D, there is shown a wire bonding method and process of a preferred embodiment of the present invention. First, as shown in Fig. 3A, a wafer 102 and a substrate 11Q having a crystal region hi are provided, and the wafer 1 is fixed to the crystal region of the substrate 111. The wafer 1 〇 2 has a plurality of inner pads 1 〇 4 and a plurality of outer pads 108. at least one of the inner pads 1 〇 4 is a first pad 106, and at least one of the outer pads 1 〇 8 It is the second pad 1〇7, and the first pad 106 has the same electrical function as the second pad 1〇7. In addition, the substrate 110 has a plurality of first pads 112, 1U and a plurality of second pads ία disposed outside the crystal region ln, and the second pads 116 are compared with the first interface. The pads 112 and Π4 are relatively far from the crystallizing area. Referring to the third b-figure, the side view of the wafer 102 bonded to the substrate 11A of the third A-picture is shown and can be obtained from the first pad 1〇6, the second pad 1〇7, The first pads 112, 114 and the second pads 6 are respectively located at opposite positions of the wafer 1 2 and the substrate 1282 133.1. Next, referring to the third c-figure, a metal wire 118 is formed by wire bonding to electrically connect the first bonding pad 1〇6 and the second fresh pad 1〇7. Then, as shown in the third D diagram, the wire bonding method is also formed. The metal wires (10) are electrically connected to the second pads 107 and the first pads 112. Next, first bonding the remaining outer pads 108 on the wafer 1〇2 and the first pads 112 and 114 on the substrate 11 to form the metal wires 122 electrically connected to the remaining outer pads 1〇8 and the substrate 11 The pads 112, 114, but in other embodiments, the scratched outer layer #塾108 can also be wire-bonded to a portion of the second joint IK according to product design and requirements. Although the metal wire 22 shown in the second figure D is electrically connected to the outer pad 1 〇 8 and the first pad 112, in fact, there are still other outer pads 1 〇 8 depending on product requirements or design. It is electrically connected to the first pad 112 or the crucible 4, and is blocked by the third D picture as a side view and cannot be displayed. Then, the remaining inner layer pads 104 on the wafer 1〇2 and the second pads 116 on the substrate 11 are bonded to form the gold lip wires 124 electrically connected to the remaining inner layer pads 1〇4 and the second pads on the substrate 11 116. In this way, the inner pad can be electrically connected to the first pad according to product design or demand, thereby increasing the possibility and variability of various wire bonding processes. The first pad 106 and the second pad 1〇7 on the wafer 10 are ground/power pads, and the remaining inner pad 104 and outer pad log are respectively an air pad and a ground/power pad. In addition, the first pad and the first pad 114 on the substrate 11 are respectively a ground pad and a power pad. The ground pad and the power pad can be the same as in the third embodiment. They are respectively a frame type, a continuous structure, or, as in other embodiments of the present invention, a plurality of spacer structures that are discontinuously spaced and surround the periphery of the crystallographic region 111. Moreover, the second interface 116 on the substrate 11 is a signal soldering device for transmitting the poor between the outside and the wafer. In addition, the above-mentioned wire bonding method can adopt ultrasonic bonding 9 1282133 v
I (Ultrasonic Bonding; U/S)、壓接合（Thermocompression Bonding; T/S)以及熱超音波壓接合（Thermosonic Bonding; T/S)等方式來實施。在本實施例中，以打線接合第一鲜塾i〇6 與第二銲墊107，與打線接合第二銲墊1〇7與第一接墊112， 其在第二銲墊107上採用同一銲點，即在第二銲墊上，電性連 接第二銲墊107與第一接墊丨12之金屬導線120打線在金屬導 線118與第二銲墊107之銲點上而相互連接，但不以此為限。 然而，如同第四A圖與第四b圖所示，其分別為本發明之另一 實施例之上視圖與側視圖，其中電性連接第一銲墊1〇6與第二 銲墊107之金屬導線118，與電性連接第二銲墊1〇7與第一接 > 墊112之金屬導線120在第二銲墊107上具有不同的銲點。換 言之，即金屬導線118與金屬導線120在第二銲墊1〇7上具有 不同的銲點，因此藉著第二銲墊107而電性連接金屬導線118 與金屬導線120〇 參照第五A圖至第五C圖，其為本發明之另一個實施例 之多層銲墊之打線方式。首先，如第五A圖所示，提供一晶片 102與一具一置晶區ill之基板11〇，並且將晶片1〇2固定於 基板111的置晶區内。此一晶片102上有兩層或兩層以上的内 層銲墊104，每一層皆包含有複數個内層銲墊1〇4，此外，晶 片102還具有數個外層銲墊1〇8。這些内層銲墊1〇4中，具有 至少一個第一銲墊106與一第三銲墊109，以及這些外層銲墊 108中，具有至少一個第二銲墊1〇7。再者，第一鋅塾1〇6、 弟二銲塾107以及第三録塾109具有相同的電性功能，並且皆 為接地/電源録塾’此外，其餘内層鮮塾1〇4皆為訊號銲塾， 而其餘外層銲塾108皆為接地/電源銲墊。在本實施例中，第 一銲墊107相較於第三銲墊109較為内層，即為較靠近晶片 10 2之中心，但不以此為限，而在其他實施例中第一銲墊1 〇 7 與第三銲墊109也可以設置一產品設計或需求而設置於同一 1282133 層。另外’基板iio上除了有置晶區ill外，並且在置曰巴 111外為設置有數個第一接墊112、114即接地接墊與電源^ 墊，以及設置有數個第二接墊116即訊號接墊，第二接墊116 相較於第一接墊112、114距離置晶區比較遠。 參照第五B圖，以打線接合方式形成一金屬導線117電 性連接第一鋅塾106與第三銲墊1〇9，接著，再以打線接合方 式形成一金屬導線11Θ電性連接第.三銲墊109與第二銲墊 107，然後，以打線接合方式形成一金屬導線12〇電性連接第 二銲墊107與第一接墊112。此一從第一銲墊106經第三銲墊 • 109、第二銲墊107而到達第一接墊112之電路聯結，使的位 於具有多層内層銲墊或外層銲墊之晶片1〇2中之較内層或最 内層銲墊，可以經由此一不需遵守打線接合設計規則（wire bondingdesignrule)之接駁方式，電性連接至基板n〇上接地/ 電源鋅塾112、114，並且不會造成内層銲塾與外層銲塾上金 屬導線彼此接觸發生短路問題。 參照第五c圖所示，同樣以打線方式接合晶片1〇2上其餘 外層銲墊108與基板11〇上第一接墊112、114，以形成金屬 φ 導線122電性連接其餘外層銲塾108與基板no上第一接塾 112 114即接地/電源接墊，但是再其他實施例中，也可以依 產2設計與需求將部份外層銲墊108與部份第二接墊116打線 接合。接著，依序以打線接合方式性成金屬導線124、126分 別墊性連接較外側之内層銲墊與第二接塾116即訊號接墊，以 及較内側之内層銲塾與第二接塾116。雖然，在第五C圖中所 示之金屬導線122為電性連接外層銲墊log與第一接墊112， 2實際上，仍有其他外層銲墊1〇8依產品需求或設計分別與第 一接塾112或114電性連接，因第五c圖為一側視圖而被遮住 無法顯示出來。 11 1282133 在本實施例中’打線接合第一銲塾106與第三銲塾i〇9， 以及打線接合第三銲墊丨〇9與第二銲墊107,其在第三銲墊109 上採用打線至同一銲點的方式，而打線接合第三銲墊109與第 二銲墊107，以及打線接合第二銲墊107與第一接墊Π2上， 其在第二銲墊107上採用打線至同一銲點的方式，但不以此為 限。參照第六圖，在本發明之其它實施例中，不論是打線接合 第一銲墊106與第三銲墊109，以及打線接合第三銲墊1〇9與 第二銲墊107，或是打線接合第三銲墊1〇9與第二銲塾ίο?， 以及打線接合第二銲墊107與第一接墊112上，其在第三銲墊 109與在第二銲墊107上皆採用打線至不同銲點的方式，即金 屬導線117、119、120皆不連接。或是依其需求在不違反本發 明之精神下，加以變化而採取打線至同一銲點方式與打線至不 同鮮點方式交互使用。 根據上述實施例，發明提供了一多層銲墊之打線方式，將 可以使得内層銲墊可以經由中間其它銲墊為過渡而依產品設 計^是需求電性連接第一銲墊，此一方式不會因不遵守打線接 合設計規則（wire bonding design ruie)造成内層銲墊與外層銲墊 上金屬導線彼此接觸發生短路問題，並增加各種打線製程之可 以上所述僅為本發明之較佳實施例，並非用以限定本發明 範f。/不違反本發明之精神，以及不脫離本發明 狀屬士/的1㊇内仍可以於以變化而加以實施，此等變化應 圍所界定明之㈣。因此，本發明之料係由下列巾請申請範 【圖式簡單說明】I (Ultrasonic Bonding; U/S), Pressure Bonding (T/S), and Thermosonic Bonding (T/S). In this embodiment, the first squeezing electrode 〇6 and the second bonding pad 107 are bonded by wire bonding, and the second bonding pad 1 〇 7 and the first bonding pad 112 are bonded to the bonding wire, and the same is used on the second bonding pad 107. Solder joints, that is, on the second bonding pad, the second bonding pads 107 and the metal wires 120 of the first bonding pads 12 are electrically connected to each other at the solder joints of the metal wires 118 and the second bonding pads 107, but not This is limited to this. However, as shown in the fourth A and fourth b, respectively, it is a top view and a side view of another embodiment of the present invention, wherein the first pad 1 〇 6 and the second pad 107 are electrically connected The metal wire 118 and the metal wire 120 electrically connected to the second pad 1〇7 and the first pad> pad 112 have different solder joints on the second pad 107. In other words, the metal wire 118 and the metal wire 120 have different solder joints on the second pad 1〇7, so the metal wire 118 and the metal wire 120 are electrically connected by the second pad 107. Referring to FIG. Up to FIG. 5C, which is a wire bonding method of a multilayer pad according to another embodiment of the present invention. First, as shown in FIG. 5A, a wafer 102 and a substrate 11 having a crystal-clear region ill are provided, and the wafer 1 is fixed to the crystal-crystalline region of the substrate 111. The wafer 102 has two or more inner pads 104, each of which includes a plurality of inner pads 1〇4, and the wafer 102 has a plurality of outer pads 1〇8. The inner pad 1 〇 4 has at least one first pad 106 and a third pad 109, and the outer pads 108 have at least one second pad 1 〇7. Furthermore, the first zinc crucible 1〇6, the second soldering crucible 107, and the third reel 109 have the same electrical function, and both are grounded/powered to record 'in addition, the remaining inner layers are 讯1〇4 are signals. The solder bumps, while the remaining outer solder pads 108 are ground/power pads. In this embodiment, the first pad 107 is closer to the inner layer than the third pad 109, that is, closer to the center of the wafer 102, but not limited thereto, and in other embodiments, the first pad 1 is used. The 〇7 and the third pad 109 may also be provided with the same design or requirement and disposed on the same 1282133 layer. In addition, the substrate iio has a crystal area ill, and a plurality of first pads 112, 114, that is, a ground pad and a power supply pad, and a plurality of second pads 116 are provided. The pads, the second pads 116 are relatively farther from the first crystal pads 112, 114 than the crystal regions. Referring to FIG. 5B, a metal wire 117 is electrically connected to the first zinc crucible 106 and the third bonding pad 1〇9 by wire bonding, and then a metal wire 11 is electrically connected by wire bonding. The pad 109 and the second pad 107 are then formed by wire bonding to form a metal wire 12 electrically connected to the second pad 107 and the first pad 112. The circuit from the first pad 106 through the third pad 117, the second pad 107 to the first pad 112 is connected to the wafer 1 〇 2 having a plurality of inner or outer pads. The inner layer or the innermost layer of the bonding pad can be electrically connected to the grounding/powering zinc crucible 112, 114 on the substrate n through the connection method of the wire bonding design rule, and does not cause The short circuit problem occurs when the inner layer soldering wire and the metal wire on the outer layer soldering wire are in contact with each other. Referring to FIG. 5C, the remaining outer pads 108 on the wafer 1 and the first pads 112 and 114 on the substrate 11 are also bonded in a wire bonding manner to form a metal φ wire 122 electrically connected to the remaining outer pads 108. The first interface 112 114 is the ground/power pad on the substrate no. However, in other embodiments, a portion of the outer pad 108 and a portion of the second pad 116 may be wire bonded according to the design and requirements. Then, the metal wires 124 and 126 are sequentially connected by wire bonding to connect the outer inner pad and the second contact 116, that is, the signal pads, and the inner inner solder and the second inner 116, respectively. Although the metal wire 122 shown in FIG. 5C is electrically connected to the outer pad pad and the first pad 112, 2 actually, there are still other outer pads 1〇8 according to product requirements or designs respectively. An interface 112 or 114 is electrically connected, and the fifth c is hidden in a side view and cannot be displayed. 11 1282133 in the present embodiment, 'wire bonding the first soldering pad 106 and the third bonding pad i〇9, and bonding the third bonding pad 9 and the second bonding pad 107, which are used on the third bonding pad 109 Wire-bonding to the same solder joint, and bonding the third pad 109 and the second pad 107, and bonding the second pad 107 and the first pad 2, and bonding the second pad 107 to the second pad 107 The same solder joint method, but not limited to this. Referring to the sixth embodiment, in other embodiments of the present invention, the first pad 106 and the third pad 109 are bonded by wire bonding, and the third pad 1〇9 and the second pad 107 are bonded by wire bonding, or the wire is bonded. Bonding the third bonding pad 1〇9 and the second bonding pad ίο?, and bonding the second bonding pad 107 and the first bonding pad 112, and applying the bonding on the third bonding pad 109 and the second bonding pad 107 The way to different solder joints, that is, the metal wires 117, 119, and 120 are not connected. Or, according to their needs, in the spirit of not infringing the spirit of the present invention, change the line and use the same solder joint method to interact with the line to different fresh points. According to the above embodiment, the invention provides a multi-layer soldering wire bonding method, which can make the inner layer bonding pad can be designed according to the product through the intermediate other bonding pads, and is required to electrically connect the first bonding pad, which is not The short circuit problem may occur due to the non-compliance with the wire bonding design ruie, and the metal wires on the outer layer and the outer layer are in contact with each other, and the various wire bonding processes may be added. The above is only a preferred embodiment of the present invention. It is not intended to limit the scope of the invention. It is also possible to carry out the changes without departing from the spirit of the invention and without departing from the scope of the invention. These changes are defined as (4). Therefore, the material of the present invention is requested by the following towel [simplified description]
12 1282133 第一A圖至第一 C圖為為傳統之多層銲墊打線方式之流程 圖。 第二圖為一傳統打線封裝結構之側視圖。 第三A圖至第三D圖為本發明之一實施例的多層銲墊打線方 式之流程圖。 第四A圖為本發明之另一實施例的多層銲墊打線封裝結構之 側視圖。 第四B圖為本發明之另一實施例的多層銲墊打線封裝結構之 上視圖。 第五A圖至第五C圖為本發明之另一實施例的多層銲墊打線 方式之流程圖。 第六圖為本發明之另一實施例的多層銲墊打線封裝結構之側 視圖。 【主要元件符號說明】 10 傳統封裝結構 12 晶片 14 内層辉塾 16 外層鮮塾 18 封裝基板 20 接地環 13 1282133 τ 22 電源環 24 訊號接墊 26、28 金屬線 102 晶片 104 内層銲塾 106 第一銲墊 107 第二銲墊 • 108 外層銲墊 109 第三銲墊 110 基板 112、114 第一接墊 116 第二接墊 金屬導線 118 、 119 、 120 、 122 、 124 、 12612 1282133 The first A to the first C is a flow chart for the traditional multi-layer bonding method. The second figure is a side view of a conventional wire bonding package structure. 3A to 3D are flow charts showing a method of wiring a multilayer pad according to an embodiment of the present invention. Figure 4A is a side elevational view of a multilayer pad wire bonding package structure in accordance with another embodiment of the present invention. Figure 4B is a top plan view of a multilayer pad wire bonding package structure in accordance with another embodiment of the present invention. Figs. 5A to 5C are flowcharts showing a manner of wiring a multilayer pad according to another embodiment of the present invention. Figure 6 is a side elevational view of a multilayer pad wire bonding package in accordance with another embodiment of the present invention. [Main component symbol description] 10 Traditional package structure 12 Wafer 14 Inner layer 塾 16 Outer layer 塾 18 Package substrate 20 Grounding ring 13 1282133 τ 22 Power ring 24 Signal pad 26, 28 Metal wire 102 Wafer 104 Inner layer soldering wire 106 First Pad 107 second pad • 108 outer pad 109 third pad 110 substrate 112, 114 first pad 116 second pad metal wire 118, 119, 120, 122, 124, 126
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