JP5709309B2 - 配線基板 - Google Patents
配線基板 Download PDFInfo
- Publication number
- JP5709309B2 JP5709309B2 JP2011069606A JP2011069606A JP5709309B2 JP 5709309 B2 JP5709309 B2 JP 5709309B2 JP 2011069606 A JP2011069606 A JP 2011069606A JP 2011069606 A JP2011069606 A JP 2011069606A JP 5709309 B2 JP5709309 B2 JP 5709309B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- element connection
- wiring
- row
- connection pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structure Of Printed Boards (AREA)
Description
4a 引出配線
5 半導体素子接続パッド
7 ソルダーレジスト層
7a 開口部
10a 搭載部
L1 搭載部10aの外周側から1番目の半導体素子接続パッド5の列
L2 搭載部10aの外周側から2番目の半導体素子接続パッド5の列
L3 搭載部10aの外周側から3番目の半導体素子接続パッド5の列
S 半導体素子
Claims (1)
- 上面中央部に半導体素子が搭載される搭載部を有する絶縁基板と、前記搭載部に外周側から1番目の列および2番目の列および3番目の列を有して格子状に配列形成された半導体素子接続パッドと、前記2番目の列および3番目の列の半導体素子接続パッドから前記1番目の列の半導体素子接続パッドの間を通って前記絶縁基板の上面を前記搭載部の外側へ延びる引出配線と、前記絶縁基板の上面に被着されており、前記半導体素子接続パッドを該半導体素子接続パッドから延びる前記引出配線の一部とともに前記1番目の列と2番目の列と3番目の列毎に露出させるスリット状の開口部を有するソルダーレジスト層とを備えて成る配線基板であって、前記引出配線は、前記半導体素子接続パッドとともに前記開口部内に露出する部位が前記開口部の開口縁に対して全て垂直に延びていることを特徴とする配線基板。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011069606A JP5709309B2 (ja) | 2011-03-28 | 2011-03-28 | 配線基板 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011069606A JP5709309B2 (ja) | 2011-03-28 | 2011-03-28 | 配線基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012204733A JP2012204733A (ja) | 2012-10-22 |
JP5709309B2 true JP5709309B2 (ja) | 2015-04-30 |
Family
ID=47185334
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011069606A Expired - Fee Related JP5709309B2 (ja) | 2011-03-28 | 2011-03-28 | 配線基板 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5709309B2 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6118652B2 (ja) * | 2013-02-22 | 2017-04-19 | ルネサスエレクトロニクス株式会社 | 半導体チップ及び半導体装置 |
JP6577846B2 (ja) * | 2015-11-25 | 2019-09-18 | 株式会社ジャパンディスプレイ | 検出装置及び表示装置 |
WO2021199475A1 (ja) * | 2020-03-31 | 2021-10-07 | 株式会社村田製作所 | モジュール基板、高周波モジュール及び通信装置 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3050807B2 (ja) * | 1996-06-19 | 2000-06-12 | イビデン株式会社 | 多層プリント配線板 |
JP4986738B2 (ja) * | 2007-06-27 | 2012-07-25 | 新光電気工業株式会社 | 半導体パッケージおよびこれを用いた半導体装置 |
-
2011
- 2011-03-28 JP JP2011069606A patent/JP5709309B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2012204733A (ja) | 2012-10-22 |
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