KR20080045729A - 피치 멀티플리케이션을 위한 스페이서들을 갖는 마스크패턴들 및 그의 형성 방법 - Google Patents
피치 멀티플리케이션을 위한 스페이서들을 갖는 마스크패턴들 및 그의 형성 방법 Download PDFInfo
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Abstract
Description
Claims (45)
- 임시 재료(temporary material)로 형성된 복수의 임시 플레이스홀더(placeholder)를 기판 위의 영역을 가로질러 형성하는 단계 - 상기 임시 플레이스홀더는 공간들에 의해 분리됨 - ;복수의 스페이서들을 형성하기 위해 상기 임시 재료의 일부를 다른 재료로 변경하는 단계 - 상기 다른 재료는 복수의 마스크 피처(feature)를 형성함 - ;변경되지 않은 임시 재료를 선택적으로 제거하는 단계; 및상기 복수의 스페이서들에 의해 정의된 마스크 패턴을 통해 상기 기판을 처리하는 단계를 포함하는 반도체 처리 방법.
- 제1항에 있어서,상기 임시 재료의 일부를 변경하는 단계는 상기 임시 플레이스홀더의 측벽들을 화학종과 선택적으로 반응시키는 단계를 포함하는 반도체 처리 방법.
- 제2항에 있어서,맨드릴(mandrel)의 측벽을 선택적으로 반응시키는 단계는 상기 맨드릴의 상부 수평면 위에 캡 층을 제공하는 단계를 포함하며,상기 캡 층은 상기 상부 수평면에서의 반응을 억제하는 반도체 처리 방법.
- 제3항에 있어서,상기 캡 층은 질화물을 포함하는 반도체 처리 방법.
- 제2항에 있어서,상기 임시 플레이스홀더의 측벽을 선택적으로 반응시키는 단계는, 상기 마스크 피처의 원하는 임계 치수에 기초하여 상기 측벽들을 반응시키기 위한 반응 조건들을 선택하는 단계를 포함하는 반도체 처리 방법.
- 제5항에 있어서,상기 임시 플레이스홀더의 측벽을 선택적으로 반응시키는 단계는 어닐링을 수행하는 단계를 포함하며, 상기 반응 조건들을 선택하는 단계는 상기 원하는 임계 치수에 기초하여 어닐링 온도 및 지속 시간을 선택하는 단계를 포함하는 반도체 처리 방법.
- 제2항에 있어서,상기 임시 플레이스홀더의 측벽을 선택적으로 반응시키는 단계는 상기 측벽들을 고상 반응물에 노출시키는 단계를 포함하는 반도체 처리 방법.
- 제7항에 있어서,상기 측벽들을 노출시키는 단계는 상기 고상 반응물을 포함하는 층의 블랭킷 성막(blanket deposition)을 포함하는 반도체 처리 방법.
- 제8항에 있어서,상기 블랭킷 성막은 화학 기상 증착을 포함하는 반도체 처리 방법.
- 제8항에 있어서,상기 블랭킷 성막은 원자 층 성막을 포함하는 반도체 처리 방법.
- 제8항에 있어서,상기 임시 재료의 일부를 변경하는 단계는 상기 고상 반응물을 포함하는 층의 일부분을 상기 임시 재료와 반응시키는 단계를 포함하는 반도체 처리 방법.
- 제11항에 있어서,상기 층의 반응하지 않은 나머지 부분을 우선적으로 제거하는 단계를 더 포함하는 반도체 처리 방법.
- 제7항에 있어서,상기 고상 반응물은 금속을 포함하고, 상기 다른 재료는 금속 실리사이드를 포함하는 반도체 처리 방법.
- 제13항에 있어서,상기 금속은 티타늄, 탄탈륨, 하프늄 및 니켈로 이루어진 군으로부터 선택되는 반도체 처리 방법.
- 제2항에 있어서,맨드릴의 측벽들을 선택적으로 반응시키는 단계는 상기 측벽들을 기상 반응물에 노출시키는 단계를 포함하는 반도체 처리 방법.
- 제15항에 있어서,상기 기상 반응물은 질소 함유 종(species)인 반도체 처리 방법.
- 제15항에 있어서,상기 기상 반응물은 산소 함유 종인 반도체 처리 방법.
- 제1항에 있어서,상기 복수의 임시 플레이스홀더를 형성하는 단계는,기판 위의 선택적으로 정의가능한 층에 패턴을 정의하는 단계; 및상기 패턴을 상기 선택적으로 정의가능한 층으로부터 상기 임시 재료로 형성된 하부 층으로 전사하는 단계를 포함하는 반도체 처리 방법.
- 제18항에 있어서,상기 패턴을 정의하는 단계는 포토리소그래피를 수행하는 단계를 포함하는 반도체 처리 방법.
- 제19항에 있어서,상기 패턴을 정의하는 단계는 193nm 또는 248nm의 파장 광을 이용하여 포토리소그래피를 수행하는 단계를 포함하는 반도체 처리 방법.
- 제1항에 있어서,상기 패턴을 전사하는 단계는 이방성 에칭을 수행하는 단계를 포함하는 반도체 처리 방법.
- 제1항에 있어서,상기 변경되지 않은 임시 재료를 선택적으로 제거하는 단계는 습식 에칭을 수행하는 단계를 포함하는 반도체 처리 방법.
- 제1항에 있어서,상기 스페이서들은 그 스페이서들과 직교하여 연장하는 적어도 제1 이격 평면과 제2 이격 평면의 사이에서 일반적으로 서로 평행한 관계로 이격되어 연장되는 반도체 처리 방법.
- 제1항에 있어서,맨드릴 재료는 실리콘을 포함하는 반도체 처리 방법.
- 제1항에 있어서,상기 다른 재료는 폴리머를 포함하는 반도체 처리 방법.
- 집적 회로를 제조하는 방법으로서,집적 회로의 영역에 맨드릴을 제공하는 단계;상기 맨드릴 위에 재료 층을 성막하는 단계; 및상기 재료 층을 등방성으로 에칭하여 상기 맨드릴의 측부에 노출된 스페이서들을 남기는 단계를 포함하는 제조 방법.
- 제26항에 있어서,상기 재료 층은 프리-스페이서(pre-spacer) 재료를 포함하는 제조 방법.
- 제27항에 있어서,등방성 에칭 전에 상기 프리-스페이서 재료를 상기 맨드릴과 반응시키는 단 계를 더 포함하며,상기 프리-스페이서 재료를 상기 맨드릴과 반응시키는 단계는 등방성 에칭에 사용되는 에칭에 대하여 내성을 갖는 스페이서 재료를 형성하는 제조 방법.
- 제26항에 있어서,상기 재료 층을 등방성으로 에칭하는 단계는 H2O, H2O2 및 NH4OH로 에칭하는 단계를 포함하는 제조 방법.
- 제29항에 있어서,상기 프리-스페이서 재료는 티타늄이고, 상기 스페이서 재료는 티타늄 실리사이드인 제조 방법.
- 제26항에 있어서,상기 스페이서들에 대해 상기 맨드릴을 우선적으로 제거하는 단계를 더 포함하는 제조 방법.
- 제26항에 있어서,상기 스페이서들은 서브리소그래피 피처(sublithographic feature)들인 제조 방법.
- 제26항에 있어서,상기 스페이서들의 측부 상에 추가 스페이서 재료 층을 성막하는 단계를 더 포함하는 제조 방법.
- 제33항에 있어서,상기 추가 스페이서 재료 층을 이방성으로 에칭하여 스페이서들의 측벽들 상에 추가 스페이서들을 형성하는 단계를 더 포함하는 제조 방법.
- 제34항에 있어서,상기 추가 스페이서들 사이의 스페이서들을 선택적으로 제거하여 프리 스탠딩(free standing) 추가 스페이서들의 패턴을 남기는 단계를 더 포함하는 제조 방법.
- 부분적으로 제조된 집적 회로 상에 놓인 중간 마스크 패턴으로서,맨드릴 재료로 형성된 복수의 이격된 맨드릴;상기 맨드릴 각각의 상면 위에 놓인 캡 층;각각의 캡 층 위에 놓인 프리-스페이서 재료 층; 및상기 맨드릴 각각의 측부 상의 스페이서들을 포함하며,상기 스페이서들은 프리-스페이서 재료와 맨드릴 재료의 조합을 포함하며, 상기 프리-스페이서 재료는 인접하는 스페이서들 사이에 연장되는 중간 마스크 패턴.
- 제36항에 있어서,상기 캡 층은 산화규소 또는 질화규소를 포함하는 중간 마스크 패턴.
- 제36항에 있어서,상기 맨드릴은 실리콘을 포함하는 중간 마스크 패턴.
- 제36항에 있어서,상기 스페이서들은 금속 실리사이드(metal silicde)를 포함하는 중간 마스크 패턴.
- 제39항에 있어서,상기 금속 실리사이드의 금속은 탄탈륨, 하프늄 및 니켈로 이루어진 군으로부터 선택되는 중간 마스크 패턴.
- 제36항에 있어서,상기 스페이서들은 서브리소그래피 피처들인 중간 마스크 패턴.
- 제36항에 있어서,상기 상면의 폭은 약 120 nm보다 작은 중간 마스크 패턴.
- 제42항에 있어서,상기 폭은 약 80 nm보다 작은 중간 마스크 패턴.
- 제42항에 있어서,상기 스페이서들은 약 80 nm 미만으로 이격된 중간 마스크 패턴.
- 제44항에 있어서,상기 스페이서들은 약 50 nm 미만으로 이격된 중간 마스크 패턴.
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2005
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2006
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- 2006-08-28 CN CN2006800398455A patent/CN101297391B/zh active Active
- 2006-08-28 JP JP2008529192A patent/JP5041250B2/ja active Active
- 2006-08-28 WO PCT/US2006/033703 patent/WO2007027686A2/en active Application Filing
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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KR20150065609A (ko) * | 2013-12-05 | 2015-06-15 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | 혼 형상 스페이서를 이용한 트렌치 형성 |
KR20170051518A (ko) * | 2014-09-12 | 2017-05-11 | 어플라이드 머티어리얼스, 인코포레이티드 | 자기 정렬식 대체 핀 형성 |
Also Published As
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CN101297391A (zh) | 2008-10-29 |
JP5041250B2 (ja) | 2012-10-03 |
US7776744B2 (en) | 2010-08-17 |
US20070049030A1 (en) | 2007-03-01 |
US20100267240A1 (en) | 2010-10-21 |
WO2007027686A2 (en) | 2007-03-08 |
WO2007027686A3 (en) | 2007-05-03 |
US9099314B2 (en) | 2015-08-04 |
EP1929509A2 (en) | 2008-06-11 |
TW200721254A (en) | 2007-06-01 |
CN101297391B (zh) | 2011-03-02 |
TWI328251B (en) | 2010-08-01 |
US20150325459A1 (en) | 2015-11-12 |
JP2009507375A (ja) | 2009-02-19 |
KR100967740B1 (ko) | 2010-07-05 |
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