KR101867955B1 - 패키지 온 패키지 장치 및 이의 제조 방법 - Google Patents

패키지 온 패키지 장치 및 이의 제조 방법 Download PDF

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KR101867955B1
KR101867955B1 KR1020120038268A KR20120038268A KR101867955B1 KR 101867955 B1 KR101867955 B1 KR 101867955B1 KR 1020120038268 A KR1020120038268 A KR 1020120038268A KR 20120038268 A KR20120038268 A KR 20120038268A KR 101867955 B1 KR101867955 B1 KR 101867955B1
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package
sealing film
solder bump
connection hole
semiconductor package
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Korean (ko)
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KR20130116100A (ko
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임충빈
유혜정
박태성
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삼성전자주식회사
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Priority to KR1020120038268A priority Critical patent/KR101867955B1/ko
Priority to US13/734,393 priority patent/US8779606B2/en
Priority to DE102013103301.6A priority patent/DE102013103301B4/de
Priority to TW102112261A priority patent/TWI611524B/zh
Priority to JP2013081768A priority patent/JP6173753B2/ja
Publication of KR20130116100A publication Critical patent/KR20130116100A/ko
Priority to US14/288,440 priority patent/US9245867B2/en
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Publication of KR101867955B1 publication Critical patent/KR101867955B1/ko
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
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US13/734,393 US8779606B2 (en) 2012-04-13 2013-01-04 Package-on-package electronic devices including sealing layers and related methods of forming the same
DE102013103301.6A DE102013103301B4 (de) 2012-04-13 2013-04-03 Elektronische Gehäuse-auf-Gehäuse-Vorrichtungen mit Abdichtungsschichten und Verfahren zum Herstellen derselben
TW102112261A TWI611524B (zh) 2012-04-13 2013-04-08 包含密封層之堆疊封裝電子元件及其相關製造方法
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US8779606B2 (en) 2014-07-15
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