KR101729933B1 - Non-volatile latch circuit and logic circuit, and semiconductor device using the same - Google Patents

Abstract

A novel non-volatile latch circuit and a semiconductor device using the non-volatile latch circuit are provided. The latch circuit has a loop structure in which the output of the first element is electrically connected to the input of the second element through the second transistor and the output of the second element is electrically connected to the input of the first element. A transistor using an oxide semiconductor as a semiconductor material in a channel forming region is used as a switching element and a capacitor element is electrically connected to a source electrode or a drain electrode of the transistor so that data of the latch circuit can be held, A non-volatile latch circuit can be formed.

Description

TECHNICAL FIELD [0001] The present invention relates to a nonvolatile latch circuit, a logic circuit, and a semiconductor device using the same. More particularly, the present invention relates to a nonvolatile latch circuit,

The disclosed invention relates to a non-volatile logic circuit in which the stored logic state is not erased even when the power supply is turned off, and a semiconductor device using the non-volatile logic circuit. In particular, the disclosed invention relates to a non-volatile latch circuit and a semiconductor device using the same.

Integrated circuits including non-volatile logic circuits have been proposed; In the integrated circuit, the logic circuit has "non-volatile" characteristics, i.e. the memory of the logic circuit is not erased even when the power supply is turned off. For example, a non-volatile latch circuit using a ferroelectric element as a non-volatile logic circuit is proposed (see Patent Document 1).

[Reference]

[Patent Document 1] PCT International Publication No. 2003/044953

However, non-volatile latch circuits using ferroelectric elements have problems with respect to reliability and voltage reduction of the number of rewrites. Further, the ferroelectric element is polarized by the electric field applied to the element and stores the data by the residual polarization. However, when the residual polarization is small, the influence of fluctuation becomes large, or a high-accuracy reading circuit is required.

In view of the above-mentioned problems, an object of an embodiment of the present invention is to provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit.

An embodiment of the present invention is a semiconductor device having a loop structure in which an output of a first element is electrically connected to an input of a second element via a second transistor and an output of the second element is electrically connected to an input of the first element Latch circuit. A transistor using an oxide semiconductor as a semiconductor material for a channel forming region is used as a switching element and a capacitor element is provided to be electrically connected to a source electrode or a drain electrode of the transistor so that data of the latch circuit can be held, Whereby a non-volatile latch circuit can be formed. The transistor using an oxide semiconductor allows the data stored in the capacitive element to be retained. And the capacitive element is electrically connected to a predetermined position in the loop structure of the latch circuit. Therefore, the non-volatile latch circuit has a configuration in which charge corresponding to data of the latch circuit is automatically accumulated in the capacitive element so that data writing is performed.

In other words, in an embodiment of the present invention, a first transistor and a second transistor each using an oxide semiconductor as a semiconductor material of a channel forming region are used as switching elements, and one of a source electrode and a drain electrode of the first transistor, And a capacitive element electrically connected to one of a source electrode and a drain electrode of the second transistor. The latch circuit has a loop structure in which the output of the first element through the second transistor is electrically connected to the input of the second element and the output of the second element is electrically connected to the input of the first element. The input of the first element is electrically connected to the wiring through which the input signal is applied through the first transistor. The output of the first element is electrically connected to the wiring to which the output signal is applied. That is, the first transistor is provided between the input to which the input signal is applied and the input of the first element, and the second transistor is provided between the output of the second element and the input of the first element do.

In this structure, one electrode of the capacitive element is electrically connected to one of the source electrode and the drain electrode of the second transistor, and the input of the first element. The one electrode of the capacitive element is also electrically connected to one of the source electrode and the drain electrode of the first transistor. And the other of the source electrode and the drain electrode of the second transistor is electrically connected to the output of the second element. And the other of the source electrode and the drain electrode of the first transistor is electrically connected to the wiring to which the input signal is applied.

In the above structure, the first element includes at least a third transistor. The gate of the third transistor is electrically connected to the input of the first element and the gate of the third transistor is electrically connected to one of the source electrode and the drain electrode of the second transistor. Further, the gate of the third transistor is electrically connected to one of the source electrode and the drain electrode of the first transistor.

In this structure, a capacitive element between the second transistor and the input of the first element can be used as a capacitive element for holding data of the latch circuit. The gate capacitance value of the third transistor can also be used as a capacitance element for holding data of the latch circuit. The gate capacitance value of the transistor other than the third transistor included in the first element can be used as a capacitance element for holding data of the latch circuit. The capacitance values may be used in combination. Further, it is possible to use only the gate capacitance value of the third transistor, and it is not possible to use other capacitance values.

In the above structure, each of the first transistor and the second transistor has a function of holding data written in the capacitive element. The capacitive element is electrically connected to a predetermined position in the loop structure of the latch circuit. Therefore, the non-volatile latch circuit has a configuration in which charge corresponding to data of the latch circuit is automatically accumulated in the capacitive element so that data writing is performed.

In the above structure, it is possible to use an element in which an inverted signal of an input signal is outputted as the first element and the second element. For example, an inverter, a NAND, a NOR, or a clocked inverter may be used as the first device and the second device. The inverter may be used as each of the first element and the second element, for example. Further, for example, it is possible to use a NAND as the first element and a clocked inverter as the second element.

In the above structure, as the oxide semiconductor layer used for the channel forming region of each of the first transistor and the second transistor, the following oxide semiconductors can be used: In-Sn-Ga- Zn-O-based oxide semiconductors; In-Zn-O-based oxide semiconductor, In-Al-Zn-O-based oxide semiconductor, Sn-Ga-Zn-O-based oxide semiconductor An oxide semiconductor, an Al-Ga-Zn-O-based oxide semiconductor, or a Sn-Al-Zn-O-based oxide semiconductor; Zn-O-based oxide semiconductor, Sn-Zn-O-based oxide semiconductor, Al-Zn-O-based oxide semiconductor, Zn-Mg-O-based oxide semiconductor, Sn-Mg-O - based oxide semiconductor, or an In-Mg-O-based oxide semiconductor; Or an In-O-based oxide semiconductor, a Sn-O-based oxide semiconductor, or a Zn-O-based oxide semiconductor. In addition, the oxide semiconductor materials may include SiO ₂ .

In the above structure, for example, an In-Sn-Ga-Zn-O-based oxide semiconductor means an oxide semiconductor containing at least In, Sn, Ga and Zn. The composition ratio of each metal element is not limited, and metal elements other than In, Sn, Ga, and Zn may be included.

Alternatively, as the oxide semiconductor layer, a film containing a material represented by InMO ₃ (ZnO) _m (m> 0, m is not a natural number) may be used. Here, M represents at least one of the metal elements selected from Ga, Al, Mn, and Co. For example, M may be Ga, Ga and Al, Ga and Mn, Ga and Co.

In the above structure, the concentration of hydrogen in the oxide semiconductor layer is 5 x 10 ¹⁹ / cm 3 or less, preferably 5 x 10 ¹⁸ / cm 3 or less, more preferably 5 x 10 ¹⁷ / cm 3 or less, Lt; ¹⁶ > / cm < 3 > or less. The carrier concentration in the oxide semiconductor layer may be set to less than 1 x 10 ¹⁴ / cm 3, preferably less than 1 x 10 ¹² / cm 3, more preferably less than 1 x 10 ¹¹ / cm 3.

In the above structure, the transistor using the oxide semiconductor may be a bottom-gate transistor, a top-gate transistor, or a bottom-contact transistor. The bottom-gate type transistor includes a gate electrode on an insulating surface; A gate insulating film on the gate electrode; An oxide semiconductor layer overlying the gate electrode on the gate insulating film; A source electrode and a drain electrode on the oxide semiconductor layer; And an insulating film over the source electrode, the drain electrode, and the oxide semiconductor layer. The top-gate type transistor includes an oxide semiconductor layer on an insulating surface; A gate insulating film on the oxide semiconductor layer; A gate electrode overlapping the oxide semiconductor layer on the gate insulating film and serving as a conductive film; Drain electrodes; A source electrode; And an insulating film on the oxide semiconductor layer. Another top-gate transistor comprises an oxide semiconductor layer on an insulating surface; A drain electrode and a source electrode on the oxide semiconductor layer; A gate insulating film on the oxide semiconductor layer, the drain electrode, and the source electrode; And a gate electrode overlapping the oxide semiconductor layer on the gate insulating film and serving as a conductive film. The bottom-contact transistor includes a gate electrode on an insulating surface; A gate insulating film on the gate electrode; A source electrode and a drain electrode on the gate insulating film; An oxide semiconductor layer on the gate insulating film which overlaps the source electrode, the drain electrode, and the gate electrode; And an insulating film over the source electrode, the drain electrode, and the oxide semiconductor layer.

The transistors (the first transistor and the second transistor) including the channel formation region formed using the oxide semiconductor layer made of the above-described oxide semiconductor material may have the following characteristics: for example, Even at a channel having a channel width (W) of 10 ⁴ 탆 and a channel length of 3 탆, the off-state current at room temperature (e.g., 20 캜) is 10 ^-13 A or less; The swing (S value) below the threshold value is approximately 0.1 V / dec (gate insulating film: 100 nm thickness). In addition, the transistor is a normally off transistor that is turned off when the voltage between the gate electrode and the source electrode is approximately 0V (i.e., the threshold voltage is positive in the case of an n-channel transistor).

The off-state current (also referred to as the leakage current) when the voltage between the gate electrode and the source electrode is approximately 0 V is much smaller than that of the transistor using silicon for the channel forming region . For example, the transistor described above with W = 1 x 10 ⁴ 탆 has a leakage current of less than or equal to 1 aA per 1 탆 of channel width at room temperature, preferably below 10 aA. (Hereinafter the following expressions are used herein: The leakage current per unit channel width at room temperature is 10 aA / 占 퐉 (preferably, 1 A / 占 퐉 or less)).

Therefore, when the transistor using the oxide semiconductor layer for the channel forming region is used as the switching element, the charge accumulated in the capacitor can be continuously held even after the supply of the power supply voltage to the latch circuit is stopped. That is, data recorded in the capacitive element can be retained continuously.

For example, it is possible to realize a much larger refresh time than that of a DRAM formed using a transistor including a channel formation region made of silicon, and also to have better memory retention ) Can be realized. Furthermore, after the power supply voltage is restarted to be supplied to the latch circuit, the data held in the capacitive element can be read. As a result, the logic state can be restored to that before the supply of the power supply voltage is stopped.

In addition, the transistor has good temperature characteristics and can have a sufficiently low off-state current and a sufficiently high on-state current even at high temperatures. For example, for the Vg-Id characteristics of the transistor, the following data is obtained: the on-state current, mobility, and S value have a small temperature dependence in the range of -25 DEG C to 150 DEG C; The off-state current is as small as 1 x 10 < ^-13 > A or less in this temperature range.

The above-described characteristics are obtained for the channel forming region of the transistor by an oxide semiconductor having a high purity and a hydrogen concentration sufficiently low to have a sufficiently low carrier concentration, i.e., intrinsic (i-type) or substantially intrinsic (i-type) , ≪ / RTI > That is, the channel forming region of the transistor is removed so that impurities other than the main component of the oxide semiconductor are contained as less as possible as n-type impurities, and intrinsic (i-type) or substantially intrinsic And is made of an oxide semiconductor which is highly purified so as to be a semiconductor.

In this specification, a semiconductor with a carrier concentration of less than 1 x 10 ¹¹ / cm 3 is referred to as an "intrinsic"("i-type") semiconductor and has a carrier concentration of 1 × 10 ¹¹ / cm 3 or more and less than 1 × 10 ¹² / Is referred to as a " substantially intrinsic "(" substantially i-type ") semiconductor.

By using such intrinsic (i-type) or substantially intrinsic (i-type) oxide semiconductors, the transistor has a conductivity of 10 aA (1 x 10 ^-17 A) 탆 or less per 1 탆 of channel width W, (1 x 10 <" ¹⁸ > A) μm or less.

As described above, in an embodiment of the present invention, the transistor using an oxide semiconductor as a semiconductor material of a channel forming region is used as the switching element; It is therefore possible to provide a non-volatile latch circuit that operates over a wide temperature range and operates stably even at high temperatures and does not erase the stored logic state even when the power supply is turned off.

In this structure, various kinds of logic circuits can be provided by using the non-volatile latch circuit. In addition, various kinds of semiconductor devices using the logic circuit can be provided. For example, among the plurality of block circuits of the logic circuit, supply of the power supply voltage to one or more of the unused block circuits may be stopped. With the use of the nonvolatile latch circuit, the logic state of the block circuit can be continuously stored even after the supply of the power supply voltage to the block circuit is stopped. In addition, the stored logic state can be read after the supply of the power supply voltage to the block circuit is resumed. As a result, the logic state can be restored to that before the supply of the power supply voltage is stopped.

In this specification and the like, it is noted that terms such as "above" or "below" do not necessarily mean that an element is necessarily located " directly above " For example, the expression "gate electrode over gate insulating layer" does not exclude the case where a component is located between the gate insulating layer and the gate electrode. In addition, terms such as "above" and "below" are used for convenience of explanation and may include instances where the relationship of components is reversed unless otherwise specified.

Also, in this specification and the like, terms such as "electrode" or "wiring" do not limit the functionality of such components. For example, "electrode" is sometimes used as part of "wiring" and vice versa. Moreover, the term "electrode" or "wiring" includes the case where a plurality of "electrodes" or "wires"

The functions of "source" and "drain" are sometimes interchanged, for example, when transistors of opposite polarity are used or when the direction of current is changed in circuit operation. Thus, in this specification, the terms "source" and "drain"

Also, in this specification and the like, the expression "electrically connected" includes the case where it is connected through an object having any electrical function which is a component. There is no particular limitation to "a subject having any electrical function" as long as electrical signals can be transmitted and received between the components connected through the object.

Examples of the "object having any electrical function" are switching elements such as transistors, resistors, inductors, capacitors, and devices having various functions as well as electrodes and wiring.

Generally, "SOI substrate" means a substrate on which a silicon semiconductor layer is provided on an insulating surface. In the present specification and the like, the "SOI substrate" also includes a substrate in which a semiconductor layer made of a material other than silicon is provided on an insulating surface. That is, the semiconductor layer included in the "SOI substrate" is not limited to the silicon semiconductor layer.

The substrate for the "SOI substrate" is not limited to a semiconductor substrate such as a silicon wafer, but may be a non-semiconductor substrate such as a glass substrate, a quartz substrate, a sapphire substrate, or a metal substrate. In other words, the "SOI" substrate "also includes a conductive or insulating substrate that is provided with a layer of semiconductor material in its category.

In addition, in this specification and the like, the term "semiconductor substrate" also means not only a substrate made of a semiconductor material but also all substrates including a semiconductor material. That is, in the present specification and the like, the "SOI substrate" is also included in the category of the "semiconductor substrate ".

(I-type) or substantially intrinsic (i-type) oxide semiconductor having a sufficiently low hydrogen concentration so as to have a high purity and a sufficiently low carrier concentration can be used as the semiconductor material of the channel forming region A used transistor is used as a switching element and a capacitive element electrically connected to a source electrode or a drain electrode of the transistor is provided; Thus, a non-volatile latch circuit that operates over a wide temperature range and operates stably even at high temperatures, and that does not erase the stored logic state even when the power supply is turned off, or a latch circuit with sufficiently long refresh time and data retention It is possible. In addition, since the electric charge accumulated in the capacitive element is held as data, the data can be easily read with less variation compared to when data is stored by residual polarization.

Various types of logic circuits may be provided by using the non-volatile latch circuit. For example, the power consumption of the logic circuit using the non-volatile latch circuit can be reduced by turning off the power of unused blocks. Also, since the logic state is stored even when the power supply is turned off, the system can be started at high speed and low power when the power is turned on or when the power supply is turned off.

1 is a diagram showing an example of the configuration of a non-volatile latch circuit;
Figures 2A and 2B illustrate examples of portions of a non-volatile latch circuit;
Figures 3a and 3b are cross-sectional and top views, respectively, of an element included in a non-volatile latch circuit;
Figures 4A through 4H show an example of a method for fabricating a device included in a non-volatile latch circuit.
Figures 5A-5G illustrate an example of a method for fabricating a device included in a non-volatile latch circuit.
6A to 6D illustrate an example of a method for fabricating a device included in a non-volatile latch circuit;
7 is a diagram showing an example of a cross-sectional structure of an inverted stagger type transistor using an oxide semiconductor.
8 is an energy band diagram (schematic diagram) along section A-A 'in Fig. 7; Fig.
Figure 9a shows a state in which the voltage (V _G> 0) of the amount applied to the gate (GE1), and Figure 9b is a cross-sectional view illustrating a state a negative voltage (V _G <0) is applied to the gate (GE1) drawing.
10 is a graph showing the relationship between a vacuum level and the work function [phi] _M of the metal and the electron affinity ([chi]) of the vacuum level and the oxide semiconductor.
11A and 11B are diagrams showing an example of a configuration of a non-volatile latch circuit;
12 shows an example of the operation of the non-volatile latch circuit;
13A and 13B illustrate examples of the operation of the non-volatile latch circuit.
14 is a diagram showing an example of the configuration of a non-volatile latch circuit;
15 is a diagram showing an example of the configuration of a non-volatile latch circuit;
16A to 16C show examples of the configuration of the non-volatile latch circuit;
17A to 17E illustrate an example of a method for manufacturing a device included in a non-volatile latch circuit;
18A to 18E illustrate an example of a method for manufacturing a device included in a non-volatile latch circuit;
19A to 19F illustrate examples of electronic devices including a semiconductor device using a non-volatile latch circuit.

Embodiments of the present invention will be described below with reference to the drawings. It should be noted that the present invention is not limited to the following description, as it will be apparent to those skilled in the art that modes and details may be altered in various ways without departing from the spirit and scope of the invention. Therefore, the present invention is not construed as being limited to the description of the embodiments. In the description using the drawings, it is noted that like parts are denoted by like reference numerals in different drawings.

Note that the sizes, film thicknesses, and regions of each structure shown in the drawings and the like in the above embodiments are exaggerated for simplicity in some cases. Therefore, the scale of each structure is not necessarily limited to that shown in the drawings.

Note that ordinals such as " first ", "second ", and" third "are used herein to identify elements, and that the terms do not limit the elements numerically.

(Example 1)

In this embodiment, the configuration and operation of a non-volatile latch circuit, which is an embodiment of the disclosed invention, the configuration and method for manufacturing an element included in the non-volatile latch circuit, and the like are shown in FIGS. 1, 2A, 3a and 3b, 4a to 4h, 5a to 5g, 6a to 6d, 7, 8, 9a and 9b, and 10, respectively.

&Lt; Configuration and operation of non-volatile latch circuit >

FIG. 1 shows the configuration of a non-volatile latch circuit 400. FIG. The non-volatile latch circuit 400 shown in FIG. 1 is a circuit in which the output of the first element D1 412 is electrically connected to the input of the second element D2 413, And the output of the second transistor 413 is electrically connected to the input of the first element D1 (412) through the second transistor 432. [

The input of the first device (D1) 412 is electrically connected to the wiring 414 to which the input signal is applied through the first transistor 431. [ The output of the first transistor (D1) 412 is electrically connected to the wiring 415 to which the output signal is applied. The wiring 414 to which an input signal is applied is a wiring which receives a signal input from the circuit of the previous stage to the non-volatile latch circuit 400. The wiring 415 to which the output signal is applied is a wiring which receives a signal output from the non-volatile latch circuit 400 to the next stage circuit.

When the first device (D1) 412 has a plurality of inputs, one of the inputs may be electrically connected to the wiring 414 to which an input signal is applied via the first transistor 431 have. When the second element (D2) 413 has a plurality of inputs, one of the inputs may be electrically connected to the output of the first element (D1) 412.

As the first element (D1) 412, it is possible to use an element which outputs an inverted signal of the input signal. For example, an inverter, a NAND, a NOR, or a clocked inverter may be used as the first device (D1) 412. The element from which the inverted signal of the input signal is output can also be used as the second element (D2) 413. For example, an inverter, a NAND, a NOR, or a clocked inverter may be used as the second element (D2) 413.

In the non-volatile latch circuit 400, the first transistor 431 and the second transistor 432, each of which uses an oxide semiconductor as a semiconductor material of the channel forming region, are used as switching elements. The non-volatile latch circuit 400 includes a capacitive element 404 electrically connected to a source electrode or a drain electrode of the first transistor 431 and the second transistor 432. That is, one electrode of the capacitive element 404 is electrically connected to one of the source electrode and the drain electrode of the first transistor 431, and one electrode of the capacitive element 404 is electrically connected to the second And is electrically connected to one of the source electrode and the drain electrode of the transistor 432. The other of the source electrode and the drain electrode of the first transistor 431 is electrically connected to the wiring to which the input signal is applied. The other of the source electrode and the drain electrode of the second transistor 432 is electrically connected to the output of the second element. The potential V _C is applied to the other electrode of the capacitor device 404.

In the above configuration, the first element 412 included in the non-volatile latch circuit 400 includes at least the third transistor 421. The gate of the third transistor 421 is electrically connected to the input of the first element 412. That is, the gate of the third transistor 421 is electrically connected to one of the source electrode and the drain electrode of the second transistor 432. Furthermore, the gate of the third transistor 421 is electrically connected to one of the source electrode and the drain electrode of the first transistor 431.

The first transistor 431 and the second transistor 432 may have the configuration shown in FIG. 2A or FIG. 2B instead of the configuration shown in FIG.

The transistor shown in Fig. 2A includes a first gate electrode and a second gate electrode. And the second gate electrode is provided on the opposite side of the first gate electrode with the oxide semiconductor layer forming a channel forming region therebetween. The first gate electrode is electrically connected to a wiring to which a signal is applied. And the second gate electrode is electrically connected to a wiring to which a predetermined potential is applied. For example, the second gate electrode is electrically connected to a wiring to which a negative potential or a ground potential (GND) is applied.

In the non-volatile latch circuit using the transistor shown in Fig. 2A, the effect that the electrical characteristics (e.g., threshold voltage) of the transistor is easily controlled is that in addition to the effect of the non-volatile latch circuit shown in Fig. &Lt; / RTI &gt; For example, when a negative potential is applied to the second gate electrode of the transistor, the transistor can easily be off-off (i.e., the transistor has a voltage between the gate electrode and the source electrode of approximately 0V Lt; / RTI &gt; can be turned off).

The transistor shown in Fig. 2B includes a first gate electrode and a second gate electrode. The second gate electrode is provided on the opposite side of the first gate electrode having an oxide semiconductor layer forming a channel forming region therebetween. And the second gate electrode is electrically connected to the first gate electrode.

In the non-volatile latch circuit using the transistor shown in Fig. 2B, an effect of increasing the amount of current of the transistor other than the effect of the non-volatile latch circuit shown in Fig. 1 can be obtained.

In the non-volatile latch circuit having the configuration shown in Fig. 1 or Figs. 2A and 2B, data writing, data holding, and data reading can be performed in the following manner. Note that although the following description of the configuration of Fig. 1 is made, the same applies to other configurations.

Volatile latch circuit 400 is configured such that the output of the first device D1 412 is electrically connected to the input of the second device D2 413, And the output of the element D2 413 is electrically connected to the input of the first element D1 412 through the second transistor 432. [ The gate capacitance value of the capacitance element 404 and the third transistor 421 is electrically connected to predetermined positions in the loop structure. Specifically, one electrode of the capacitive element 404 and the gate of the third transistor 421 are electrically connected to the input of the first element (D1) 412. In this manner, the capacitance value of the capacitive element 404 and the third transistor 421 is electrically connected to predetermined positions in the loop structure of the non-volatile latch circuit 400. Therefore, all the time data is written to the latch circuit, and the electric charge corresponding to the data is accumulated in the capacitance value of the capacitance element 404 and the gate capacitance value of the third transistor 421. In other words, the data of the latch circuit 400 is automatically written to the non-volatile latch (data writing). Data rewriting can similarly be performed.

The data stored in the gate capacitance value of the capacitance element 404 and the third transistor 421, that is, the charge stored in the capacitance element 404 and the gate capacitance value of the third transistor 421 Is performed by applying a potential to the gate of the first transistor 431 and the gate of the second transistor 432 such that the first transistor 431 and the second transistor 432 are turned off (Data retention).

Here, the transistor used as the first transistor 431 and the second transistor 432 uses an oxide semiconductor layer for a channel forming region and has normally off characteristics and a very low off-state current. Therefore, the electric charge stored in the capacitive element stops supplying at least the supply voltage to the first element (D1) 412 and the second element (D2) 413 included in the latch circuit (400) Can even be maintained. As a result, the logic state of the latch circuit 400 can be continuously stored even after the supply of the power supply voltage is stopped.

The gate capacitance value of the capacitor device 404 and the third transistor 421 is electrically connected to the input of the first device (D1) 412. Therefore, after the power supply voltage is restarted to be supplied to at least the first device (D1) 412 of the latch circuit 400, the potential of the output signal OUT is lower than the potential of the capacitor device 404 and the third transistor Is determined by the charge accumulated in the gate capacitance value of the gate electrode 421. That is, the data recorded in the capacitance element 404 and the gate capacitance value of the third transistor 421 can be read (data read).

As the oxide semiconductor layer used for the channel forming region of each of the first transistor 431 and the second transistor 432, the following oxide semiconductors can be used: In-Sn-Ga -Zn-O-based oxide semiconductor; In-Zn-O-based oxide semiconductor, In-Al-Zn-O-based oxide semiconductor, Sn-Ga-Zn-O-based oxide semiconductor An oxide semiconductor, an Al-Ga-Zn-O-based oxide semiconductor, or an Sn-Al-Zn-O-based oxide semiconductor layer; Zn-O-based oxide semiconductor, Sn-Zn-O-based oxide semiconductor, Al-Zn-O-based oxide semiconductor, Zn-Mg-O-based oxide semiconductor, Sn-Mg-O - based oxide semiconductor, or an In-Mg-O-based oxide semiconductor; Or an In-O-based oxide semiconductor, a Sn-O-based oxide semiconductor, or a Zn-O-based oxide semiconductor. In addition, the oxide semiconductor materials may include SiO ₂ .

In the above structure, for example, an In-Sn-Ga-Zn-O-based oxide semiconductor means an oxide semiconductor containing at least In, Sn, Ga and Zn. The composition ratio of each metal element is not limited, and metal elements other than In, Sn, Ga, and Zn may be included.

Alternatively, as the oxide semiconductor layer, a film containing a material represented by InMO ₃ (ZnO) _m (m> 0, m is not a natural number) may be used. Here, M represents at least one of the metal elements selected from Ga, Al, Mn, and Co. For example, M may be Ga, Ga and Al, Ga and Mn, or Ga and Co.

In the above structure, the concentration of hydrogen in the oxide semiconductor layer is 5 x 10 ¹⁹ / cm 3 or less, preferably 5 x 10 ¹⁸ / cm 3 or less, more preferably 5 x 10 ¹⁷ / cm 3 or less, Lt; ¹⁶ &gt; / cm &lt; 3 &gt; or less. The carrier concentration in the oxide semiconductor layer may be less than 1 x 10 ¹⁴ / cm 3, preferably less than 1 x 10 ¹² / cm 3, more preferably less than 1 x 10 ¹¹ / cm 3.

In the above structure, the transistor 431 and the transistor 432 each using an oxide semiconductor may be a bottom-gate transistor or a top-gate transistor. In addition, the transistor 431 and the transistor 432 may be a bottom-contact transistor or a top-contact transistor. The bottom-gate type transistor includes at least a gate electrode on an insulating surface; A gate insulating film on the gate electrode; And an oxide semiconductor layer overlapping the gate electrode on the gate insulating film and serving as a channel forming region. The top-gate transistor includes an oxide semiconductor layer on an insulating surface serving as at least a channel forming region; A gate insulating film on the oxide semiconductor layer; And a gate electrode overlapping the oxide semiconductor layer on the gate insulating film. The bottom-contact type transistor includes an oxide semiconductor layer serving as a channel forming region on the source electrode and the drain electrode. The top-contact type transistor includes a source electrode and a drain electrode on the oxide semiconductor layer serving as a channel forming region.

The transistors (the first transistor 431 and the second transistor 432) including a channel forming region formed using the oxide semiconductor layer made of the above-described oxide semiconductor material may have the following characteristics: When the drain voltage Vd applied is + 1V or + 10V and the gate voltage Vg applied to the gate electrode is in the range of -5V to -20V, for example, when the transistor is a 1 × 10 ⁴ μm channel Even in the case of having a width W and a channel length of 3 mu m, the off-state current at room temperature (e.g., 20 DEG C) is 10 ^-13 A or less; The swing (S value) below the threshold value is approximately 0.1 V / dec (gate insulating film: 100 nm thickness). In addition, the transistor has normally off characteristics (i.e., the threshold voltage is positive in the case of an n-channel transistor) in which the transistor is turned off when the voltage between the gate electrode and the source electrode is approximately 0V.

Thus, the transistor has the following characteristics: an off-state current (also referred to as a leak current) when the voltage between the gate electrode and the source electrode is approximately 0 V is greater than that of the transistor using silicon for the channel forming region Much smaller. For example, the above-described transistor with W = 1 x 10 ⁴ 탆 has a leakage current of 10 aA / 탆 or less per 1 탆 of the channel width at room temperature.

Therefore, when the transistor including the channel forming region formed using the oxide semiconductor layer is used as the switching element, the charge accumulated in the capacitor can be continuously maintained even after the supply of the supply voltage to the latch circuit is stopped . That is, data recorded in the capacitive element can be retained continuously.

For example, it is possible to realize a much longer refresh time than that of a DRAM formed using a transistor including a channel formation region made of silicon, and also to have better memory retention ) Can be realized. Furthermore, after the power supply voltage is supplied to the latch circuit, the data held in the capacitive element can be read. As a result, the logic state can be restored to that before the supply of the power supply voltage is stopped.

In addition, the transistor has good temperature characteristics and can have a sufficiently low off-state current and a sufficiently high on-state current even at high temperatures. For example, for the Vg-Id characteristics of the transistor, the following data is obtained: the on-state current, mobility, and S value have a small temperature dependence in the range of -25 DEG C to 150 DEG C; The off-state current is as small as 1 x 10 &lt; ^-13 &gt; A or less in this temperature range.

The above-described characteristics are obtained for the channel forming region of the transistor by an oxide semiconductor having a high purity and a hydrogen concentration sufficiently low to have a sufficiently low carrier concentration, i.e., intrinsic (i-type) or substantially intrinsic (i-type) , &Lt; / RTI &gt; That is, the channel forming region of the transistor is formed such that hydrogen is removed as an n-type impurity so that impurities other than the main component of the oxide semiconductor are contained as little as possible, and intrinsic (i-type) or substantially intrinsic (i-type) Of the oxide semiconductor.

In this specification, a semiconductor with a carrier concentration of less than 1 x 10 ¹¹ / cm 3 is referred to as an "intrinsic"("i-type") semiconductor and has a carrier concentration of 1 × 10 ¹¹ / cm 3 or more and less than 1 × 10 ¹² / Is referred to as a " substantially intrinsic "(" substantially i-type ") semiconductor.

By using such intrinsic (i-type) or substantially intrinsic (i-type) oxide semiconductors, the transistor can have a current density of 10 aA (1 x ^10-17 A) 1 x 10 &lt;&quot; ¹⁸ &gt; A) μm or less.

As described above, in one embodiment of the present invention, the first transistor 431 and the second transistor 432 using an oxide semiconductor as the semiconductor material of the channel forming region are used as the switching element; It is therefore possible to provide a non-volatile latch circuit that operates over a wide temperature range and operates stably even at high temperatures and does not erase the stored logic state even when the power supply is turned off.

Note that the concentration of hydrogen in the oxide semiconductor layer is the concentration measured by secondary ion mass spectrometry (SIMS).

&Lt; Structure of elements in non-volatile latch circuit >

In addition to the first transistor 431 and the second transistor 432 using an oxide semiconductor, some elements included in the non-volatile latch circuit 400 may be made of a semiconductor material other than an oxide semiconductor. As a material other than the oxide semiconductor, single crystal silicon, crystalline silicon, or the like can be used. For example, the elements other than the first transistor 431 and the second transistor 432 may be provided on a substrate containing a semiconductor material. As the substrate including a semiconductor material, a silicon wafer, a silicon on insulator (SOI) substrate, a silicon film on an insulating surface, or the like can be used. Use of such materials other than oxide semiconductors enables high-speed operation.

For example, the third transistor 421 included in the first device (D1) 412 may be formed of a material other than an oxide semiconductor (such as silicon). Other elements included in the first device (D1) 412 and the second device (D2) 413 may also be made of a material other than an oxide semiconductor (such as silicon).

Another element, such as the capacitive element 404 included in the non-volatile latch circuit 400, is connected to the transistor (the first transistor 431 and the second transistor 432) using an oxide semiconductor or the oxide semiconductor May be formed using the same material on the same layer as the semiconductor layer, the insulating layer, the conductive layer, or the conductive layer used as the wiring included in the transistor using the other material (such as silicon).

For example, the third transistor 421 using a material other than the oxide semiconductor may be provided at the bottom, and the first transistor 431 and the second transistor 432 using oxide semiconductors may be provided on the upper portion . Then, an excellent non-volatile latch circuit with the characteristics of both transistors can be manufactured.

3A and 3B show an example of the structures of the elements included in the non-volatile latch circuit. In Fig. 3A, the transistor 421 using a material other than an oxide semiconductor is provided below, and a transistor 402 using an oxide semiconductor is provided on the top. The transistor 402 is used as the first transistor 431 and the second transistor 432. The transistor 421 is used as the third transistor 421.

Fig. 3A is a sectional view and Fig. 3B is a plan view. Figure 3a corresponds to the cross-section along the lines A1-A2 and B1-B2 in Figure 3b. In FIGS. 3A and 3B, the transistor 421 using a material other than the oxide semiconductor is provided at the bottom, and the transistor 402 using the oxide semiconductor is provided at the top.

The transistor 421 includes a channel formation region 116 in a substrate 100 including a semiconductor material; Impurity regions 114 and high-concentration impurity regions 120 (also referred to simply as impurity regions simply and moderately); A gate insulating layer 108a over the channel forming region 116; A gate electrode 110a on the gate insulating layer 108a; And a source or drain electrode 130a and a source or drain electrode 130b electrically connected to the impurity regions 114 (see FIG. 3A).

Sidewall insulating layers 118 are provided on the sides of the gate electrode 110a. The high-concentration impurity regions 120 are provided in regions of the substrate 100 that do not overlap with the sidewall insulating layers 118 when viewed from above, - &lt; / RTI &gt; concentration impurity regions (120). An element isolation insulating layer 106 is provided on the substrate 100 to surround the transistor 421. An interlayer insulating layer 126 and an interlayer insulating layer 128 are provided so as to surround the transistor 421. [ It should be noted that the sidewall insulating layers 118 are not necessarily provided in the case of highly miniaturization of the semiconductor device.

The source or drain electrode 130a and the source or drain electrode 130b are electrically connected to the metal compound regions 124 through openings formed in the interlayer insulating layer 126 and the interlayer insulating layer 128. [ do. In other words, the source or drain electrode 130a and the source or drain electrode 130b are connected to the high-concentration impurity regions 120 and the impurity regions 114 through the metal compound regions 124, And is electrically connected.

The transistor 402 includes a gate electrode 136d on the interlayer insulating layer 128; A gate insulating layer 138 over the gate electrode 136d; An oxide semiconductor layer 140 on the gate insulating layer 138; And a source or drain electrode 142a and a source or drain electrode 142b on the oxide semiconductor layer 140 and electrically connected to the oxide semiconductor layer 140 (see FIG. 3A).

A protective insulating layer 144 is provided over the transistor 402 to connect to a portion of the oxide semiconductor layer 140. An interlayer insulating layer 146 is provided on the protective insulating layer 144. The protective insulating layer 144 and the interlayer insulating layer 146 include openings that reach the source or drain electrode 142a and the source or drain electrode 142b. An electrode 150d and an electrode 150e are provided in contact with the source or drain electrode 142a and the source or drain electrode 142b through the openings.

The electrodes 150a and 150b and the electrode 150c are electrically connected to the gate insulating layer 138, the protective insulating layer 144, and the electrodes 150a and 150b simultaneously with the formation of the electrode 150d and the electrode 150e. The electrode 136b, and the electrode 136c through the openings formed in the interlayer insulating layer 146, respectively. For example, a bottom-gate type transistor is used as the transistor 402, but the structure of the transistor is not limited thereto, and a top-gate type transistor can be used.

An insulating layer 152 is provided on the interlayer insulating layer 146. The electrode 154a, the electrode 154b, the electrode 154c, and the electrode 154d are provided so as to be embedded in the insulating layer 152. [ The electrode 154a, the electrode 154b, the electrode 154c and the electrode 154d are electrically connected to the electrode 150a, the electrode 150b and the electrodes 150c and 150d, (150e).

That is, the source or drain electrode 142a of the transistor 402 is electrically connected to other elements (not shown) through the electrode 130c, the electrode 136c, the electrode 150c, the electrode 154c, (Such as the transistor using a material other than an oxide semiconductor) (see Fig. 3A). The source or drain electrode 142b of the transistor 402 is electrically connected to other elements through the electrode 150e and the electrode 154d. The structure of the connection electrodes (such as the electrode 130c, the electrode 136c, the electrode 150c, the electrode 154c, and the electrode 150d) is not limited to the above, And can be omitted.

One example of the connection relationship is shown above, but the embodiment of the disclosed invention is not limited thereto.

The oxide semiconductor layer 140 is preferably a high-purity oxide semiconductor layer in which impurities such as hydrogen are sufficiently removed. Specifically, the concentration of hydrogen in the oxide semiconductor layer 140, which is measured by secondary ion mass spectrometry (SIMS), is 5 × 10 ¹⁹ / cm 3 or less, preferably 5 × 10 ¹⁸ / cm 3 or less, Lt; ¹⁷ &gt; / cm &lt; 3 &gt;, and even more preferably less than 1 x 10 &lt; ¹⁶ &gt; / cm &lt; 3 &gt;

The highly refined oxide semiconductor layer 140 having a sufficiently low hydrogen concentration has a much lower carrier concentration (for example, 1 x &lt; RTI ID = 0.0 &gt; (Less than 10 ¹² / cm 3, preferably less than 1 × 10 ¹¹ / cm 3) (approximately 1 × 10 ¹⁴ / cm 3).

By using such an i-type or substantially i-type oxide semiconductor, the transistor 402 with excellent off-current characteristics can be obtained. For example, when the drain voltage Vd applied to the drain electrode is + 1V or + 10V and the gate voltage Vg applied to the gate electrode is in the range of -5V to -20V, Even in the case of having a channel width (W) of 10 ⁴ 탆 and a channel length of 3 탆, the off-state current at room temperature is 10 ^-13 A or less. In addition, the transistor 402 has the above characteristics as a normally-off transistor.

Thus, the transistor 402 has the following characteristics: an off-state current (also referred to as a leakage current) when the voltage between the gate electrode and the source electrode is approximately 0V is used for the transistor Is much smaller than that of. For example, the transistor 402 has a leakage current of 10 aA / [mu] m or less per 1 mu m of channel width at room temperature.

In addition, the transistor 402 has good temperature characteristics and can have a sufficiently low off-state current and a sufficiently high on-state current even at high temperatures. For example, for the Vg-Id characteristics of the transistor, the following data can be obtained: On-state current, mobility, and S value have small temperature dependence in the range of -25 ° C to 150 ° C Having; The off-state current is as small as 1 x 10 &lt; ^-13 &gt; A or less in this temperature range.

By using such intrinsic (i-type) or substantially intrinsic (i-type) oxide semiconductors, the transistor can have a current density of 10 aA (1 x ^10-17 A) 1 x 10 &lt;&quot; ¹⁸ &gt; A) μm or less.

As described above, when the high-purity oxide semiconductor layer 140 having a sufficiently low hydrogen concentration is used to reduce the off-state current of the transistor 402, a semiconductor device having a new structure can be realized .

&Lt; Method for manufacturing elements in non-volatile latch circuit >

Next, an example of a method for manufacturing elements included in the above-described non-volatile latch circuit will be described. First, a method for fabricating the transistor 421 will be described with reference to FIGS. 4A-4H, and then a method for fabricating the transistor 402 is described with reference to FIGS. 5A through 5G or 6A through 6D. Will be described with reference to FIG. With the manufacturing method shown below, the elements included in the above-described non-volatile latch circuit can be manufactured. Note that Figures 4a-4h only show a cross-section along line A1-A2 in Figure 3a. Figs. 5A to 5G and Figs. 6A to 6D show cross sections along the line A1-A2 and the line B1-B2 in Fig. 3A.

&Lt; Method for fabricating a transistor at the bottom &

First, the substrate 100 including a semiconductor material is prepared (see FIG. 4A). As the substrate 100 including a semiconductor material, for example, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon, silicon carbide, or the like; A compound semiconductor substrate made of silicon germanium or the like; Or an SOI substrate may be used. One example shown here is the case of using a single crystal silicon substrate as the substrate 100 including a semiconductor material.

Note that in general, "SOI substrate" means a substrate on which a silicon semiconductor layer is provided on an insulating surface. In the present specification and the like, the "SOI substrate" also includes a substrate on which a semiconductor layer formed of a material other than silicon is provided on its insulating surface in its category. That is, the semiconductor layer included in the "SOI substrate" is not limited to the silicon semiconductor layer. The SOI substrate may have a structure in which a semiconductor layer is provided on an insulating substrate such as a glass substrate.

A protective layer 102 serving as a mask for forming an element isolation insulating layer is formed on the substrate 100 (see Fig. 4A). As the protective layer 102, for example, an insulating layer made of silicon oxide, silicon nitride, silicon nitride oxide, or the like can be used. Note that before or after this step, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity may be added to the substrate 100 to control the threshold voltage of the transistor. In the case where silicon is used as the semiconductor material, phosphorus, arsenic, or the like can be used as the impurity imparting the n-type conductivity, and boron, aluminum, gallium or the like can be used as the impurity imparting the p-type conductivity.

Next, a portion of the substrate 100 in a region not covered by the protective layer 102 (i.e., in the exposed region) is removed by etching using the protective layer 102 as a mask. Thus, a separate semiconductor region 104 is formed (see FIG. 4B). As the etching, dry etching is preferably performed, but wet etching can be performed. The etching gas or etchant may be appropriately selected depending on the material to be etched.

Thereafter, an insulating layer is formed to cover the semiconductor region 140, and the insulating layer in a region overlapping with the semiconductor region 104 is selectively removed so that the element isolation insulating layers 106 are formed (See FIG. 4B). The insulating layer is made of silicon oxide, silicon nitride, silicon nitride oxide, or the like. As a method for removing the insulating layer, any of a polishing treatment and an etching treatment such as CMP may be used. Note that the protective layer 102 is removed after formation of the semiconductor region 104 or after formation of the element isolation insulating layers 106.

Next, an insulating layer is formed on the semiconductor region 104, and a layer including a conductive material is formed on the insulating layer.

The insulating layer later acts as a gate insulating layer and preferably has a single-layer structure or a stacked structure using a film containing silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide or the like formed by a CVD method, a sputtering method, Structure. Alternatively, the insulating layer may be formed in such a manner that the surface of the semiconductor region 104 is oxidized or nitrided by a high-density plasma treatment or a thermal oxidation treatment. The high-density plasma treatment may be performed using a mixed gas of a rare gas such as He, Ar, Kr, or Xe and a gas such as oxygen, nitrogen, oxide, ammonia, nitrogen, or hydrogen. There is no particular limitation on the thickness of the insulating layer. For example, the insulating layer may have a thickness of 1 nm or more and 100 nm or less.

The layer including the conductive material may be made of a metal material such as aluminum, copper, titanium, tantalum, or tungsten. The layer including the conductive material may also be formed of a semiconductor material such as polycrystalline silicon including an impurity element imparting conductivity. There is no particular limitation on the method for forming the layer including the conductive material, and various film forming methods such as a vapor deposition method, a CVD method, a sputtering method, or a spin coating method may be used. Note that this embodiment shows an example of the case where the layer including the conductive material is made of a metal material.

Then, the layer including the insulating layer and the conductive material is selectively etched, thereby forming the gate insulating layer 108a and the gate electrode 110a (see FIG. 4C).

Next, an insulating layer 112 covering the gate electrode 110a is formed (see FIG. 4C). Phosphorus (P), arsenic (As), and the like are then added to the semiconductor region 104, thereby forming the impurity regions 114 having a shallow junction depth (see FIG. 4C). Phosphorus or arsenic is added thereto to form an n-channel transistor; Note that an impurity element such as boron (B) or aluminum (Al) may be added when forming a p-channel transistor.

With the formation of the impurity regions 114, the channel forming region 116 is formed in the semiconductor region 104 under the gate insulating layer 108a (see FIG. 4C). Here, the concentration of the added impurity can be appropriately set; The concentration is preferably increased when the size of the semiconductor element is extremely reduced. Wherein the impurity regions 114 are formed after the formation of the insulating layer 112 is used herein; Alternatively, the insulating layer 112 may be formed after formation of the impurity regions 114.

Next, the sidewall insulating layers 118 are formed (see FIG. 4D). An insulating layer is formed to cover the insulating layer 112 and then the sidewall insulating layers 118 may be formed in a self-aligning manner when highly anisotropically etched. At this time, it is preferable that the insulating layer 112 is partially etched so that the upper surface of the gate electrode 110a and the upper surfaces of the impurity regions 114 are exposed. It should be noted that the sidewall insulating layers 118 are not necessarily provided in the case of highly miniaturization of the semiconductor device.

Then, an insulating layer is formed to cover the gate electrode 110a, the impurity regions 114, the sidewall insulating layers 118, and the like. Phosphorus (P), arsenic (As) and the like are then added to regions in contact with the impurity regions 114; Accordingly, the high-concentration impurity regions 120 are formed. The insulating layer is then removed and a metal layer 122 is formed to cover the gate electrode 110a, the sidewall insulating layers 118, the high-concentration impurity regions 120, and the like Reference).

The metal layer 122 may be formed by various film forming methods such as a vacuum deposition method, a sputtering method, or a spin coating method. The metal layer 122 is preferably made of a metallic material that reacts with the semiconductor material contained in the semiconductor region 104 to become a low-resistance metal compound. Examples of such metallic materials include titanium, tantalum, tungsten, nickel, cobalt, and platinum.

Next, thermal processing is performed to cause the metal layer 122 to react with the semiconductor material. Thus, the metal compound regions 124 that are in contact with the high-concentration impurity regions 120 are formed (see FIG. 4F). Note that when the gate electrode 110a is made of polycrystalline silicon or the like, a metal compound region is also formed in the region of the gate electrode 110a in contact with the metal layer 122. [

As the heat treatment, irradiation with, for example, a flash lamp may be used. Needless to say, another heat treatment method can be used, but a method by which heat treatment can be achieved in a very short time is preferably used to improve the controllability of the chemical reaction in the formation of the metal compound. Note that the metal compound regions are formed by the reaction of the metal material and the semiconductor material and have sufficiently high conductivity. The formation of the metal compound regions can sufficiently reduce the electrical resistance and improve device characteristics. Note that the metal layer 122 is removed after the metal compound regions 124 are formed.

Then, the interlayer insulating layer 126 and the interlayer insulating layer 128 are formed to cover the components formed in the steps (see FIG. 4G). The interlayer insulating layers 126 and 128 may be formed of an inorganic insulating material such as silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, or tantalum oxide. Alternatively, the interlayer insulating layers 126 and 128 may be formed of an organic insulating material such as polyimide or acrylic. A two-layer structure of the interlayer insulating layer 126 and the interlayer insulating layer 128 may be used here; Note that the structure of the interlayer insulating layer is not limited to this structure. After the formation of the interlayer insulating layer 128, the surface of the interlayer insulating layer 128 is preferably planarized by CMP, etching, or the like.

Then, openings reaching the metal compound regions 124 are formed in the interlayer insulating layers, and the source or drain electrode 130a and the source or drain electrode 130b are formed in the openings 4h). The source or drain electrodes 130a and 130b may be formed by a method in which a conductive layer is formed in a region including the openings by a PVD method or a CVD method and then a part of the conductive layer is removed by etching, As shown in FIG.

Note that in the case where the source or drain electrodes 130a and 130b are formed by removing a portion of the conductive layer, the surfaces are preferably treated to be planarized. For example, when a thin titanium film or a thin titanium nitride film is formed in an area containing the openings and then a tungsten film is formed to be embedded in the openings, the subsequent CMP removes unnecessary tungsten, titanium, titanium nitride and the like Thereby allowing the flatness of the surface to be improved. When the surface including the source or drain electrodes 130a and 130b is planarized in this manner, electrodes, wiring, an insulating layer, a semiconductor layer and the like can be formed well in later steps.

There is no particular limitation on the material used for the source or drain electrodes 130a and 130b, and various conductive materials can be used. For example, a conductive material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium may be used. Note that only the source or drain electrodes 130a and 130b that are in contact with the metal compound regions 124 are shown here and that at this stage, the electrode 130c, etc., lets do it.

Specifically, for example, the conductive layer can be formed as follows: a thin titanium film is formed by a PVD method in an area including the openings, and a thin titanium nitride film is formed by a CVD method, As shown in FIG. Here, the titanium film formed by the PVD method has a function of reducing the oxide film that can be formed on the surface of the metal compound regions and reducing the contact resistance with the metal compound regions. After the formation of the titanium film, the titanium nitride film has a barrier function to prevent diffusion of the conductive material. The copper film may be formed by a plating method after formation of the above-mentioned barrier film such as titanium or titanium nitride. Note that a double damascene method as well as a so-called single damascene method can also be used.

Through the above steps, the transistor 421 using the substrate 100 including a semiconductor material is obtained. Note that electrodes, wiring, insulating layers, etc. may be additionally formed after the above steps. When the wirings have a multi-layer structure of a laminated structure including an interlayer insulating layer and a conductive layer, a highly integrated semiconductor device can be provided.

&Lt; Method for fabricating the transistor on the top &

Next, steps for fabricating the transistor 402 on the interlayer insulating layer 128 will be described with reference to FIGS. 5A to 5G and 6A to 6D. 5A through 5G and 6A through 6D illustrate steps for fabricating the electrodes, the transistor 402, and the like on the interlayer dielectric layer 128, and therefore, Note that the transistors 421 and the like are omitted.

First, an insulating layer 132 is formed on the interlayer insulating layer 128, the source or drain electrodes 130a and 130b, and the electrode 130c (see FIG. 5A). Next, openings are formed in the insulating layer 132 to reach the source or drain electrodes 130a and 130b and the electrode 130c. Thereafter, a conductive layer 134 is formed to be embedded in the openings (see FIG. 5B). A portion of the conductive layer 134 is removed by etching or CMP to expose the insulating layer 132 to form the electrodes 136a, (See Fig. 5C).

The insulating layer 132 may be formed by a PVD method, a CVD method, or the like. The insulating layer 132 may be formed of an inorganic insulating material such as silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, or tantalum oxide.

The openings in the insulating layer 132 may be formed by etching using a mask or the like. The mask may be formed by a method such as exposure using a photomask. Wet etch or dry etch may be used as the etch; Dry etching is preferably used for micromachining.

The conductive layer 134 may be formed by a film forming method such as a PVD method or a CVD method. Examples of the material used for the conductive layer 134 include conductive materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium; And alloys and compounds (e.g., nitrides) of any of these materials.

More specifically, the conductive layer 134 may be formed, for example, by forming a thin titanium film on a region including the openings by a PVD method and forming a thin titanium nitride film by a CVD method and then forming a tungsten film to be embedded in the openings As shown in FIG. Here, the titanium film formed by the PVD method may be formed by reducing an oxide film that may be formed on the surface of the lower electrodes (here, the source or drain electrodes 130a and 130b, the electrode 130c, etc.) And has a function of reducing the contact resistance with the lower electrodes.

The titanium nitride film formed after formation of the titanium film has a barrier function to prevent diffusion of the conductive material. The copper film may be formed by a plating method after formation of the above-mentioned barrier film such as titanium or titanium nitride. Note that a dual damascene method as well as a so-called single damascene method can also be used.

After the conductive layer 134 is formed, a part of the conductive layer 134 is removed by etching, CMP, or the like, so that the insulating layer 132 is exposed and the electrodes 136a, 136b, (See Fig. 5C). Note that when the electrodes 136a, 136b, 136c and the gate electrode 136d are formed by removing a portion of the conductive layer 134, the surfaces are preferably treated to be planarized. When the surfaces of the insulating layer 132, the electrodes 136a, 136b and 136c and the gate electrode 136d are planarized in this manner, the electrode, wiring, insulating layer, semiconductor layer, Can be formed well.

Next, the gate insulating layer 138 is formed to cover the insulating layer 132, the electrodes 136a, 136b, and 136c, and the gate electrode 136d (see FIG. 5D). The gate insulating layer 138 may be formed by a CVD method, a sputtering method, or the like. The gate insulating layer 138 is preferably made of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, or the like. Note that the gate insulating layer 138 may have a single-layer structure or a stacked-layer structure.

For example, the gate insulating layer 138 made of silicon oxynitride can be formed by plasma CVD using silane (SiH4), oxygen, and nitrogen as source gases. There is no particular limitation on the thickness of the gate insulating layer 138. For example, the gate insulating layer 138 may have a thickness of 10 nm or more and 500 nm or less. In the case of using the laminated structure, for example, the gate insulating layer 138 preferably has a first gate insulating layer having a thickness of 50 nm or more and 200 nm or less, and a second gate insulating layer having a thickness of 5 nm or more and 300 nm or less Lt; RTI ID = 0.0 &gt; a &lt; / RTI &gt;

If hydrogen, water, or the like is included in the gate insulating layer 138, hydrogen may enter the oxide semiconductor layer or extract oxygen from the oxide semiconductor layer, causing deterioration of characteristics of the transistor. Accordingly, the gate insulating layer 138 preferably contains as little hydrogen or water as possible.

For example, in the case of using a sputtering method or the like, the gate insulating layer 138 is preferably formed in a state in which moisture remaining in the treatment chamber is removed. To remove moisture remaining in the treatment chamber, an entrapment vacuum pump such as a cryopump, an ion pump, or a titanium sublimation pump is preferably used. A turbo pump with a cold trap can be used. Hydrogen, water and the like are sufficiently removed from the treatment chamber that is evacuated with the cryopump and the like; Therefore, the concentration of the impurity in the gate insulating layer 138 can be reduced.

When the gate insulating layer 138 is formed, it is preferable to use a high-purity gas whose concentration of impurities such as hydrogen or water is reduced to 1 ppm (preferably, 1 ppb or less).

Oxide semiconductors which result in i-type or substantially i-type oxide semiconductors (high-purity oxide semiconductors) by removing impurities are very sensitive to interfacial levels or interface charge, and therefore such oxide semiconductors can be used for oxide semiconductor layers , It is important to note that the interface between the oxide semiconductor layer and the gate insulating layer is important. In other words, the gate insulating layer 138 in contact with the high-purity oxide semiconductor layer is required to have a high quality.

For example, a high-density plasma CVD process using microwaves (2.45 GHz) is preferred because a dense, high-quality gate insulating layer 138 with a high withstand voltage can be formed. This is because when the high-purity oxide semiconductor layer is in close contact with the high-quality gate insulating layer, the interface level can be reduced and good interface characteristics can be obtained.

It is needless to say that even when a high-purity oxide semiconductor layer is used, another method such as a sputtering method or a plasma CVD method can be used as long as a high-quality insulating layer can be formed as the gate insulating layer. In addition, it is desirable to use an insulating layer in which quality and interfacial properties are improved with the heat treatment performed after formation of the insulating layer. In any case, an insulating layer having a good film quality as the gate insulating layer 138 and capable of reducing the interface level density with the oxide semiconductor layer is formed as the gate insulating layer 138 to form a good interface.

Next, an oxide semiconductor layer is formed on the gate insulating layer 138 and is processed by a method such as etching using a mask so that the island-shaped oxide semiconductor layer 140 is formed (see FIG. 5E).

As the oxide semiconductor layer, the following oxide semiconductors are used: an In-Sn-Ga-Zn-O-based oxide semiconductor which is a quaternary metal oxide; In-Zn-O-based oxide semiconductor, In-Al-Zn-O-based oxide semiconductor, Sn-Ga-Zn-O-based oxide semiconductor An oxide semiconductor, an Al-Ga-Zn-O-based oxide semiconductor, or an Sn-Al-Zn-O-based oxide semiconductor layer; Zn-O-based oxide semiconductor, Sn-Zn-O-based oxide semiconductor, Al-Zn-O-based oxide semiconductor, Zn-Mg-O-based oxide semiconductor, Sn-Mg-O - based oxide semiconductor, or an In-Mg-O-based oxide semiconductor; Or an In-O-based oxide semiconductor, a Sn-O-based oxide semiconductor, or a Zn-O-based oxide semiconductor. In addition, the oxide semiconductor materials may include SiO ₂ .

Alternatively, as the oxide semiconductor layer, a film containing a material represented by InMO ₃ (ZnO) _m (m> 0, m is not a natural number) may be used. Here, M represents at least one of the metal elements selected from Ga, Al, Mn, and Co. For example, M may be Ga, Ga and Al, Ga and Mn, or Ga and Co.

In this embodiment, an amorphous oxide semiconductor layer is formed as the oxide semiconductor layer by a sputtering method using an In-Ga-Zn-O-based metal oxide target. Since the crystallization of the amorphous oxide semiconductor layer can be suppressed by adding silicon to the amorphous oxide semiconductor layer, the oxide semiconductor layer can be formed using a target containing, for example, 2 wt% or more and 10 wt% or less of SiO ₂ .

A target having a composition ratio of, for example, In ₂ O ₃ : Ga ₂ O ₃ : ZnO = 1: 1: 1 [molar ratio] is used as the target for forming the oxide semiconductor layer by a sputtering method It is possible. And a target having a composition ratio of In ₂ O ₃ : Ga ₂ O ₃ : ZnO = 1: 1: 2 [molar ratio] or a target having a composition ratio of In ₂ O ₃ : Ga ₂ O ₃ : ZnO = 1: 1: 4 [molar ratio] It is possible to use a target having a composition ratio. The filling rate of the metal oxide target is 90% or more and 100% or less, and preferably 95% or more (for example, 99.9%). With the use of a metal oxide target having a high filling rate, an oxide semiconductor layer which is a dense film can be formed.

The atmosphere in which the oxide semiconductor layer is formed is preferably a rare gas (usually argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of rare gas (typically argon) and oxygen. Specifically, it is preferable to use a high-purity gas atmosphere in which impurities such as hydrogen, water, hydroxyl groups, or hydrides are removed at a concentration of 1 ppm or less (preferably 1 ppb or less).

When the oxide semiconductor layer is formed, the substrate is maintained in a processing chamber maintained at a reduced pressure, and the substrate temperature is set to be not less than 100 ° C and not more than 600 ° C, preferably not less than 200 ° C and not more than 400 ° C. By forming the oxide semiconductor layer while heating the substrate, the impurity concentration of the oxide semiconductor layer can be reduced. In addition, damage due to sputtering can be reduced. Thereafter, hydrogen and water are removed from the sputtering gas, and the oxide semiconductor layer is formed using a metal oxide as a target.

In order to remove moisture remaining in the treatment chamber, a suction type vacuum pump is preferably used. For example, a cryo pump, an ion pump, or a titanium sublimation pump may be used. The exhaust unit may be a turbo pump with a cold trap. (Preferably, a compound containing a carbon atom) containing a hydrogen atom such as a hydrogen atom or water (H ₂ O) is removed from the film forming chamber which is exhausted with the cryopump, Thereby reducing the concentration of impurities contained in the formed oxide semiconductor layer.

The oxide semiconductor layer is formed, for example, under the following conditions: the distance between the substrate and the target is 100 mm; The pressure is 0.6 Pa; The direct current (DC) power is 0.5 kW; The atmosphere is oxygen (100% oxygen). Note that it is desirable to use a pulsed direct current (DC) power source because the dust can be reduced and the film thickness can be uniform. The thickness of the oxide semiconductor layer is 2 nm or more and 200 nm or less, preferably 5 nm or more and 30 nm or less. An appropriate thickness of the oxide semiconductor layer is different depending on the oxide semiconductor material used; Therefore, the thickness can be determined according to the material. When the channel length is short, the thickness of the oxide semiconductor layer may be set to, for example, 5 nm or more and 30 nm or less. When the size of the device is reduced in this manner, high integration can be achieved and the short-channel effect can be suppressed by the reduction of the thickness of the oxide semiconductor layer.

It is preferable to perform inverse sputtering in which plasma is generated with the introduced argon gas before the oxide semiconductor layer is formed by the sputtering method so that the dust adhering to the surface of the gate insulating layer 138 is removed Be careful. Here, the inverse sputtering is a method in which ions collide with the surface to be treated such that the surface is changed, in contrast to the normal sputtering in which ions collide with the sputtering target. One example of a method for causing ions to collide with a surface to be treated is how a high-frequency voltage is applied to the surface in an argon atmosphere and a plasma is generated near the substrate. Note that an atmosphere of nitrogen, helium, oxygen, etc. may be used instead of the argon atmosphere.

Dry etching or wet etching may be used to etch the oxide semiconductor layer. It goes without saying that dry etching and wet etching can be used in combination. The etching conditions (e.g., etching gas or etchant, etching time, and temperature) are appropriately set depending on the material so that the oxide semiconductor layer can be etched into a desired shape.

One example of the etching gas used for dry etching is a chlorine-containing gas (chlorine gas such as chlorine (Cl ₂ ), boron trichloride (BCl ₃ ), silicon tetrachloride (SiCl ₄ ), or carbon tetrachloride (CCl ₄ ) . In addition, fluorine-containing gases such as carbon tetrafluoride (CF ₄ ), hexafluorosulfide (SF ₆ ), nitrogen trifluoride (NF ₃ ), or trifluoromethane (CHF ₃ ) , Oxygen (O ₂ ), helium (He) or argon (Ar) may be used.

As the dry etching method, a parallel plate type RIE (reactive ion etching) method or ICP (inductively coupled plasma) etching method can be used. (For example, the amount of power applied to the coil electrode, the amount of power applied to the electrode on the substrate side, and the electrode temperature on the substrate side) to properly etch the oxide semiconductor layer into a desired shape do.

As the etchant used for the wet etching, a mixed solution of phosphoric acid, acetic acid, nitric acid, ammonia and water (mixed solution of ammonia, water, and hydrogen peroxide solution) and the like may be used. An etchant such as ITO07N (manufactured by KANTO CHEMICAL CO., INC.) May also be used.

Next, a first heat treatment is preferably performed on the oxide semiconductor layer. The oxide semiconductor layer may be dehydrated or dehydrogenated by the first heat treatment. The temperature of the first heat treatment is 300 ° C to 800 ° C, preferably 400 ° C to 700 ° C, more preferably 450 ° C to 700 ° C, and even more preferably 550 ° C to 700 ° C.

The first heat treatment at a temperature of 350 DEG C or higher allows dehydration or dehydrogenation of the oxide semiconductor layer, which results in a reduction of the hydrogen concentration in the layer. The first heat treatment at a temperature of 450 [deg.] C or higher permits further reduction of the hydrogen concentration in the layer. The first heat treatment at a temperature of 550 [deg.] C or higher permits a further further reduction in the hydrogen concentration in the layer. The first heat treatment is performed, for example, in such a manner that the substrate is introduced into an electric furnace using a resistance heating element or the like, and then the oxide semiconductor layer 140 is thermally treated at 450 DEG C for 1 hour under a nitrogen atmosphere . During the heat treatment, the oxide semiconductor layer 140 is not exposed to air to prevent entry of water or hydrogen.

The heat treatment apparatus is not limited to an electric furnace, and it is also possible to use an apparatus for heating the article to be treated by using heat conduction or thermal radiation generated from a medium such as heated gas. For example, RTA (Rapid Thermal Anneal) devices such as GRTA (Gas Rapid Thermal Anneal) devices or LRTA (Rapid Thermal Annealing) devices can be used.

The LRTA device is an apparatus for heating a material to be processed by radiation (electromagnetic waves) of light emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. The GRTA apparatus is a device for performing heat treatment using high-temperature gas. As the gas, an inert gas which does not react with the object to be treated by heat treatment, for example, a rare gas such as nitrogen or argon is used.

For example, as the first heat treatment, the GRTA treatment can be performed as follows. The substrate is placed in an inert gas atmosphere heated to a high temperature of 650 ° C to 700 ° C, heated for several minutes, and then taken out of the inert gas. The GRTA treatment enables high-temperature heat treatment for a short time. In addition, the GRTA treatment can be used even when the temperature exceeds the upper temperature limit of the substrate because the heat treatment is performed in a short time. For example, when an SOI substrate including a substrate having a relatively low heat resistance such as a glass substrate is used, shrinkage of the substrate is a problem at a temperature higher than the heat resistance temperature (strain point), but heat treatment is performed for a short time This is not a problem.

It is preferable to use an atmosphere containing nitrogen or a rare gas (e.g., helium, neon, or argon) as its main component and not containing water, hydrogen, or the like as the inert gas atmosphere in which the first heat treatment is performed Note that. For example, the purity of nitrogen or a rare gas such as helium, neon, or argon introduced into the heat treatment apparatus is not less than 6N (99.9999%), preferably not less than 7N (99.99999% Or less, preferably 0.1 ppm or less).

Note that the inert gas atmosphere may be changed during the process in an atmosphere containing oxygen. For example, when an electric furnace is used in the first heat treatment, the atmosphere can be changed when the heat treatment temperature falls. (At a constant temperature) of an inert gas such as, for example, rare gas (e.g., helium, neon, or argon) or nitrogen, and the atmosphere is an atmosphere containing oxygen . &Lt; / RTI &gt; As the atmosphere containing oxygen, an oxygen gas or a mixed gas of oxygen gas and nitrogen gas may be used. When an atmosphere containing oxygen is used, it is preferable that the atmosphere does not contain water, hydrogen, or the like. Alternatively, the purity of the oxygen gas or nitrogen is preferably 6N (99.9999%) or more, more preferably 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less )to be. Defects caused by oxygen depletion can be reduced by performing the first thermal treatment in an atmosphere containing oxygen.

Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer is crystallized to become microcrystalline or polycrystalline. For example, in some cases, the oxide semiconductor layer is crystallized to be a microcrystalline oxide semiconductor layer having a crystallinity of 90% or more, or 80% or more. In other cases, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may be an amorphous oxide semiconductor layer not containing a crystal component.

Further, in the oxide semiconductor layer, microcrystalline (particle diameter of 1 nm or more and 20 nm or less, typically 2 nm or less and 4 nm or less) is occasionally mixed in an amorphous oxide semiconductor (for example, at the surface of the oxide semiconductor layer).

The electrical characteristics of the oxide semiconductor layer can be changed by arranging the microcrystals in the amorphous semiconductor. For example, when the oxide semiconductor layer is formed using an In-Ga-Zn-O-based metal oxide target, a microcrystalline portion in which crystal grains of In ₂ Ga ₂ ZnO ₇ having electrical anisotropy are arranged is formed, Whereby the electrical characteristics of the oxide semiconductor layer can be changed.

For example, when the crystal grains are arranged so that the c-axis of In ₂ Ga ₂ ZnO ₇ is perpendicular to the surface of the oxide semiconductor layer, the conductivity in a direction parallel to the surface of the oxide semiconductor layer can be improved, The insulating properties in a direction perpendicular to the surface of the oxide semiconductor layer can be improved. Moreover, such a microcrystalline portion has a function of suppressing the entry of impurities such as water or hydrogen into the oxide semiconductor layer.

Note that the oxide semiconductor layer including the microcrystalline portion can be formed by heating the surface of the oxide semiconductor layer by GRTA treatment. In addition, the oxide semiconductor layer can be formed in a more preferable manner by using a sputtering target in which the amount of Zn is smaller than that of In or Ga.

The first thermal treatment for the oxide semiconductor layer 140 may be performed on the oxide semiconductor layer that has not yet been treated with the island-shaped oxide semiconductor layer 140. In this case, after the first heat treatment, the substrate is taken out of the heating apparatus and a photolithography step is performed.

Note that the above-described heat treatment may also be called as dehydration treatment, dehydrogenation treatment or the like due to the effect of dehydration or dehydrogenation of the oxide semiconductor layer 140. This dehydration treatment or dehydrogenation treatment may be performed after the oxide semiconductor layer is formed, for example, after the source electrode and the drain electrode are laminated on the oxide semiconductor layer 140, or after the protective insulating layer is formed on the source and drain electrodes May be carried out after being formed on the substrate. Such a dehydration treatment or dehydrogenation treatment may be performed once or plural times.

Next, the source or drain electrode 142a and the source or drain electrode 142b are formed in contact with the oxide semiconductor layer 140 (see FIG. 5F). The source or drain electrodes 142a and 142b may be formed in such a manner that a conductive layer is formed to cover the oxide semiconductor layer 140 and then selectively etched.

The conductive layer may be formed by a CVD (Chemical Vapor Deposition) method such as a PVD (physical vapor deposition) method such as a sputtering method or a plasma CVD method. As the material for the conductive layer, one element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, or tungsten; An alloy including any one of these elements may be used as the component. Alternatively, one or more materials selected from manganese, magnesium, zirconium, beryllium, and yttrium may be used. Aluminum combined with at least one of the elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, or scandium may be used.

An oxide conductive film may be used for the conductive layer. As the oxide conductive film, indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), indium oxide-tin oxide alloy (In ₂ O ₃ -SnO ₂ , , Indium oxide-zinc oxide (In ₂ O ₃ -ZnO), or any of these metal oxide materials to which silicon or silicon oxide is added can be used.

In this case, it is preferable to use a material having a high conductivity and a low resistivity as compared with the material used for the oxide semiconductor layer 140. The conductivity of the oxide conductive film can be increased by the increase in the carrier concentration. The carrier concentration of the oxide conductive film can be increased by the increase in the hydrogen concentration. Further, the carrier concentration of the oxide conductive film can be increased by an increase in oxygen depletion.

The conductive layer may have a single layer structure or a laminated structure including two or more layers. For example, the conductive layer may have a single-layer structure of an aluminum film including silicon, a two-layer structure in which a titanium film is stacked on an aluminum film, or a three-layer structure in which a titanium film, an aluminum film, and a titanium film are stacked in this order have. Here, a three-layer structure of a titanium film, an aluminum film, and a titanium film is used.

An oxide conductive layer may be formed between the oxide semiconductor layer 140 and the conductive layer. The oxide conductive layer and the conductive layer may be formed continuously (continuous film formation). This oxide conductive layer allows to reduce the resistance of the source region or the drain region, so that the transistor can operate at high speed.

Next, the conductive layer is selectively etched to form the source or drain electrodes 142a and 142b (see FIG. 5F). Here, ultraviolet light, KrF laser light, or ArF laser light is preferably used for exposure when forming a mask used for etching.

The channel length L of the transistor is determined by the distance between the lower end of the source or drain electrode 142a and the lower end of the source or drain electrode 142b. Note that in the case where the exposure is performed such that the channel length L is less than 25 nm, the exposure for forming the mask is performed with very short ultraviolet rays of wavelengths ranging from several nanometers to tens of nanometers. Exposure with ultraviolet rays results in high resolution and large depth of focus. For these reasons, it is possible to design the mask so that the channel length L of the transistor to be formed later is in the range of less than 25 nm, i.e., 10 nm or more and 1000 nm or less, and the circuit can operate at a higher speed. In addition, the off-state current is very low, which prevents the power consumption from increasing.

Materials and etching conditions of the conductive layer and the oxide semiconductor layer 140 are appropriately adjusted so that the oxide semiconductor layer 140 is not removed at the time of etching the conductive layer. Note that depending on the materials and the etching conditions, the oxide semiconductor layer 140 is partially etched in the etching step and thus has a trench (recess).

To reduce the number of masks used and reduce the number of steps, a resist mask may be formed using a multi-tone mask, which is an exposure mask through which light is transmitted to have a plurality of intensities, Can be performed by using such a resist mask. A resist mask formed using a multi-gradation mask has a shape having a plurality of thicknesses (step-shaped shape) and can be changed in shape by ashing; Thus, the resist mask may be used for a plurality of etching steps for processing with different patterns. That is, a resist mask corresponding to at least two kinds of different patterns can be formed by using a multi-gradation mask. Thus, the number of exposure masks can be reduced, and the number of corresponding photolithography steps can also be reduced, thereby simplifying the processing.

Note that after this step, the plasma treatment is performed using a gas such as N ₂ O, N ₂ , or Ar. Such a plasma treatment removes water or the like adhering to the exposed surface of the oxide semiconductor layer. The plasma treatment may be performed using a mixed gas of oxygen and argon.

Next, the protective insulating layer 144 is formed in contact with a part of the oxide semiconductor layer 140 without exposure to the air (see FIG. 5G).

The protective insulating layer 144 may be formed by appropriately using a method such as a sputtering method in which impurities such as water and hydrogen are prevented from being mixed in the protective insulating layer 144. The protective insulating layer 144 has a thickness of at least 1 nm or more. The protective insulating layer 144 may be formed of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like. The protective insulating layer 144 may have a single-layer structure or a stacked-layer structure. The substrate temperature when forming the protective insulating layer 144 is preferably room temperature to 300 占 폚. The atmosphere for forming the protective insulating layer 144 is preferably a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere containing rare gas (typically argon) and oxygen.

If hydrogen is included in the protective insulating layer 144, the hydrogen may enter the oxide semiconductor layer or may extract oxygen from the oxide semiconductor layer, whereby the resistance of the oxide semiconductor layer on the back channel side Can be reduced and a parasitic channel can be formed. Therefore, it is important not to use hydrogen when forming the protective insulating layer 144 such that the protective insulating layer 144 contains as little hydrogen as possible.

In addition, the protective insulating layer 144 may be formed while moisture remaining in the process chamber is removed. This is to prevent hydrogen, hydroxyl groups, or moisture from being contained in the oxide semiconductor layer 140 and the protective insulating layer 144.

In order to remove moisture remaining in the treatment chamber, a suction type vacuum pump is preferably used. For example, a cryo pump, an ion pump, or a titanium sublimation pump is preferably used. The exhaust unit may be a turbo pump with a cold trap. A hydrogen atom, a compound containing hydrogen atoms such as water (H ₂ O), and the like are removed from the film formation chamber that is exhausted with the cryo pump, thereby forming a protective film on the protective insulating layer 144 The concentration of the impurities can be reduced.

As the sputtering gas used for forming the protective insulating layer 144, impurities such as hydrogen, water, hydroxyl, or hydride are removed at a concentration of 1 ppm or less (preferably, 1 ppb or less) It is preferable to use gas.

Next, the second heat treatment is preferably carried out in an inert gas atmosphere or an oxygen gas atmosphere (preferably 200 DEG C to 400 DEG C, for example, 250 DEG C to 350 DEG C). For example, the second heat treatment is performed at 250 DEG C for 1 hour in a nitrogen atmosphere. The second thermal processing may reduce variations in the electrical characteristics of the transistor.

Further, the heat treatment may be performed in the air at 100 占 폚 to 200 占 폚 for 1 hour to 30 hours. This heat treatment can be carried out at a constant heating temperature; Alternatively, the increase in the heating temperature at room temperature to 100 ° C or higher and 200 ° C or lower and the decrease in the heating temperature to room temperature may be repeatedly performed a plurality of times. This heat treatment can be performed under a reduced pressure before the protective insulating layer is formed. The heat treatment time can be shortened under the reduced pressure. This heat treatment may be performed, for example, instead of the second heat treatment, or may be performed before or after the second heat treatment.

Next, the interlayer insulating layer 146 is formed on the protective insulating layer 144 (see FIG. 6A). The interlayer insulating layer 146 may be formed by a PVD method, a CVD method, or the like. The interlayer insulating layer 146 may be formed of an inorganic insulating material such as silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, or tantalum oxide. After the formation of the interlayer insulating layer 146, the surface of the interlayer insulating layer 146 is preferably planarized by CMP, etching, or the like.

Next, openings reaching the electrodes 136a, 136b, 136c and the source or drain electrodes 142a, 142b are formed in the interlayer insulating layer 146, the protective insulating layer 144, Layer 138 as shown in FIG. Thereafter, a conductive layer 148 is formed to be embedded in the openings (see FIG. 6B). The openings may be formed by a method such as etching using a mask. The mask may be formed by a method such as exposure using a photomask.

Wet etch or dry etch may be used as the etch; Dry etching is preferably used for micronization. The conductive layer 148 may be formed by a film forming method such as a PVD method or a CVD method. The conductive layer 134 may be formed of a conductive material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium or an alloy or compound (e.g., nitride) of any of these materials. As shown in FIG.

Specifically, for example, the conductive layer 148 can be formed as follows: a thin titanium film is formed by the PVD method in the region including the openings, and a thin titanium nitride film is formed by the CVD method; A tungsten film is then formed to be embedded in the openings. Here, the titanium film formed by the PVD method can reduce the oxide film that can be formed at the interface and lower electrodes (here, the electrodes 136A, 136B, 136c and the source or drain electrodes 142a, 142b ) Of the contact resistance. The titanium nitride film formed after formation of the titanium film has a barrier function to prevent diffusion of the conductive material. The copper film may be formed by a plating method after formation of a barrier film such as titanium or titanium nitride.

After the conductive layer 148 is formed, a part of the conductive layer 148 is removed by etching, CMP, or the like so that the interlayer insulating layer 146 is exposed and the electrodes 150a, 150b, 150c, 150d, 150e (See Fig. 6C). Note that when the electrodes 150a, 150b, 150c, 150d, 150e are formed by removing a portion of the conductive layer 148, the surfaces are preferably treated to be planarized. When the surfaces of the interlayer insulating layer 146 and the electrodes 150a, 150b, 150c, 150d and 150e are planarized in this manner, the electrode, wiring, insulating layer, semiconductor layer, .

Thereafter, the insulating layer 152 is formed, and openings reaching the electrodes 150a, 150b, 150c, 150d, and 150e are formed in the insulating layer 152. [ After the conductive layer is formed to be embedded in the openings, a part of the conductive layer is removed by etching, CMP, or the like, and the insulating layer 152 is exposed and the electrodes 154a, 154b, 154c, and 154d are formed (See FIG. 6D). This step is similar to the step of forming the electrode 150a and the like; Therefore, detailed description is omitted.

When the transistor 402 is formed in the above-described manner, the hydrogen concentration in the oxide semiconductor layer 140 is 5 × 10 ¹⁹ / cm 3 or less and the off-state current of the transistor 402 at room temperature is 1 × 10 ^-13 A or less (the leakage current at room temperature per 1 m of the channel width is 10 aA / 占 퐉 or less). The carrier concentration of the oxide semiconductor layer is less than 1 x 10 ¹⁴ / cm 3. The transistor 402 with excellent characteristics can be obtained by using such an oxide semiconductor layer 140 that is sufficiently purified at a hydrogen concentration and highly purified by the supply of oxygen. Further, since the transistor 421 provided with the material other than the oxide semiconductor is provided below and the transistor 402 using the oxide semiconductor is provided on the upper side, an excellent nonvolatile latch circuit having characteristics of all of the transistors, It is possible to manufacture a semiconductor device using a nonvolatile latch circuit.

Since oxygen, water, or the like is not likely to enter the oxide semiconductor layer, and thus an oxide semiconductor layer having very good characteristics can be realized, oxygen is supplied to the oxide semiconductor layer 140 immediately after the hydrogen concentration is reduced . Needless to say, the treatment for reducing the hydrogen concentration and the treatment for supplying oxygen need not be performed continuously as long as the oxide semiconductor layer having good characteristics can be realized. For example, another process may be performed between these processes. Alternatively, these processes may be performed simultaneously.

Note that silicon carbide (e.g., 4H-SiC) is a semiconductor material that can be compared to oxide semiconductors. Oxide semiconductors and 4H-SiC have some commonalities: for example, carrier density. According to the Fermi-Dirac distribution, the density of minority carriers in oxide semiconductors is estimated to be approximately 10 ^-7 / cm3. This value is very small, similar to that of 4H-SiC, i.e., 6.7 x 10 &lt; ^-11 &gt; / cm &lt; 3 &gt;. It is easily understood that when the minority carrier density of the oxide semiconductor is compared with the intrinsic carrier density of silicon (approximately 1.4 x 10 ¹⁰ / cm 3), the minority carrier density of the oxide semiconductor is significantly low.

In addition, the energy band gap of the oxide semiconductor is 3.0 eV or more and 3.5 eV or less, and that of 4H-SiC is 3.26 eV, which means that both the oxide semiconductor and the silicon carbide are wide band gap semiconductors.

On the other hand, there is a major difference between the oxide semiconductor and the silicon carbide: the processing temperature. Since heat treatment at 1500 deg. C or higher and 2000 deg. C or lower is usually required in semiconductor processing using silicon carbide, it is difficult to form a laminate of silicon carbide and semiconductor elements by using a semiconductor material other than silicon carbide. This is because the semiconductor substrate, the semiconductor element, and the like are damaged by such a high temperature. On the other hand, the oxide semiconductor can be formed by heat treatment at 300 DEG C or higher and 500 DEG C or lower (glass transition temperature or lower, up to about 700 DEG C); Therefore, it is possible to form an integrated circuit by using a semiconductor material other than an oxide semiconductor, and thereafter form a semiconductor element including an oxide semiconductor.

Also, in contrast to silicon carbide, oxide semiconductors are advantageous in that low heat-resistant substrates such as glass substrates can be used. In addition, the oxide semiconductor is also advantageous in that the energy costs can be sufficiently reduced as compared with the silicon carbide because heat treatment at a high temperature is not required.

Although much work has been done on the physical properties of oxide semiconductors, such as density of states (DOS), note that they do not suggest the idea of sufficiently reducing the localized levels themselves. According to one embodiment of the disclosed invention, a high purity oxide semiconductor is formed by removing water or hydrogen which may be the cause of localized levels. This is based on the idea of sufficiently reducing the localized levels themselves. Thus, good industrial products can be produced.

Further, a higher purity (i-type) oxide semiconductor can be obtained by supplying oxygen to a dangling bond of a metal produced by oxygen depletion and reducing the localized level due to the oxygen depletion. For example, an oxide film containing excess oxygen is formed close to the channel forming region, and then oxygen is supplied from the oxide film to the channel forming region, so that localized levels due to oxygen defects can be reduced.

The defect in the oxide semiconductor is said to be due to excessive hydrogen, a shallow level of 0.1 eV to 0.2 eV below the conduction band, a deep level due to lack of oxygen, and the like. For the elimination of these defects, thorough removal of hydrogen and sufficient supply of oxygen will be correct as a technical idea.

Although oxide semiconductors are generally considered as n-type semiconductors, according to one embodiment of the disclosed invention, an i-type semiconductor is realized by removing impurities, particularly water and hydrogen. In this respect, it can be said that one embodiment of the disclosed invention differs from i-type semiconductors such as silicon added to impurities and therefore includes new technical ideas.

In the above-described example, among elements of the nonvolatile latch circuit 400, elements other than the transistor 402 using an oxide semiconductor use a material other than an oxide semiconductor as a semiconductor material; It is not limited to this example of the disclosed invention. The oxide semiconductor may be used as a semiconductor material of the elements other than the transistor 402 included in the nonvolatile latch circuit 400. [

<Electrical Conduction Mechanism of Transistor Using Oxide Semiconductor>

The electrical conduction mechanism of a transistor using an oxide semiconductor will be described with reference to Figs. 7, 8. Figs. 9A and 9B, and Fig. Note that the following description is based on the ideal situation for ease of understanding and does not fully reflect the actual situation. It is also noted that the following description is merely a consideration and does not affect the effectiveness of the present invention.

7 is a cross-sectional view of a transistor (thin film transistor) using an oxide semiconductor. An oxide semiconductor layer OS is provided on the gate electrode GE1 with a gate insulating layer GI sandwiched therebetween and a source electrode S and a drain electrode D are provided on the oxide semiconductor layer. An insulating layer is provided to cover the source electrode (S) and the drain electrode (D).

FIG. 8 is an energy band diagram (schematic diagram) of the section A-A 'in FIG. In Fig. 8, black circles (●) and white circles (○) represent electrons and holes and have charges (-q, + q), respectively. A positive voltage (V _D > 0) is applied to the drain electrode, a broken line shows a case where no voltage is applied to the gate electrode (V _G = 0) (V _G > 0). When no voltage is applied to the gate electrode, carriers are not injected from the electrode toward the oxide semiconductor due to the high potential barrier, so that current does not flow, which means OFF state. On the other hand, when a positive voltage is applied to the gate electrode, the potential barrier is lowered and therefore the current flows, which means the ON state.

FIGS. 9A and 9B are energy band diagrams (schematic diagrams) along B-B 'in FIG. Figure 9a is a positive voltage (V _G> 0) it is applied and carriers (electrodes) shows a state in which flows between the source electrode and the drain electrode to the gate electrode (GE1). FIG. 9B shows an OFF state in which a negative voltage (V _G < 0) is applied to the gate electrode GE1 and no minority carriers flow.

Figure 10 shows the relationships between the vacuum level and the work function (? _M ) of the metal and the relationship between the vacuum level and the electron affinity (?) Of the oxide semiconductor. At room temperature, electrons in the metal are degenerated and the Fermi level is located within the conductive band. On the other hand, a conventional oxide semiconductor is an n-type semiconductor wherein the Fermi level (E _F ) is located farther away from the intrinsic Fermi level (E _i ) located in the center of the band gap and closer to the conductive band . Note that some of the hydrogen is a donor in oxide semiconductors and that oxide semiconductors are one of the factors that make them n-type semiconductors.

On the other hand, the oxide semiconductor according to an embodiment of the disclosed invention removes hydrogen as a factor for the n-type oxide semiconductor from the oxide semiconductor and includes as few elements (i.e., impurity element) as the main component than the oxide semiconductor (I-type) or substantially intrinsic oxide semiconductor obtained by highly purifying the oxide semiconductor so that the oxide semiconductor is highly purified. That is, the feature is obtained by removing impurities such as hydrogen and water as much as possible, rather than adding a high-purity i-type (intrinsic) semiconductor or a semiconductor near it, by adding an impurity element. Therefore, the Fermi level (E _F ) may be comparable to the intrinsic Fermi level (E _i ).

The band gap (E _g ) of the oxide semiconductor is 3.15 eV and its electron affinity (χ) is 4.3 eV. The work function of titanium (Ti) contained in the source electrode and the drain electrode is substantially equal to the electron affinity (x) of the oxide semiconductor. In this case, a Schottky barrier for electrons is not formed at the interface between the metal and the oxide semiconductor.

At this time, as shown in FIG. 9A, the electrons move in the vicinity of the interface between the gate insulating layer and the highly-purified oxide semiconductor (the lower portion of the oxide semiconductor which is stable with respect to energy).

Further, as shown in Fig. 9B, when a negative potential is supplied to the gate electrode GE1, the value of the current is very close to zero because the number of holes, which are minority carriers, is substantially zero.

In this way, intrinsic (i-type) or substantially intrinsic oxide semiconductors are obtained by high purity such that elements other than its principal component (i.e., impurity element) are contained as little as possible. Therefore, the characteristics of the interface between the oxide semiconductor and the gate insulating layer become important. For this reason, the gate insulating layer is required to form a good interface with the oxide semiconductor. In detail, for example, the following insulating layers are preferably used: an insulating layer formed by a CVD method using a high-density plasma produced with a power supply frequency in the range of VHF band to microwave band, or an insulating layer formed by sputtering An insulating layer formed by the method.

When the oxide semiconductor is highly purified while a good interface is made between the oxide semiconductor and the gate insulating layer, for example, when the transistor has a channel width W of 1 x 10 ⁴ m and a channel length L of 3 m It is possible to realize an off-state current of 1 x 10 &lt; ^-13 &gt; A or less at room temperature and a swing (S value) of less than or equal to a threshold value of 0.1 V / dec (gate insulating layer: 100 nm thick).

When the oxide semiconductor is highly refined as described above so as to contain as few elements as possible (i.e., impurity element) other than its oxide, the thin film transistor can operate in a good manner.

According to this embodiment, as the semiconductor material in the channel forming region, a transistor using an intrinsic (i-type) or substantially intrinsic (i-type) oxide semiconductor having a sufficiently low hydrogen concentration and sufficiently low carrier concentration to be high purity The capacitance element being used as the switching element and being electrically connected to the source electrode or the drain electrode of the transistor is provided; Therefore, a non-volatile latch circuit that operates over a wide temperature range and operates stably even at high temperatures and does not erase the stored logic state even when the power supply is turned off, or a latch circuit with sufficiently long refresh time and data retention It is possible to implement. Further, since the electric charge accumulated in the capacitive element is held as data, the data can be easily read with less variation compared with the case where data is stored by the residual polarization.

Various types of logic circuits may be provided by using the non-volatile latch circuit. For example, the power consumption of the logic circuit using the non-volatile latch circuit can be reduced by turning off the power of unused blocks. Also, since the logic state is stored even when the power supply is turned off, the system can be started when the power is turned on at high speed and low power, or can be terminated when the power supply is turned off.

This embodiment can be freely combined with other embodiments.

(Example 2)

In this embodiment, the configuration and operation of the non-volatile latch circuit which is one embodiment of the disclosed invention will be described with reference to Figs. 11A, 11B, and 12. Fig.

FIG. 11A shows the configuration of the non-volatile latch circuit 400. FIG. Fig. 11B shows a configuration of a part of the non-volatile latch circuit 400. Fig. FIG. 12 is an example of a timing chart of the non-volatile latch circuit 400. FIG.

FIG. 11A shows an example of the above configuration of the latch circuit 400 in FIG. 1, wherein the first inverter is used as the first element 412 and the second inverter is used as the second element 413 do. The first transistor 431 and the second transistor 432 may have a structure similar to that shown in the first embodiment. That is, as the first transistor 431 and the second transistor 432, it is possible to use a transistor having an oxide semiconductor layer for a channel forming region and having normally off characteristics and a significantly low off-state current It is possible.

The non-volatile latch circuit 400 shown in FIG. 11A is configured such that the output of the first element (first inverter) 412 is electrically connected to the input of the second element (second inverter) 413, And the output of the second element (the second inverter) is electrically connected to the input of the first element (the first inverter) 412 through the second transistor 432.

The input of the first element (first inverter) 412 is electrically connected to the wiring 414 to which an input signal is applied through the first transistor 431. The output of the first element (first inverter) 412 is electrically connected to the wiring 415 to which an output signal is applied. The wiring 414 to which an input signal is applied is a wiring which receives a signal input from the circuit of the previous stage to the non-volatile latch circuit 400. The wiring 415 to which the output signal is applied is a wiring which receives a signal output from the non-volatile latch circuit 400 to the next stage circuit.

In the non-volatile latch circuit 400, the first transistor 431 and the second transistor 432, each of which uses an oxide semiconductor as a semiconductor material of the channel forming region, are used as switching elements. The non-volatile latch circuit 400 includes a capacitive element 404 electrically connected to a source electrode or a drain electrode of the first transistor 431 and the second transistor 432. That is, one electrode of the capacitive element 404 is electrically connected to one of the source electrode and the drain electrode of the first transistor 431, and one electrode of the capacitive element 404 is electrically connected to the second transistor 432 and the drain electrode. The other of the source electrode and the drain electrode of the first transistor 431 is electrically connected to the wiring 414 to which an input signal is applied. The other of the source electrode and the drain electrode of the second transistor 432 is electrically connected to the output of the second element (second inverter) 413. The potential V _C is applied to the other electrode of the capacitor device 404. A node connected to the input of the first element (first inverter) 412 is denoted as node S.

As shown in FIG. 11B, the first element (first inverter) 412 included in the non-volatile latch circuit 400 includes at least a third transistor 421. The gate of the third transistor 421 is electrically connected to the input of the first element (first inverter) 412. That is, the gate of the third transistor 421 is electrically connected to one of the source electrode and the drain electrode of the second transistor 432. Furthermore, the gate of the third transistor 421 is electrically connected to one of the source electrode and the drain electrode of the first transistor 431.

The first transistor 431 and the second transistor 432 may have the structure shown in FIG. 2A or 2B instead of the structure shown in FIG. 11A.

The potential of the input signal IN is applied to the wiring 414 from the circuit of the previous stage. The potential of the wiring 415 is applied as an output signal OUT to a circuit of a subsequent stage. The potential of the signal? 1 is applied to the first transistor 431. And the potential of the signal? 2 is applied to the second transistor 432. When the high-level potential is applied to the signal? 1, the first transistor 431 is turned on. When the high-level potential is applied to the signal? 2, the second transistor 432 is turned on. Although both the first transistor 431 and the second transistor 432 are n-type transistors, they may be p-type transistors.

In the normal operation period, the high-level power supply voltage VDD and the low-level power supply voltage VSS are supplied to the first element (first inverter) 412 and the second element (Second inverter) 413, as shown in Fig.

The data write, retain, and read operations of the non-volatile latch circuit 400 will be described with reference to FIG. 12 is a graph showing the relationship between the signal (phi 1) obtained during the period (operation period) during which the non-volatile latch circuit 400 is operated and during the period during which the non-volatile latch circuit 400 is not operated 2 shows an example of a timing chart of the potentials of the signal? 2, the input signal IN, and the output signal OUT. 12 also shows the potential of the node S in the latch circuit 400 and the potential of the node S applied to the first element (first inverter) 412 and the second element (second inverter) And the potential of the voltage VDD. Note that a predetermined potential V _C , for example, a ground potential, is applied to the other electrode of the capacitor device 404.

12, periods (a), (b), (d) and (e) are periods during which the latch circuit 400 operates (operation periods): the power supply voltage VDD and The power supply voltage VSS is applied to the first element (first inverter) 412 and the second element (second inverter) 413. The period (c) is a period during which the latch circuit 400 is not operated (non-operation period) and a power source to the first element (first inverter) 412 and the second element The supply of the voltage is stopped and the power supply voltage VDD is lowered. The period (a) and the period (e) are periods when the high-level potential and the low-level potential are alternately applied to the signal? 1 and the signal? 2, Operating periods. When the potential of the signal? 1 is at a low level, the potential of the signal? 2 is at a low level, and when the potential of the signal? 1 is at a low level, It is at a high level. That is, the signal? 1 and the signal? 2 have an inverted relationship. The period (b) is a preparation period until the non-operation period. The period (b) is also referred to as a falling period. The period (d) is a preparation period until the normal operation period after the non-operation period starts with the supply of electric power. The period (d) is also referred to as a rising period.

In the normal operation period (period a), when the high-level potential is applied to the signal? 1 and the low-level potential is applied to the signal? 2, While the first transistor 431 is turned on so that the loop structure of the latch circuit 400 (also referred to as an inverter loop) inputs the potential of the input signal to the first element (first inverter) 412 The potential of the input signal is inverted by the first element (first inverter) 412 and applied to the circuit of a subsequent stage as the output signal OUT. 1) and an output signal having a low level potential can be obtained when the input signal has a high-level potential. When a high-level potential is applied to the signal &lt; RTI ID = 0.0 &gt; When having a potential, an output signal having a high-level potential can be obtained.

When the low-level potential is applied to the signal? 1 and a high-level potential is applied to the signal? 2, the first transistor 431 is turned off and the second transistor 432 is turned off So that the potential of the output signal OUT is maintained (data is latched, i.e., the logic state of the latch circuit is maintained). The node S shows the potential of the input of the first inverter, which is the inversion potential of the output signal OUT in the normal operation period.

An input of the first element (first inverter) 412 is electrically connected to one electrode of the capacitor device 404 and the gate of the third transistor 421. Therefore, all the time data is written in the latch circuit, and the electric charge corresponding to the data is accumulated in the gate capacitance value of the capacitance element 404 and the third transistor 421. [ In other words, the data of the latch circuit 400 is automatically written to the non-volatile latch (data writing). A charge corresponding to the potential is accumulated in one electrode of the capacitor device 404 and the gate (node S) of the third transistor 421. [

The potential (low-level potential) for turning off the first transistor 431 and the second transistor 432 in the preparation period (period (b)) before the non-operation period is the signal (? 1) And the signal? 2, whereby the first transistor 431 and the second transistor 432 are turned off and the node S is in a floating state. As a result, the charge accumulated in the node S is held (data holding).

Next, the supply of the power supply voltage to the first element (first inverter) 412 and the second element (second inverter) 413 is stopped to lower the power supply voltage VDD, - the operating period (period (c)) starts. In the non-operating period (period (c)), the input signal IN and the output signal OUT may have any value between VDD and VSS. Here, a transistor having an oxide semiconductor layer for a channel forming region and having normally off characteristics and a significantly low off-state current is used as the first transistor 431 and the second transistor 432; Therefore, the charge (the charge stored in the node S) accumulated in the gate capacitance value of the capacitor device 404 and the third transistor 421 is not supplied to the latch circuit 400 (Period (c)) may continue to be maintained. Therefore, after the supply of the power supply voltage to the latch circuit 400 is stopped, the logic state of the latch circuit 400 can be stored. Note that when the power supply voltage VDD drops, the potential of the node S slightly changes in some cases due to the influence of capacitive coupling with the power supply voltage. It is needless to say that the potential of the node S is restored to the original level when the power source voltage VDD is restarted to be supplied because the charge accumulated in the node S is continuously maintained.

The gate capacitance of the capacitive element 404 and the third transistor 421 is electrically connected to the input of the first element (first inverter) 412. Therefore, after the power supply voltage is restarted to be supplied to at least the first element (first inverter) 412 of the latch circuit 400 (period (d)), the potential of the output signal (Data recorded in the gate capacitance value of the device 404 and the third transistor 421). That is, the data recorded in the gate capacitance value of the capacitor device 404 and the third transistor 421 can be read (data read). As a result, the logic state of the latch circuit can be restored to before the non-operation period.

Next, a high-level potential is applied to the signal? 2. When the high-level potential is applied to the signal? 2, the second transistor 432 is turned on and an inverter loop is formed. When the inverter loop is formed, a high-level or low-level potential is applied to the output signal OUT and the node S and then held (data latched).

For example, when the power source is stopped for a long time, the potential of the node S is stored in the node S (the gate capacitance value of the capacitor device 404 and the third transistor 421) May be slightly shifted from the high-level or low-level potential due to the decrease in the amount of charge. Even in this case, a high-level potential or a low-level potential is applied again; As a result, the potential of the node S can be restored to the level before the shift (also called a rewrite operation). This operation is particularly effective when the gate capacitance values of the capacitance element 404 and the third transistor 421 have low capacitance values. Note that, in the period (d), the period during which the high-level potential is applied to the signal? 2 is not necessarily provided.

Next, a high-level potential and a low-level potential are applied to the signal? 1 and the signal? 2 so that a normal operation period (period (e)) is started. When the normal operation period (period (e)) starts, the signal (? 1) and the signal (? 2) are at the same potential as the previous normal operation period ), Or it may have an inverted potential (next state) of that when the period (a)) is completed.

According to this embodiment, as the semiconductor material in the channel forming region, a transistor using an intrinsic (i-type) or substantially intrinsic (i-type) oxide semiconductor having a hydrogen concentration sufficiently high so as to have a high purity and a sufficiently low carrier concentration A capacitive element which is used as a switching element and is electrically connected to the source electrode or the drain electrode of the transistor is provided; Therefore, a non-volatile latch circuit that operates over a wide temperature range and operates stably even at high temperatures and does not erase the stored logic state even when the power supply is turned off, or a latch circuit with sufficiently long refresh time and data retention It is possible to implement. Further, since the electric charge accumulated in the capacitive element is held as data, the data can be easily read with less variation compared with the case where data is stored by the residual polarization.

Various types of logic circuits may be provided by using the non-volatile latch circuit. For example, the power consumption of the logic circuit using the non-volatile latch circuit can be reduced by turning off the power of unused blocks. Also, since the logic state is stored even when the power supply is turned off, the system can be started when the power is turned on at high speed and low power, or can be terminated when the power supply is turned off.

This embodiment can be freely combined with other embodiments.

(Example 3)

In this embodiment, the operation of the non-volatile latch circuit, which is one embodiment of the disclosed invention, will be described with reference to Figs. 13A and 13B. The non-volatile latch circuit has the same configuration as that shown in Figs. 11A and 11B, and its timing chart is different from that of Fig.

13A is a timing chart showing the relationship between the signal φ1 obtained during the period in which the non-volatile latch circuit 400 operates (operation period) and the period during which the non-volatile latch circuit 400 is inactive (non-operation period) (2), an input signal (IN), and an output signal (OUT). 13A also shows the potential of the node S in the latch circuit 400 and the power supply voltage Vcc applied to the first element (first inverter) 412 and the second element (second inverter) (VDD) of the capacitive element 404, and the potential (V _C ) of the other electrode of the capacitive element 404.

13A, periods a, b, d, and e are periods during which the latch circuit 400 operates (operation periods): the power supply voltage VDD and The power supply voltage VSS is applied to the first element (first inverter) 412 and the second element (second inverter) 413. The period (c) is a period during which the latch circuit 400 is not operated (non-operation period) and a power source to the first element (first inverter) 412 and the second element The supply of the voltage is stopped and the power supply voltage VDD is lowered. The period (a) and the period (e) are periods when the high-level potential and the low-level potential are alternately applied to the signal? 1 and the signal? 2, Operating periods. When the potential of the signal? 1 is at a low level, the potential of the signal? 2 is at a low level, and when the potential of the signal? 1 is at a low level, It is at a high level. That is, the signal? 1 and the signal? 2 have an inverted relationship. The period (b) is a preparation period until the non-operation period. The period (b) is also referred to as a falling period. The period (d) is a preparation period until the normal operation period after the non-operation period starts with the supply of electric power. The period (d) is also referred to as a rising period.

In Fig. 13A, the operations in the period (a) and the period (b) are similar to those in Fig. Next, the supply of the power supply voltage to the first element (first inverter) 412 and the second element (second inverter) 413 stops to lower the power supply voltage VDD, The non-operation period (period (c)) begins. In the non-operating period (period (c)), the input signal IN and the output signal OUT may have any value between VDD and VSS. Here, a transistor having an oxide semiconductor layer for a channel forming region and having normally off characteristics and a significantly low off-state current is used as the first transistor 431 and the second transistor 432; Therefore, the charge (the charge stored in the node S) accumulated in the gate capacitance value of the capacitor device 404 and the third transistor 421 is supplied to the latch circuit 400 when the supply of the power supply voltage to the latch circuit 400 is stopped (Period (c)) may continue to be maintained. Therefore, after the supply of the power supply voltage to the latch circuit 400 is stopped, the logic state of the latch circuit 400 can be stored. Note that when the power supply voltage VDD is lowered, the potential of the node S slightly changes in some cases due to the influence of capacitive coupling with the power supply voltage. It is needless to say that the potential of the node S is restored to the original level when the power source voltage VDD is restarted to be supplied because the charge accumulated in the node S is continuously maintained.

Next, the potential (V _C ) of the other electrode of the capacitor device 404 is set to a predetermined potential. The potential V _C is set to a potential raised from a low level and a potential between the low level and the high level. As a result, an increase in the potential (V _C ) of the other electrode of the capacitive element 404 is added to the potential applied to the node S. When the power supply voltage is applied to the first element (first inverter) 412 and the second element (second inverter) 413 in this state (period d), the potential of the output signal OUT Is determined by the charge accumulated in the gate capacitance value of the capacitance element 404 and the third transistor 421. [ That is, the data recorded in the gate capacitance value of the capacitor device 404 and the third transistor 421 can be read (data read). As a result, the logic state of the latch circuit can be restored to before the non-operation period.

The potential V _C of the other electrode of the capacitive element 404 is set such that the supply of the power supply voltage to the first element (first inverter) 412 is restarted and the capacitive element 404 The data stored in (the data written in) the gate capacitance value of the third transistor 421 is set to a predetermined potential at the timing of reading, whereby the data reading can be performed more stably. For example, when the power supply voltage is stopped for a long time, the potential of the node S is decreased by a decrease in the amount of charge accumulated in the capacitance element 404 and the gate capacitance value of the third transistor 421 Level potential as shown in Fig. 13B, so that the stability of data reading can be degraded. This phenomenon is particularly likely to occur when the capacitance values of the capacitance element 404 and the third transistor 421 have low capacitance values. Even in this case, the potentials of the capacitive element 404 and the gate electrode of the third transistor may be set such that the potential V _C of the other electrode of the capacitive element 404 is set to a predetermined potential Lt; / RTI &gt; can be controlled to appropriate potentials. That is, the operation is enabled when the capacitance element is reduced in size, which achieves miniaturization. Further, the data holding period can be further increased.

Next, a high-level potential is applied to the signal? 2. When the high-level potential is applied to the signal? 2, the second transistor 432 is turned on and an inverter loop is formed. When the inverter loop is formed, a high-level or low-level potential is applied to the output signal OUT and the node S and then held (data is latched).

Even when the potential of the node S is slightly shifted from the high-level potential or the low-level potential at this time, the high-level potential or the low-level potential is again applied; As a result, the potential of the node S can be restored to the level before the shift (also referred to as a rewrite operation). After the potential of the node S is restored to the level before the shift (after the rewrite operation), the potential of V _C is restored to the original level.

Next, a high-level potential and a low-level potential are applied to the signal? 1 and the signal? 2 so that a normal operation period (period (e)) is started. When the normal operation period (period (e)) starts, the signal (? 1) and the signal (? 2) are at the same potential as the previous normal operation period ), Or it may have a reverse potential (next state) of that when the period (a) is completed.

According to this embodiment, as the semiconductor material in the channel forming region, a transistor using an intrinsic (i-type) or substantially intrinsic (i-type) oxide semiconductor having a hydrogen concentration sufficiently high so as to have a high purity and a sufficiently low carrier concentration A capacitive element which is used as a switching element and is electrically connected to the source electrode or the drain electrode of the transistor is provided; Therefore, a non-volatile latch circuit that operates over a wide temperature range and operates stably even at high temperatures and does not erase the stored logic state even when the power supply is turned off, or a latch circuit with sufficiently long refresh time and data retention It is possible to implement. Further, since the electric charge accumulated in the capacitive element is held as data, the data can be easily read with less variation compared with the case where data is stored by the residual polarization.

Various types of logic circuits may be provided by using the non-volatile latch circuit. For example, the power consumption of the logic circuit using the non-volatile latch circuit can be reduced by turning off the power of unused blocks. Also, since the logic state is stored even when the power supply is turned off, the system can be started when the power is turned on at high speed and low power, or can be terminated when the power supply is turned off.

This embodiment can be freely combined with other embodiments.

(Example 4)

In this embodiment, an example of the configuration of the non-volatile latch circuit which is an embodiment of the disclosed invention different from that of Fig. 1 will be described with reference to Fig. Fig. 14 shows the configuration of the non-volatile latch circuit 400. Fig.

14 is the same as that of FIG. 1 except that a capacitive element (the capacitive element 404 in FIG. 1) electrically connected to the input of the first element (D1) 412 is not provided. Do. That is, the non-volatile latch circuit 400 shown in FIG. 14 is configured such that the output of the first element D1 (412) is electrically connected to the input of the first element (D2) 413, And the output of the element D2 413 is electrically connected to the input of the first element D1 (412) through the second transistor 432. [

An input of the first device (D1) 412 is electrically connected to the wiring 414 to which an input signal is applied through the first transistor 431. [ The output of the first device (D1) 412 is electrically connected to the wiring 415 to which the output signal is applied. The wiring 414 to which an input signal is applied is a wiring which receives a signal input from the circuit of the previous stage to the non-volatile latch circuit 400. The wiring 415 to which the output signal is applied is a wiring which receives a signal output from the non-volatile latch circuit 400 to the next stage circuit.

In the non-volatile latch circuit 400, the first transistor 431 and the second transistor 432, each of which uses an oxide semiconductor as a semiconductor material of the channel forming region, are used as switching elements. The first transistor 431 and the second transistor 432 may have a structure similar to that shown in the first embodiment. That is, as the first transistor 431 and the second transistor 432, it is possible to use a transistor having an oxide semiconductor layer for a channel forming region and having normally off characteristics and a significantly low off-state current It is possible.

In the above configuration, the first element included in the non-volatile latch circuit 400 includes at least the third transistor 421. The gate of the third transistor 421 is electrically connected to the input of the first element 412. That is, the gate of the third transistor 421 is electrically connected to one of the source electrode and the drain electrode of the second transistor 432. Furthermore, the gate of the third transistor 421 is electrically connected to one of the source electrode and the drain electrode of the first transistor 431. The other of the source electrode and the drain electrode of the first transistor 431 is electrically connected to a wiring to which an input signal is applied. The other of the source electrode and the drain electrode of the second transistor 432 is electrically connected to the output of the second element.

The first transistor 431 and the second transistor 432 may have a structure shown in FIG. 2A or FIG. 2B instead of the structure shown in FIG.

In the non-volatile latch circuit having the configuration shown in Fig. 14, data writing, data holding, and data reading can be performed in the following manner.

The non-volatile latch circuit 400 is configured such that the output of the first device D1 412 is electrically connected to the input of the second device D2 413, D2) 413 is electrically connected to the input of the first device (D1) 412 through the second transistor 432. The first transistor The gate capacitance value of the third transistor 421 is electrically connected to a predetermined position in the loop structure. Specifically, the gate of the third transistor 421 is electrically connected to the input of the first device (D1) 412. In this manner, the gate capacitance value of the third transistor 421 is electrically connected to a predetermined position in the loop structure of the non-volatile latch circuit 400. Therefore, all the time data is written in the latch circuit, and the charge corresponding to the data is accumulated in the gate capacitance value of the third transistor 421. [ In other words, the data of the latch circuit 400 is automatically written to the non-volatile latch (data writing). Data rewriting can similarly be performed.

The data stored in the gate capacitance value of the third transistor 421, that is, the charge accumulated in the gate capacitance value of the third transistor 421, is supplied to the first transistor 431 and the second transistor 432, (Data retention) by applying a potential to the gate of the first transistor 431 and the gate of the second transistor 432 to be turned off.

Here, the transistors used as the first transistor 431 and the second transistor 432 use an oxide semiconductor layer for a channel forming region and have normally off characteristics and a very low off-state current. Therefore, the electric charge accumulated in the gate capacitance value is not supplied to the first element (D1) 412 and the second element (D2) 413 included in the latch circuit 400 at least at the supply voltage Even after that, it can be maintained. Therefore, the logic state of the latch circuit 400 can be continuously stored even after the supply of the power supply voltage is stopped.

The gate capacitance of the third transistor 421 is electrically connected to the input of the first element (D1) 412. Therefore, after the power supply voltage is restarted to be supplied to at least the first device (D1) 412 of the latch circuit 400, the potential of the output signal (OUT) Is determined by the charge accumulated in the teeth. That is, data recorded in the gate capacitance value of the third transistor 421 can be read (data read).

According to this embodiment, as the semiconductor material in the channel forming region, a transistor using an intrinsic (i-type) or substantially intrinsic (i-type) oxide semiconductor having a hydrogen concentration sufficiently high so as to have a high purity and a sufficiently low carrier concentration A capacitive element which is used as a switching element and is electrically connected to the source electrode or the drain electrode of the transistor is provided; Therefore, a non-volatile latch circuit that operates over a wide temperature range and operates stably even at high temperatures and does not erase the stored logic state even when the power supply is turned off, or a latch circuit with sufficiently long refresh time and data retention It is possible to implement. Further, since the electric charge accumulated in the capacitive element is held as data, the data can be easily read with less variation compared with the case where data is stored by the residual polarization.

Various types of logic circuits may be provided by using the non-volatile latch circuit. For example, the power consumption of the logic circuit using the non-volatile latch circuit can be reduced by turning off the power of unused blocks. Also, since the logic state is stored even when the power supply is turned off, the system can be started when the power is turned on at high speed and low power, or can be terminated when the power supply is turned off.

This embodiment can be freely combined with other embodiments.

(Example 5)

In this embodiment, an example of the configuration of the non-volatile latch circuit which is one embodiment of the disclosed invention, which is different from that of Figs. 11A and 11B, will be described with reference to Fig. Fig. 15 shows the configuration of the non-volatile latch circuit 400. Fig.

The configuration in Fig. 15 is the same as that in Figs. 11A and 11B except that a capacitor element (the capacitor element 404 in Fig. 11A) connected to the node S is not provided.

Fig. 15 shows an example of the configuration of the latch circuit 400 in Fig. 14, wherein a first inverter is used as the first element 412 and a second inverter is used as the second element 413 . The first transistor 431 and the second transistor 432 may have a structure similar to that shown in the first embodiment. That is, as the first transistor 431 and the second transistor 432, it is possible to use a transistor having an oxide semiconductor layer for a channel forming region and having normally off characteristics and a significantly low off-state current It is possible.

The non-volatile latch circuit 400 shown in FIG. 15 is configured such that the output of the first element (first inverter) 412 is electrically connected to the input of the second element (second inverter) And the output of the second element (second inverter) 413 is electrically connected to the input of the first element (first inverter) 412 through the second transistor 432 .

The input of the first element (first inverter) 412 is electrically connected to the wiring 414 to which an input signal is applied through the first transistor 431. The output of the first element (first inverter) 412 is electrically connected to the wiring 415 to which an output signal is applied. The wiring 414 to which an input signal is applied is a wiring which receives a signal input from the circuit of the previous stage to the non-volatile latch circuit 400. The wiring 415 to which the output signal is applied is a wiring which receives a signal output from the non-volatile latch circuit 400 to the next stage circuit.

In the non-volatile latch circuit 400, the first transistor 431 and the second transistor 432, each of which uses an oxide semiconductor as a semiconductor material of the channel forming region, are used as switching elements. The first element (first inverter) 412 included in the non-volatile latch circuit 400 includes at least the third transistor 421. The gate of the third transistor 421 is electrically connected to the input of the first element (first inverter) 412. That is, the gate of the third transistor 421 is electrically connected to one of the source electrode and the drain electrode of the second transistor 432. Furthermore, the gate of the third transistor 421 is electrically connected to one of the source electrode and the drain electrode of the first transistor 431. The other of the source electrode and the drain electrode of the first transistor 431 is electrically connected to the wiring 414 to which an input signal is applied. The other of the source electrode and the drain electrode of the second transistor 432 is electrically connected to the output of the second element (second inverter) 413. A node connected to the input of the first element (first inverter) 412 is referred to as a node S.

The first transistor 431 and the second transistor 432 may have the structure shown in FIG. 2A or 2B instead of the structure shown in FIG.

The data write, retain and read operations of the non-volatile latch circuit 400 are the same as those of the latch circuit 400 shown in Figs. 11A and 11B (Figs. 12, 13A and 13B and the description thereof) similar.

According to this embodiment, as the semiconductor material in the channel forming region, a transistor using an intrinsic (i-type) or substantially intrinsic (i-type) oxide semiconductor having a hydrogen concentration sufficiently high so as to have a high purity and a sufficiently low carrier concentration A capacitive element which is used as a switching element and is electrically connected to the source electrode or the drain electrode of the transistor is provided; Therefore, a non-volatile latch circuit that operates over a wide temperature range and operates stably even at high temperatures and does not erase the stored logic state even when the power supply is turned off, or a latch circuit with sufficiently long refresh time and data retention It is possible to implement. Further, since the electric charge accumulated in the capacitive element is held as data, the data can be easily read with less variation compared with the case where data is stored by the residual polarization.

Various types of logic circuits may be provided by using the non-volatile latch circuit. For example, the power consumption of the logic circuit using the non-volatile latch circuit can be reduced by turning off the power of unused blocks. Also, since the logic state is stored even when the power supply is turned off, the system can be started when the power is turned on at high speed and low power, or can be terminated when the power supply is turned off.

This embodiment can be freely combined with other embodiments.

(Example 6)

In this embodiment, the configuration of the logic state including a plurality of the non-volatile latch circuits each of which is an embodiment of the present invention disclosed will be described with reference to FIGS. 16A to 16C.

16A shows a configuration of a logic circuit including two non-volatile latch circuits 400. In Fig. This logic circuit is called D-FF and is used, for example, as a register in a CPU or various logic circuits. 16B shows a configuration of a part of the non-volatile latch circuit 400. FIG.

16A shows an example of the configuration of the latch circuit 400 in FIG. 1, wherein NAND is used as the first element and a clocked inverter is used as the second element.

That is, the latch circuit 400 is configured such that the output of the first element (NAND) 412 is electrically connected to the input of the second element (clocked inverter) 413 and the output of the second element And the output of the second transistor 413 is electrically connected to the input of the first element (NAND) 412 through the second transistor 432.

One of the inputs of the first device (NAND) 412 is electrically connected to the wiring 414 to which the input signal is applied through the first transistor 431. The output of the first element (NAND) 412 is electrically connected to the wiring 415 to which the output signal is applied. The other input of the first element (NAND) 412 is electrically connected to the wiring to which the signal RSTB is applied. A clock signal and an inverted clock signal are applied to the second element (clocked inverter) 413. The first transistor 431 and the second transistor 432 may have a structure similar to that shown in the first embodiment. That is, as the first transistor 431 and the second transistor 432, using a transistor having an oxide semiconductor layer for a channel forming region and having normally off characteristics and a significantly low off-state current It is possible.

In the non-volatile latch circuit 400, the first transistor 431 and the second transistor 432 are used as switching elements. The non-volatile latch circuit 400 includes the capacitive element 404 electrically connected to the source electrode or the drain electrode of the first transistor 431 and the second transistor 432. That is, one electrode of the capacitive element 404 is electrically connected to one of the source electrode and the drain electrode of the first transistor 431, and one electrode of the capacitive element 404 is electrically connected to the second transistor 432 and the drain electrode. The other of the source electrode and the drain electrode of the first transistor 431 is electrically connected to the wiring to which the input signal is applied. The other of the source electrode and the drain electrode of the second transistor 432 is electrically connected to the output of the second element. The potential V _C is applied to the other electrode of the capacitor device 404.

In the above configuration, the first element (NAND) 412 included in the non-volatile latch circuit 400 includes at least the third transistor 421 as shown in FIG. 16B. The gate of the third transistor 421 is electrically connected to the input of the first element (NAND) 412. That is, the gate of the third transistor 421 is electrically connected to one of the source electrode and the drain electrode of the second transistor 432. Furthermore, the gate of the third transistor 421 is electrically connected to one of the source electrode and the drain electrode of the first transistor 431.

The first transistor 431 and the second transistor 432 may have the structure shown in FIGS. 2A and 2B instead of the structure shown in FIG. 16A.

As described above, in the non-volatile latch circuit 400, the capacitance values of the capacitive element 404 and the third transistor 421 are electrically connected to predetermined positions in the loop structure. Specifically, one electrode of the capacitive element 404 and the gate of the third transistor 421 are electrically connected to the input of the first element (NAND) 412. In this manner, the capacitance value of the capacitive element 404 and the third transistor 421 is electrically connected to predetermined positions in the loop structure of the non-volatile latch circuit 400. Therefore, all the time data is written to the latch circuit, and the electric charge corresponding to the data is accumulated in the capacitance value of the capacitance element 404 and the gate capacitance value of the third transistor 421. In other words, the data of the latch circuit 400 is automatically written to the non-volatile latch (data writing). Data rewriting can similarly be performed.

The data stored in the gate capacitance values of the capacitive element 404 and the third transistor 421, that is, the charges accumulated in the capacitive element 404 and the gate capacitance value of the third transistor 421, (Data retention) by applying a potential to the gate of the first transistor 431 and the gate of the second transistor 432 so that the second transistor 431 and the second transistor 432 are turned off.

Here, the transistors used as the first transistor 431 and the second transistor 432 use an oxide semiconductor layer for a channel forming region and have normally off characteristics and a very low off-state current. Therefore, the charge accumulated in the capacitive element is supplied to the first element (NAND) 412 and the second element (clocked inverter) 413 at least included in the latch circuit 400, Even after it has been established. Therefore, the logic state of the latch circuit 400 can be continuously stored even after the supply of the power supply voltage is stopped.

A gate capacitance value of the capacitance element 404 and the third transistor 421 is electrically connected to the input of the first element (NAND) 412. Therefore, after the power supply voltage is at least restarted to be supplied to the first element (NAND) 412 of the latch circuit 400, the potential of the output signal OUT becomes higher than the potential of the capacitive element 404 and the third Is determined by the charge accumulated in the gate capacitance value of the transistor 421. [ That is, the data recorded in the gate capacitance value of the capacitor device 404 and the third transistor 421 can be read (data read).

The logic circuit shown in FIG. 16A includes the two non-volatile latch circuits 400 described above. The non-volatile latch circuit 400 is electrically connected to the wiring 414 to which the potential of the input signal is applied from the circuit of the previous stage. The wiring 417 to which the potential of the output signal of the non-volatile latch circuit 400 is applied is electrically connected to the wiring 416 to which the potential of the input signal of the non-volatile latch circuit 400 is applied. The non-volatile latch circuit 400 is electrically connected to the wiring 415 to which the potential of the output signal is applied to a circuit of a subsequent stage.

16A shows an example in which the data of the latch circuit 400 is held at the gate capacitance value of the capacitance element 404 and the third transistor 421. It is to be noted that only the gate capacitance of the third transistor 421 The capacitance can be used without using another capacitive element (the capacitive element 404). In this case, the capacitive element 404 is not necessarily provided to the latch circuit 400.

In the latch circuit 400 shown in Fig. 16A, the second element (clocked inverter) 413 may have the configuration shown in Fig. 16C. The second element (clocked inverter) 413 in FIG. 16C includes a transistor 442 and a transistor 443 electrically connected to the input and the output of the second element (clocked inverter) 413, A transistor 441 electrically connected to the high level supply voltage VDD and a transistor 444 electrically connected to the low level power supply voltage VSS. Each of the transistor 441 and the transistor 444 functions as a switch for controlling supply and stop of the power supply voltage. The clock signal? And the inverted clock signal? B are applied to the gate of the transistor 441 and the gate of the transistor 444, respectively.

Here, as the transistor 441 and the transistor 444 included in the second element (clocked inverter) 413 in FIG. 16C, an oxide semiconductor layer for a channel forming region is used and a normally- It is possible to use transistors with characteristics and a significantly low off-state current. Therefore, the transistor using the oxide semiconductor as the semiconductor material in the channel forming region functions as a switch for controlling supply and stop of the power supply voltage of the second element (clocked inverter) 413, The current path through the latch circuit 400 may be cut off. When the configuration of Fig. 16C is used, the second transistor 432 in the latch circuit is not necessarily provided. That is, when the configuration of FIG. 16C is used, the second transistor 432 is not necessarily provided in the latch circuit 400.

According to this embodiment, as the semiconductor material in the channel forming region, a transistor using an intrinsic (i-type) or substantially intrinsic (i-type) oxide semiconductor having a hydrogen concentration sufficiently high so as to have a high purity and a sufficiently low carrier concentration A capacitive element which is used as a switching element and is electrically connected to the source electrode or the drain electrode of the transistor is provided; Therefore, a non-volatile latch circuit that operates over a wide temperature range and operates stably even at high temperatures and does not erase the stored logic state even when the power supply is turned off, or a latch circuit with sufficiently long refresh time and data retention It is possible to implement. Further, since the electric charge accumulated in the capacitive element is held as data, the data can be easily read with less variation compared with the case where data is stored by the residual polarization.

Various types of logic circuits may be provided by using the non-volatile latch circuit. For example, the power consumption of the logic circuit using the non-volatile latch circuit can be reduced by turning off the power of unused blocks. Also, since the logic state is stored even when the power supply is turned off, the system can be started when the power is turned on at high speed and low power, or can be terminated when the power supply is turned off.

This embodiment can be freely combined with other embodiments.

(Example 7)

Next, another example of a method for fabricating a transistor using an oxide semiconductor that can be used as the transistor 402 in the above embodiments (such as Embodiment 1 or Embodiment 2) will be described with reference to FIGS. 17A to 17E Will be explained. In this embodiment, a description is made in detail of the case of using an oxide semiconductor (particularly, having an amorphous structure) which is highly purified. Although a top-gate type transistor is used as an example in the following description, the structure of the transistor is not limited thereto.

First, an insulating layer 202 is formed on the lower substrate 200. Thereafter, an oxide semiconductor layer 206 is formed on the insulating layer 202 (see Fig. 17A).

Here, the lower layer substrate 200 corresponds to the substrate including the transistor 421 in the lower portion, as shown in the above embodiments. The embodiments may be referred to for details of the lower layer substrate 200. Note that the surface of the lower layer substrate 200 is preferably as flat as possible. In order to achieve this, the surface should have a peak-to-valley height of less than 5 nm, preferably less than 1 nm, or a root-mean-square of less than 2 nm, preferably less than 0.4 nm a chemical mechanical polishing (CMP) method or the like so as to have a roughness (RMS).

The insulating layer 202 acts as a ground and may be formed in a manner similar to that for forming the gate insulating layer 138, the protective insulating layer 144, and the like shown in the embodiments. The embodiments may be referred to for details of the insulating layer 202. Note that it is preferable to form the insulating layer 202 to contain as little hydrogen or water as possible.

The oxide semiconductor layer 206 may be an In-Sn-Ga-Zn-O-based oxide semiconductor which is a quaternary metal oxide; In-Zn-O-based oxide semiconductor, In-Al-Zn-O-based oxide semiconductor, Sn-Ga-Zn-O-based oxide semiconductor An oxide semiconductor, an Al-Ga-Zn-O-based oxide semiconductor, or an Sn-Al-Zn-O-based oxide semiconductor layer; Zn-O-based oxide semiconductor, Sn-Zn-O-based oxide semiconductor, Al-Zn-O-based oxide semiconductor, Zn-Mg-O-based oxide semiconductor, Sn-Mg-O - based oxide semiconductor, or an In-Mg-O-based oxide semiconductor; Or an In-O-based oxide semiconductor, an Sn-O-based oxide semiconductor, or a Zn-O-based oxide semiconductor.

In particular, the In-Ga-Zn-O-based oxide semiconductor material has a sufficiently high resistance in the absence of an electric field, and therefore a sufficiently low off-state current can be obtained. Further, since the In-Ga-Zn-O-based oxide semiconductor material has a high electric field mobility, it is suitable for a semiconductor device.

A typical example of the In-Ga-Zn-O-based oxide semiconductor material is represented by InGaO ₃ (ZnO) _m (m> 0, where m is not a natural number). Another example of the oxide semiconductor material is represented by InMO ₃ (ZnO) _m (m> 0, m is not a natural number), where M is used instead of Ga. Here, M represents at least one of metal elements selected from gallium (Ga), aluminum (Al), iron (Fe), nickel (Ni), manganese (Mn), cobalt (Co) For example, M may be Ga, Ga and Al, Ga and Fe, Ga and Ni, Ga and Mn, or Ga and Co, and the like. Note that the above-described composition is only an example obtained from the crystal structure.

In this embodiment, the oxide semiconductor layer 206 having an amorphous structure is formed by a sputtering method using an In-Ga-Zn-O-based metal oxide target.

A target having a composition ratio of, for example, In ₂ O ₃ : Ga ₂ O ₃ : ZnO = 1: 1: 1 [molar ratio] may be used as the target used for forming the oxide semiconductor layer with the sputtering method have. Furthermore, a target having a composition ratio of In ₂ O ₃ : Ga ₂ O ₃ : ZnO = 1: 1: 2 [molar ratio] or a target having a molar ratio of In ₂ O ₃ : Ga ₂ O ₃ : ZnO = 1: May also be used.

The relative density of the oxide semiconductor in the metal oxide target is 80% or more, preferably 95% or more, and more preferably 99.9% or more. The use of the metal oxide target with a high relative density makes it possible to form the oxide semiconductor layer 206 having a dense structure.

The atmosphere in which the oxide semiconductor layer 206 is formed is preferably a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere containing rare gas (typically argon) and oxygen. Specifically, for example, a concentration of impurities such as hydrogen, water, a hydroxyl group, or a hydride is in the range of several ppm or less (for example, 1 ppm or less), preferably several ppb or less (for example, 1 ppb or less) It is preferable to use a high-purity gas atmosphere which is removed by a high-purity gas atmosphere.

When forming the oxide semiconductor layer, for example, the substrate is held in a treatment chamber maintained under a reduced pressure, and the substrate is heated to a temperature of 100 ° C to 550 ° C, preferably 200 ° C to 400 ° C . Thereafter, hydrogen and water-removed sputtering gas are introduced into the processing chamber during the moisture removal in the processing chamber, whereby the oxide semiconductor layer 206 is formed using the above-mentioned target. The oxide semiconductor layer 206 is formed while the substrate is heated, so that impurities contained in the oxide semiconductor layer 206 can be reduced. In addition, damage to the semiconductor layer due to sputtering can be reduced. An adsorption vacuum pump is preferably used to remove moisture in the treatment chamber. For example, a cryo pump, an ion pump, or a titanium sublimation pump may be used. Turbo pumps with cold traps can also be used. The concentration of impurities in the oxide semiconductor layer 206 can be reduced because hydrogen, water, and the like are removed from the treatment chamber that is exhausted with the cryopump.

The oxide semiconductor layer 206 may be formed, for example, under the following conditions: the distance between the substrate and the target is 170 mm; The pressure is 0.4 Pa; The direct current (DC) power is 0.5 kW; The atmosphere is a mixed atmosphere comprising oxygen (100% oxygen), argon (100% argon), or oxygen and argon. Note that it is desirable to use a pulsed direct current (DC) power source because the dust (such as powder materials formed during film formation) can be reduced and the thickness distribution can be reduced. The thickness of the oxide semiconductor layer 206 is 2 nm or more and 200 nm or less, preferably 5 nm or more and 30 nm or less. The appropriate thickness of the oxide semiconductor layer is different depending on the oxide semiconductor material to be used, the intended purpose of the semiconductor device, and the like; Therefore, the thickness can be determined according to the material to be used, the intended purpose, and the like.

Before the oxide semiconductor layer 206 is formed with the sputtering method, reverse sputtering is preferably performed, which is performed with argon gas into which plasma is introduced. Thus, the materials attached to the surface of the insulating layer 202 are removed . Here, the inverse sputtering is a method in which ions collide with a surface to be processed such that the surface is changed, as opposed to the usual sputtering in which ions collide with a sputtering target. One example of a method for causing ions to collide with a surface to be treated is how a high-frequency voltage is applied under an argon atmosphere and a plasma is generated near the substrate. Note that the atmosphere of nitrogen, helium, oxygen and the like can be used instead of the argon atmosphere.

Next, the oxide semiconductor layer 206 is processed in the same manner as etching using a mask, whereby an island-shaped oxide semiconductor layer 206a is formed.

Dry etching or wet etching may be used to etch the oxide semiconductor layer 206. It goes without saying that dry etching and wet etching can be used in combination. The etching conditions (for example, etching gas or etchant, etching time, and temperature) are appropriately set depending on the material so that the oxide semiconductor layer can be etched into a desired shape. The embodiments may be referred to for details of the etch conditions. The oxide semiconductor layer 206 may be etched in a manner similar to that for forming the oxide semiconductor layer in the embodiments. The embodiments can be referred to for details of the etch.

Then, heat treatment (first heat treatment) is preferably performed on the oxide semiconductor layer 206a. Excess hydrogen (including hydrogen and hydroxyl groups) in the oxide semiconductor layer 206a may be removed through the first heat treatment, the structure of the oxide semiconductor layer 206a may be arranged, Defects in layer 206a can be reduced. The first heat treatment is performed at a temperature of, for example, 300 ° C or higher and 550 ° C or lower, or 400 ° C or higher and 550 ° C or lower.

The heat treatment may be performed in such a manner that the lower layer substrate 200 is introduced into an electric furnace using a resistance heating element or the like, and then heated under a nitrogen atmosphere at 450 DEG C for 1 hour. The oxide semiconductor layer 206a is not exposed to the atmosphere during the heat treatment so that entry of water or hydrogen can be prevented.

The heat treatment apparatus is not limited to the electric furnace, and it is also possible to use an apparatus for heating the article to be treated by using heat conduction or thermal radiation generated from a medium such as heated gas. For example, a high speed thermal annealing (RTA) device such as a gas high speed thermal annealing (GRTA) device or a lamp high speed thermal annealing (LRTA) device may be used. The LRTA device is an apparatus for heating a material to be processed by radiation (electromagnetic waves) of light emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. The GRTA apparatus is a device for performing heat treatment using high-temperature gas. As the gas, an inert gas which does not react with the object to be treated by heat treatment, for example, a rare gas such as nitrogen or argon is used.

For example, as the first heat treatment, the GRTA treatment can be performed as follows. The substrate is placed in an inert gas atmosphere, heated for several minutes, and then taken out of the inert gas atmosphere. The GRTA treatment enables high-temperature heat treatment for a short time. In addition, the GRTA treatment can be used even when the upper temperature limit of the substrate is exceeded because it is a thermal treatment for a short time.

Note that the inert gas may be changed to a gas containing oxygen during the process. This is because defects caused by oxygen depletions can be reduced by performing the first heat treatment in an atmosphere containing oxygen.

For example, when an electric furnace is used in the first heat treatment, the atmosphere can be changed when the heat treatment temperature falls. (At a constant temperature) of an inert gas such as, for example, rare gas (e.g., helium, neon, or argon) or nitrogen, and the gas is changed to an atmosphere containing oxygen . As the atmosphere containing oxygen, an oxygen gas or a mixed gas of oxygen gas and nitrogen gas may be used.

Note that as the inert gas atmosphere, it is preferable to use an atmosphere containing nitrogen or a rare gas (for example, helium, neon, or argon) as its main component and not containing water, hydrogen or the like. For example, the purity of nitrogen or a rare gas such as helium, neon, or argon introduced into the heat treatment apparatus is not less than 6N (99.9999%), preferably not less than 7N (99.99999% , Preferably not more than 0.1 ppm).

In any case, when the impurity is reduced through the first heat treatment to form the i-type or substantially i-type oxide semiconductor layer 206a, a transistor having excellent characteristics can be realized.

Note that the first heat treatment may also be performed on the oxide semiconductor layer 206 that has not yet been treated with the island-shaped oxide semiconductor layer 206a. In this case, after the first heat treatment, the lower layer substrate 200 is taken out of the heating apparatus and a photolithography step is performed.

The first heat treatment, which has an effect of removing hydrogen or water, may also be called a dehydration treatment, a dehydrogenation treatment or the like. The dehydration treatment or dehydrogenation treatment may be performed, for example, after the oxide semiconductor layer is formed, or after the source or drain electrode is deposited on the oxide semiconductor layer 206a. Such a dehydration treatment or dehydrogenation treatment may be performed once or plural times.

Next, the conductive layer may be formed in contact with the oxide semiconductor layer 206a. Thereafter, the source or drain electrode 208a and the source or drain electrode 208b are formed by selectively etching the conductive layer (see FIG. 17B). This step is similar to the above step for forming the source or drain electrode 142a, etc. described in the above embodiments. The embodiments may be referenced for details of the step.

Next, a gate insulating layer 212 is formed in contact with a part of the oxide semiconductor layer 206a (see FIG. 17C). The description of the gate insulating layer in the above embodiments can be referred to for details of the gate insulating layer 212. [

After the gate insulating layer 212 is formed, the second heat treatment is preferably performed in an inert gas atmosphere or an oxygen atmosphere. The heat treatment is performed at a temperature of 200 ° C or more and 450 ° C or less, preferably 250 ° C or more and 350 ° C or less. For example, the heat treatment may be performed at 250 占 폚 for 1 hour in a nitrogen atmosphere. The second thermal processing may reduce variations in the electrical characteristics of the transistor. When the gate insulating layer 212 contains oxygen, oxygen is supplied to the oxide semiconductor layer 206a in order to reduce oxygen depletion of the oxide semiconductor layer 206a, whereby i-type (intrinsic) or substantially An i-type oxide semiconductor layer may be formed.

Note that the second heat treatment is performed immediately after the gate insulating layer 212 is formed in this embodiment, but the timing of the second heat treatment is not limited thereto.

Next, a gate electrode 214 is formed on the gate insulating layer 212 in a region overlapping with the oxide semiconductor layer 206a (see FIG. 17D). The gate electrode 214 may be formed by forming a conductive layer on the gate insulating layer 212, and then selectively patterning the conductive layer. A description of the gate electrode in the above embodiments may be referred to for details of the gate electrode 214. [

Next, an interlayer insulating layer 216 and an interlayer insulating layer 218 are formed on the gate insulating layer 212 and the gate electrode 214 (see FIG. 17E). The interlayer insulating layer 216 and the interlayer insulating layer 218 may be formed using a PVD method, a CVD method, or the like. The interlayer insulating layer 216 and the interlayer insulating layer 218 may be formed using a material including an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, or tantalum oxide . Note that the lamination structure of the interlayer insulating layer 216 and the interlayer insulating layer 218 is used in this embodiment, but the embodiment of the present invention disclosed herein is not limited thereto. A laminate structure including a single layer structure or three or more layers may also be used.

Note that the interlayer insulating layer 218 is preferably formed to have a planarized surface. This is because electrodes, wiring, and the like can be formed well on the interlayer insulating layer 218 when the interlayer insulating layer 218 is formed to have a planarized surface.

Through the above steps, the transistor 250 including the highly-purified oxide semiconductor layer 206a is completed.

The transistor 250 shown in FIG. 17E includes the oxide semiconductor layer 206a provided on the lower substrate 200 with the insulating layer 202 interposed therebetween; The source or drain electrode 208a and the source or drain electrode 208b electrically connected to the oxide semiconductor layer 206a; The gate insulating layer 212 covering the oxide semiconductor layer 206a, the source or drain electrode 208a, and the source or drain electrode 208b; The gate electrode 214 on the gate insulating layer 212; The interlayer insulating layer 216 on the gate insulating layer 212 and the gate electrode 214; And the interlayer insulating layer 218 on the interlayer insulating layer 216.

In the transistor 250 shown in this embodiment, the oxide semiconductor layer 206a is highly purified. Therefore, the concentration of hydrogen in the oxide semiconductor layer 206a is 5 × 10 ¹⁹ / cm 3 or less, preferably 5 × 10 ¹⁸ / cm 3 or less, more preferably 5 × 10 ¹⁷ / cm 3 or less, and still more preferably Lt; ¹⁶ &gt; / cm &lt; 3 &gt; or less. The carrier density of the oxide semiconductor layer 206a is sufficiently low (for example, less than 1 x 10 ¹² / cm 3, more preferably, 1 x 10 ¹⁴ / cm 3) × 10 ¹¹ / cm 3). As a result of this, a sufficiently low off-state current can be obtained. For example, when the drain voltage V _D is +1 V or +10 V and the gate voltage V _G is in the range of -5 V to -20 V, the off-state current is 1 × 10 ^-13 A or less at room temperature to be. In addition, the transistors described above have characteristics of a normally-off transistor. Therefore, the off-state current obtained when the voltage between the gate electrode and the source electrode is approximately 0 V, that is, the leakage current is much smaller than that of the transistor using silicon. For example, the leakage current per unit channel width at room temperature is 10 aA / 占 퐉 or less.

In this way, by using the high purity intrinsic oxide semiconductor layer 206a, the off-state current of the transistor can be sufficiently reduced.

Note that in this embodiment, the transistor 250 is used as the transistor 402 shown in the above embodiments, but the invention disclosed herein should not be construed as limiting the case. For example, when the electrical characteristics of the oxide semiconductor are sufficiently increased, the oxide semiconductor may be used for all of the transistors including the transistors included in the integrated circuit. In this case, it is not necessary to use a lamination structure as shown in the above embodiments, and the semiconductor device can be formed using, for example, a substrate such as a glass substrate.

The structures, methods, and the like described in this embodiment may be appropriately combined with any of the structures, methods, and the like described in the other embodiments.

(Example 8)

Next, another example of a method of manufacturing a transistor using an oxide semiconductor that can be used as the transistor 402 in the above embodiments (Embodiment 1 or Embodiment 2) will be described with reference to Figs. 18A to 18E. In this embodiment, as the oxide semiconductor layer, when a first oxide semiconductor layer having a crystallized region and a second oxide semiconductor layer obtained by crystal growth from the crystallized region of the first oxide semiconductor layer are used Is explained in detail. Although a top-gate transistor is used as an example in the following description, the structure of the transistor is not limited thereto.

First, an insulating layer 302 is formed on the lower substrate 300. Next, a first oxide semiconductor layer is formed on the insulating layer 302, and then the first heat treatment is performed to crystallize at least a region including the surface of the first oxide semiconductor layer, (See Fig. 18A).

Here, the lower layer substrate 300 corresponds to the substrate including the transistor 421 on a lower portion shown in the above embodiments. The embodiments may be referred to for details of the lower substrate 300. Note that the flatness of the surface of the lower substrate 300 is particularly important in this embodiment because it is not necessary for constant crystal growth. In order to obtain an oxide semiconductor having a desired crystallinity, the surface of the lower substrate 300 has a peak-to-valley height of 1 nm or less, preferably 0.2 nm or less, or 0.5 nm or less, preferably 0.1 mean square root-mean-square (RMS) root-mean-square roughness (RMS).

The insulating layer 302 acts as a ground and may be formed in a manner similar to that of the insulating layer 168, the protective insulating layer 144, and the like shown in the embodiments. The embodiments may be referred to for details of the insulating layer 302. Note that it is preferable to form the insulating layer 302 so as to contain as little hydrogen or water as possible.

The first oxide semiconductor layer 304 may be formed in a manner similar to that of the oxide semiconductor layer 206 shown in the embodiment. This embodiment can be referred to for details of the first oxide semiconductor layer 304 and the manufacturing method thereof. In this embodiment, the first oxide semiconductor layer 304 is intentionally crystallized through the first thermal processing, and therefore, the first oxide semiconductor layer 304 is preferably made of a metal oxide target . &Lt; / RTI &gt; For example, ZnO can be used. In addition, it is preferable to use an In-Ga-Zn-O-based oxide having a Zn content of 60% or more from metallic elements (In, Ga, Zn) O-based oxide is easily crystallized. The thickness of the first oxide semiconductor layer 304 is preferably 3 nm or more and 15 nm or less, and in this embodiment, for example, 5 nm. It should be noted that the appropriate thickness of the oxide semiconductor layer 304 depends on the oxide semiconductor material to be used, the intended purpose of the semiconductor device, and the like, and therefore, the thickness can be determined according to the material, the intended object and the like.

The first heat treatment is performed at a temperature of 450 ° C or more and 850 ° C or less, preferably 550 ° C or more and 750 ° C or less. The time of the first heat treatment is preferably 1 minute to 24 hours. The temperature and the time vary depending on the type or the composition ratio of the oxide semiconductor. Also, the first heat treatment is preferably performed under an atmosphere that does not contain hydrogen or water, such as nitrogen, oxygen, or rare gas (e.g., helium, neon, or argon) from which water has been sufficiently removed.

As the heat treatment apparatus, an apparatus for heating the object to be treated by using heat conduction or thermal radiation generated from a medium such as a heated gas, not limited to the electric furnace, may be used. For example, a high speed thermal annealing (RTA) device such as a gas high speed thermal annealing (GRTA) device or a lamp high speed thermal annealing (LRTA) device may be used. The LRTA device is used to heat a workpiece by radiation (electromagnetic waves) of light emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, Device. The GRTA apparatus is a device for performing heat treatment using high-temperature gas. As the gas, an inert gas which does not react with the object to be treated by heat treatment, for example, a rare gas such as nitrogen or argon is used.

Through the above-described first heat treatment, a region including at least the surface of the first oxide semiconductor layer is crystallized. The crystallized region is formed in such a manner that crystal growth proceeds from the surface of the first oxide semiconductor layer toward the interior of the first oxide semiconductor layer. Note that in some cases, the crystallized region includes plate-like crystals having an average thickness of 2 nm or more and 10 nm or less. In some cases, the crystallized region also includes a crystal having an ab-plane substantially parallel to the surface of the oxide semiconductor layer and a c-axis oriented in a direction substantially perpendicular to the surface of the oxide semiconductor layer. Here, "substantially parallel direction" means a direction within +/- 10 degrees of the parallel direction, and "substantially vertical direction" means direction within +/- 10 degrees of the vertical direction.

Through the first heat treatment in which the crystallized region is formed, hydrogen (including water or hydroxyl groups) in the first oxide semiconductor layer is preferably removed. It is preferable that the first heat treatment is performed at a purity of 6N (99.9999%) or more (that is, the impurity concentration is 1 ppm or less), more preferably 7N (99.99999% Oxygen, or rare gas (e.g., helium, neon, or argon), having a purity of at most 0.1 ppm. Alternatively, the first heat treatment may be carried out in super-dry air containing H ₂ O with 20 ppm or less, preferably 1 ppm or less.

Further, through the first thermal treatment in which the crystallized region is formed, oxygen is preferably supplied to the first oxide semiconductor layer. The oxygen can be supplied to the first oxide semiconductor layer, for example, by changing the atmosphere for the heat treatment to an oxygen atmosphere.

In this embodiment, the first heat treatment is as follows: hydrogen or the like is removed from the oxide semiconductor layer through heat treatment in a nitrogen atmosphere at 700 ° C for 1 hour, after which the atmosphere is oxygen, And is changed to an oxygen atmosphere so as to be supplied to the inside of the layer. Wherein the main purpose of the first heat treatment is to form the crystallized region; Therefore, it should be noted that the processing for removing hydrogen and the like and the processing for supplying oxygen can be performed separately. For example, the heat treatment for crystallization can be performed after the heat treatment for removing hydrogen and the like and the treatment for supplying oxygen.

Through the first heat treatment, the crystallized region is formed, hydrogen (including water and hydroxyl groups) is removed, and the first oxide semiconductor layer 304 to which oxygen is supplied can be obtained.

Next, a second oxide semiconductor layer 305 is formed on the first oxide semiconductor layer 304 including the crystallized region on at least its surface (see FIG. 18B).

The second oxide semiconductor layer 305 may be formed in a manner similar to that of the oxide semiconductor layer 206 shown in the above embodiments. The embodiments may be referred to for details of the second oxide semiconductor layer 305 and the manufacturing method thereof. Note that the second oxide semiconductor layer 305 is preferably formed to be thicker than that of the first oxide semiconductor layer 304. In addition, the second oxide semiconductor layer 305 is preferably formed such that the total thickness of the first oxide semiconductor layer 304 and the second oxide semiconductor layer 305 is not less than 3 nm and not more than 50 nm. The appropriate thickness of the oxide semiconductor layer depends on the oxide semiconductor material to be used, the intended purpose of the semiconductor device, and the like; Therefore, it should be noted that the thickness may be determined according to the material, the intended purpose, and the like.

The second oxide semiconductor layer 305 and the first oxide semiconductor layer 304 preferably have the same main component and use materials (lattice mismatch less than 1%) close to the lattice constants after crystallization . This is because, in the crystallization of the second oxide semiconductor layer 305, crystal growth easily proceeds from the crystallized region of the first oxide semiconductor layer 304 when materials having the same main component are used. In addition, the use of materials having the same main component realizes good interfacial physical properties or electrical properties.

Note that, when a desired film quality is obtained through crystallization, the second oxide semiconductor layer 305 may be formed using a material having a main component different from that of the material of the first oxide semiconductor layer 304 .

Next, a second thermal treatment is performed on the second oxide semiconductor layer 305, whereby crystal growth proceeds from the crystallized region of the first oxide semiconductor layer 304, and the second oxide semiconductor layer 306 are formed (see Fig. 18C).

The second heat treatment is performed at a temperature of 450 ° C or more and 850 ° C or less, preferably 600 ° C or more and 700 ° C or more. The time for the second heat treatment is 1 minute to 100 hours, preferably 5 hours to 20 hours, and usually 10 hours. Note that the second heat treatment is preferably performed under an atmosphere that does not contain hydrogen or water.

The details of the atmosphere and the effect of the second heat treatment are similar to those of the first heat treatment. The heat treatment apparatus that can be used is similar to that of the first heat treatment. For example, in the second heat treatment, the furnace is filled with a nitrogen atmosphere when the temperature rises, and the furnace is filled with the oxygen atmosphere when the temperature falls, whereby hydrogen or the like is removed under the nitrogen atmosphere And oxygen can be supplied under the oxygen atmosphere.

Through the above-described second heat treatment, crystal growth can proceed from the crystallized region of the first oxide semiconductor layer 304 to the entirety of the second oxide semiconductor layer 305, (306) may be formed. In addition, it is possible to form the second oxide semiconductor layer 306 in which hydrogen (including water and hydroxyl groups) and the like are removed and oxygen is supplied. Furthermore, the orientation of the crystallized region of the first oxide semiconductor layer 304 can be improved through the second heat treatment.

For example, when an In-Ga-Zn-O-based oxide semiconductor material is used for the second oxide semiconductor layer 306, the second oxide semiconductor layer 306 may be InGaO ₃ (ZnO) _m ( a crystal represented by In ₂ Ga ₂ ZnO ₇ (In: Ga: Zn: O = 2: 2: 1: 7), and the like, represented by m> 0 and m is not a natural number. These crystals are oriented through the second heat treatment such that the c-axis is in a direction substantially perpendicular to the surface of the second oxide semiconductor layer 306. [

Here, the above-described crystals can be considered to have a laminate structure of a plurality of layers including any of In, Ga, and Zn and parallel to the a-axis and the b-axis. Specifically, the above-described crystals have a structure in which a layer containing In and a layer containing no In (layer containing Ga or Zn) are stacked in the c-axis direction.

In the In-Ga-Zn-O-based oxide semiconductor crystal, a layer containing In, that is, a layer in a direction parallel to the a-axis and the b-axis has good conductivity. This is because the electrical conductivity in the In-Ga-Zn-O-based oxide semiconductor crystal is controlled mainly by In, and the 5s orbit of the In atom overlaps with the 5s orbit of the adjacent In atom to form the carrier path.

In addition, in the case where the first oxide semiconductor layer 304 includes an amorphous region at the interface with the insulating layer 302, through the second thermal treatment, crystal growth may occur in some cases, And proceeds from the crystallized region formed on the surface of the layer 304 toward the bottom of the first oxide semiconductor layer to crystallize the amorphous region. Note that in some instances, the amorphous region remains dependent on the material of the insulating layer 302, the thermal processing conditions, and the like.

In some cases, when the first oxide semiconductor layer 304 and the second oxide semiconductor layer 305 are formed using oxide semiconductor materials having the same main component, the first oxide semiconductor layer 304 and / The second oxide semiconductor layer 306 has the same crystal structure in some cases, as shown in Fig. 18C. 18C, the boundary between the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 may be a boundary between the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306. Therefore, Lt; RTI ID = 0.0 &gt; 306 &lt; / RTI &gt; can be considered as the same layer.

Next, the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 are processed in the same manner as etching using a mask, whereby the island-shaped first oxide semiconductor layer 304a and the island- -Shaped second oxide semiconductor layer 306a is formed (see Fig. 18D).

The first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 may be etched by dry etching or wet etching. It goes without saying that dry etching and wet etching can be used in combination. The etching conditions (for example, etching gas or etchant, etching time, and temperature) are appropriately set depending on the material so that the oxide semiconductor layer can be etched into a desired shape. The first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 may be etched in a manner similar to that of the oxide semiconductor layer shown in the embodiments. The embodiments can be referred to for details of the etch.

The region of the oxide semiconductor layers, which is a channel forming region, preferably has a planarized surface. For example, the surface of the second oxide semiconductor layer preferably has a high or low height of 1 nm or less (more preferably 0.2 nm or less) in a region overlapping the gate electrode (the channel forming region).

Next, a conductive layer is formed in contact with the second oxide semiconductor layer 306a. Thereafter, a source or drain electrode 308a and a source or drain electrode 308b are formed by selectively etching the conductive layer (see FIG. 18D). The source or drain electrode 308a and the source or drain electrode 308b may be formed in a manner similar to that of the source or drain electrode 142a and the source or drain electrode 142b shown in the embodiments have. The embodiments may be referred to for details of the source or drain electrode 308a and the source or drain electrode 308b.

The side surfaces of the first oxide semiconductor layer 304a and the second oxide semiconductor layer 306a which are in contact with the source or drain electrode 308a and the source or drain electrode 308b, The crystalline layers on the surface are in some cases amorphous.

Next, a gate insulating layer 312 is formed in contact with a part of the first oxide semiconductor layer 306a. The gate insulating layer 312 may be formed by a CVD method or a sputtering method. Thereafter, the gate electrode 314 is formed on the gate insulating layer 312 in a region overlapping the first oxide semiconductor layer 304a and the second oxide semiconductor layer 306a. Then, an interlayer insulating layer 316 and an interlayer insulating layer 318 are formed on the gate insulating layer 312 and the gate electrode 314 (see FIG. 18E). The gate insulating layer 312, the gate electrode 314, the interlayer insulating layer 316 and the interlayer insulating layer 318 are formed in a manner similar to the gate insulating layer and the like shown in the embodiments . The embodiments may be referred to for details of the gate insulator layer 312, the gate electrode 314, the interlayer insulator layer 316, and the interlayer insulator layer 318.

After the gate insulating layer 312 is formed, the third heat treatment is preferably performed in an inert gas atmosphere or an oxygen atmosphere. The third heat treatment is performed at a temperature of 200 ° C or more and 450 ° C or less, preferably 250 ° C or more and 350 ° C or less. For example, the heat treatment may be performed at 250 DEG C for 1 hour in an atmosphere containing oxygen. The third thermal processing may reduce variations in the electrical characteristics of the transistor. When oxygen is contained in the gate insulating layer 312, oxygen is supplied to the second oxide semiconductor layer 306a to reduce oxygen depletion of the second oxide semiconductor layer 306a, Or a substantially i-type oxide semiconductor layer may be formed.

Note that in this embodiment, the third thermal processing is performed after the gate insulating layer 312 is formed, but the timing of the third thermal processing is not limited thereto. Further, the third heat treatment may be omitted when oxygen is supplied to the second oxide semiconductor layer through another process such as the second heat treatment.

The gate electrode 314 may be formed by forming a conductive layer on the gate insulating layer 312 and then selectively patterning the conductive layer. In the above embodiments, the description of the gate electrode may be referred to for details of the gate electrode 314.

The interlayer insulating layer 316 and the interlayer insulating layer 318 may be formed by a PVD method, a CVD method, or the like. The interlayer insulating layer 316 and the interlayer insulating layer 318 may be formed using a material including an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, or tantalum oxide . Note that the lamination structure of the interlayer insulating layer 316 and the interlayer insulating layer 318 is used in this embodiment, but the embodiments of the present invention disclosed herein are not limited thereto. A laminate structure including a single layer structure or three or more layers may also be used.

Note that the interlayer insulating layer 318 is preferably formed to have a planarized surface. This is because electrodes, wiring, and the like can be formed well on the interlayer insulating layer 318 when the interlayer insulating layer 318 is formed to have a planarized surface.

Through the above steps, the transistor 350 is completed. The transistor 350 uses the first oxide semiconductor layer 304a and the second oxide semiconductor layer 306a obtained by crystal growth from the crystallized region of the first oxide semiconductor layer 304a.

The transistor 350 shown in FIG. 18E includes the first oxide semiconductor layer 304a provided on the lower substrate 300 via the insulating layer 302; The second oxide semiconductor layer 306a provided on the first oxide semiconductor layer 304a; The source or drain electrode 308a and the source or drain electrode 308b electrically connected to the second oxide semiconductor layer 306a; The gate insulating layer 312 covering the second oxide semiconductor layer 306a, the source or drain electrode 308a, and the source or drain electrode 308b; The gate electrode (314) on the gate insulating layer (312); The gate insulating layer 312 and the interlayer insulating layer 316 on the gate electrode 314; And the interlayer insulating layer 318 on the interlayer insulating layer 316. [

In the transistor 350 shown in this embodiment, the first oxide semiconductor layer 304a and the second oxide semiconductor layer 306a are highly purified. Therefore, the concentration of hydrogen in the first oxide semiconductor layer 304a and the second oxide semiconductor layer 306a is 5 × 10 ¹⁹ / cm 3 or less, preferably 5 × 10 ¹⁸ / cm 3 or less, more preferably 5 × 10 to ¹⁷ / ㎤ or less, and even more preferably less than 1 × 10 ¹⁶ / ㎤. The carrier density of the first oxide semiconductor layer 304a and the second oxide semiconductor layer 306a is sufficiently low as compared with a conventional silicon wafer (approximately 1 x 10 ¹⁴ / cm 3) (for example, 1 Less than 10 ¹² / cm 3, more preferably less than 1 10 ¹¹ / cm 3). As a result of this, a sufficiently low off-state current can be obtained. For example, when the drain voltage V _D is +1 V or +10 V and the gate voltage V _G is in the range of -5 V to -20 V, the off-state current is 1 × 10 ^-13 A or less at room temperature to be. In addition, the transistors described above have characteristics of a normally-off transistor. Therefore, the off-state current, that is, the leakage current in the state where the voltage between the gate electrode and the source electrode is approximately 0 V, is much smaller than that of the transistor using silicon. For example, the leakage current per unit channel width is 10 aA / 占 퐉 or less at room temperature.

In this way, by using the high-purity intrinsic first oxide semiconductor layer 304a and the second oxide semiconductor layer 306a, the off-state current of the transistor can be sufficiently reduced.

Furthermore, in this embodiment, the first oxide semiconductor layer 304a having a crystallized region and the second oxide semiconductor layer 304a obtained by crystal growth from the crystallized region of the first oxide semiconductor layer 304a, (306a) is used as the oxide semiconductor layer. Thus, the electric field mobility can be increased and a transistor having good electrical characteristics can be realized.

Note that, in this embodiment, the transistor 350 is used as the transistor 402 shown in the above embodiments, but the disclosed invention should not be construed as limited to the case described above. For example, the transistor 350 shown in this embodiment may be used for crystal growth from the crystallized region of the first oxide semiconductor layer 304a and the first oxide semiconductor layer 304a having a crystallized region The second oxide semiconductor layer 306a obtained by using the second oxide semiconductor layer 306a is used, and thus has a high electric field mobility. Thus, the oxide semiconductor can be used for all of the transistors including the transistors included in the integrated circuit. In this case, it is not necessary to use a lamination structure as shown in the above embodiments, and the semiconductor device can be formed using a substrate such as a glass substrate, for example.

The structures, methods, and the like described in this embodiment may be appropriately combined with any of the structures, methods, and the like described in the other embodiments.

(Example 9)

In this embodiment, examples of an electronic apparatus equipped with a semiconductor device using the nonvolatile latch circuit obtained in the above embodiments will be described with reference to Figs. 19A to 19F. The electronic apparatus equipped with the semiconductor device using the non-volatile latch circuit obtained in the above embodiments has excellent characteristics not found in the prior art. Therefore, by use of the semiconductor device including the nonvolatile latch circuit, an electronic device having a new structure can be provided. Note that the semiconductor device using the non-volatile latch circuit according to the above embodiments is integrated to be mounted on a circuit board or the like, and is then located inside each electronic device.

19A shows a laptop personal computer equipped with a semiconductor device using the non-volatile latch circuit according to the above embodiments and includes a main body 1301, a housing 1302, a display portion 1303, a keyboard 1304 and the like do. When the semiconductor device according to the disclosed invention is applied to a personal computer, a high-performance personal computer can be provided.

19B shows a portable information terminal (PDA) equipped with a semiconductor device using the non-volatile latch circuit according to the above embodiments. The main body 1311 includes a display unit 131, an external interface 1315, operation keys 1314, and the like. Also, a stylus 1312 is provided as an accessory for operating the PDA. When the semiconductor device according to the disclosed invention is applied to a PDA, a high-performance portable information terminal (PDA) have.

19C shows an electronic book reader 1320 as an example of an electronic paper with a semiconductor device using the non-volatile latch circuit according to the above embodiments. The electronic book reader 1320 includes two housings, i.e., a housing 1321 and a housing 1323. [ The housing 1321 and the housing 1323 are coupled with the shaft 1337 so that the electronic book reader 1320 can open and close with a hinge 1337 as an axis. With this structure, the electronic book reader 1320 can be used like a paper book.

The housing 1321 includes a display portion 1325 and the housing 1323 includes a display portion 1327. [ The display unit 1325 and the display unit 1327 may display a continuous image or different images. For example, the text may be displayed on the right display portion (the display portion 1325 in Fig. 19C) and the images may be displayed on the left display portion (the display portion 1327 in Fig. 19C) Can be displayed.

19C shows an example in which an operation unit or the like is provided in the housing 1321. Fig. The housing 1321 includes a power switch 1331, operation keys 1333, and a speaker 1335, for example. Pages may be handed over with the operation keys 1333. Note that a keyboard, pointing device, etc., may also be provided on the surface of the housing on which the display is provided. Furthermore, a recording medium insertion portion or the like may be provided on the back surface or the side surface of the housing, an external connection terminal (a terminal that can be connected to various cables such as an earphone terminal, a USB terminal, an AC adapter and a USB cable, etc.). In addition, the electronic book reader 1320 may also function as an electronic dictionary.

In addition, the electronic book reader 1320 may have a configuration capable of transmitting and receiving data wirelessly. Through wireless communication, desired book data and the like can be purchased and downloaded from the electronic book server.

Note that electronic paper may be applied to devices in various fields of displaying information. For example, electronic paper may be used for electronic book readers as well as for display on various cards such as posters, advertisements in vehicles such as trains, or credit cards. When the semiconductor device according to the disclosed invention is applied to an electronic paper, a high-performance electronic paper can be provided.

19D shows a portable telephone equipped with a semiconductor device using the non-volatile latch circuit according to the above embodiments. The mobile phone includes two housings, namely a housing 1340 and a housing 1341. The housing 1341 includes a display panel panel 1342, a speaker 1343, a microphone 1344, a pointing device 1346, a camera lens 1347, an external connection terminal 1348, and the like. The housing 1341 also includes a solar cell 1349 for charging the portable telephone, the external memory slot 1350, and the like. In addition, an antenna is built in the housing 1341.

The display panel 1342 has a touch panel function. In Fig. 19D, a plurality of operation keys 1345 displayed as images are indicated by dotted lines. Note that the cellular phone includes a step-up circuit for increasing the voltage output from the solar cell 1349 to the voltage required for each circuit. In addition to the above structure, a noncontact IC chip, a small recording device, and the like can be incorporated in the mobile phone.

The display orientation of the display panel 1342 is appropriately changed depending on the usage pattern. Furthermore, the camera lens 1347 is provided on the same surface as the display panel 1342 so that the mobile phone can be used as a video phone. The speaker 1343 and the microphone 1344 can be used for voice calls as well as for video phone calls, recording, and playback sound. In addition, the housing 1340 and the housing 1341, which are not folded as shown in Fig. 19D, can overlap each other by sliding. Accordingly, the portable telephone may be of a suitable size for portable use.

The external connection terminal 1348 can be connected to various cables such as an AC adapter and a USB cable, whereby the portable telephone can be charged or data communication can be performed. Also, when a recording medium is inserted into the external memory slot 1350, a large amount of data can be stored and moved. In addition to the above functions, an infrared communication function, a television receiving function, and the like may be provided. When the semiconductor device according to the disclosed invention is applied to a portable telephone, a high-performance portable telephone can be provided.

19E shows a digital camera equipped with a semiconductor device using the non-volatile latch circuit according to the above embodiments. The digital camera includes a main body 1361, a display portion (A) 1367, an eyepiece portion 1363, an operation switch 1364, a display portion (B) 1365, a battery 1366 and the like. When the semiconductor device according to the disclosed invention is applied to a digital camera, a high-performance digital camera can be provided.

19F shows a television set equipped with a semiconductor device using the non-volatile latch circuit according to the above embodiment. In the television set 1370, the housing 1371 includes a display portion 1373. Images may be displayed on the display unit 1373. [ Note that the housing 1371 is supported by the stand 1375 here.

The television set 1370 may be operated with an operation switch of the housing 1371 or a remote controller 1380 provided separately. The channels and the volume can be controlled with the operation keys 1379 of the remote controller 1380 so that the image displayed on the display unit 1373 can be controlled. Also, the remote controller 1380 may include a display unit 1377 for displaying data output from the remote controller 1380.

Note that the television set 1370 preferably comprises a receiver, modem, and the like. A typical television broadcast may be received with the receiver. In addition, when the television set is connected to the communication network either wired or wirelessly via the modem, data communication in the short-direction (from the transmitter to the receiver) or in both directions (between the transmitter and the receiver, between the receivers, etc.) . When the disclosed semiconductor device according to the disclosed invention is applied to a television set, a high-performance television set can be provided.

The structures, methods, and the like shown in this embodiment may be appropriately combined with any of the structures, methods, and the like shown in other embodiments.

This application is based on Japanese Patent Application No. 2009-288146 filed with the Japanese Patent Office on December 18, 2009, the entire contents of which are incorporated herein by reference.

100: substrate 102: protective layer
104: semiconductor region 106: element isolation insulating layer
108a: Gate insulating layer 110a: Gate electrode
112: insulating layer 114: impurity region
116: channel forming region 118: side wall insulating layer
120: high-concentration impurity region 122: metal layer
124: metal compound region 126, 128: interlayer insulating layer
130a, 130b: source or drain electrode 130c: electrode
132: insulating layer 134: conductive layer
136a, 136b, 136c: electrode 136d: gate electrode
138: gate insulating layer 140: oxide semiconductor layer
142a, 142b: source or drain electrode 144: protective insulating layer
146: interlayer insulating layer 148: conductive layer
150a, 150b, 150c, 150d, 150e: electrode 152: insulating layer
154a, 154b, 154c, 154d: electrode 200: lower layer substrate
202: insulating layer 206, 206a: oxide semiconductor layer
208a, 208b: source or drain electrode 212: gate insulating layer
214: gate electrode 216, 218: interlayer insulating layer
250: transistor 300: lower layer substrate
302: insulation layer
308a, 308b: source or drain electrode
304, 304a, 305, 306, 306a: an oxide semiconductor layer
312: gate insulating layer 314: gate electrode
316, 318: interlayer insulating layer 350: transistor
400: latch circuit 402: transistor
404: capacitive element 412, 413: first element
414, 415: wiring 421: third transistor
431: first transistor 432: second transistor
441, 442, 443, 444: Transistor 1301:
1302: Housing 1303:
1304: keyboard 1311:
1312: Stylus 1313: Display
1314: Operation button 1315: External interface
1320: electronic book reader 1321, 1323: housing
1325, 1327: display section 1331: power switch
1333: Operation key 1335: Speaker
1337: shank 1340, 1341: housing
1342: Display panel 1343: Speaker
1344: microphone 1345: operation key
1346: pointing device 1347: camera lens
1348: External connection terminal 1349: Solar cell
1350: External memory slot 1361:
1363: eyepiece portion 1364: operation switch
1365: display portion (B) 1366: battery
1367: Display section (A) 1370: Television device
1371: Housing 1373: Display
1375: Stand 1377: Display
1379: Operation key 1380: Remote controller

Claims (44)

In a non-volatile latch circuit,
A first transistor;
A second transistor;
A first element including a third transistor; And
And a second element,
Wherein an output of the first element is electrically connected to an input of the second element and an output of the second element is electrically connected to an input of the first element through the second transistor,
Wherein the input of the first element is electrically connected to a wiring to which an input signal is applied through the first transistor, the output of the first element is electrically connected to a wiring to which an output signal is applied,
Wherein one of the source electrode and the drain electrode of the first transistor is electrically connected to the gate of the third transistor and the other of the source electrode and the drain electrode of the first transistor is connected to the wiring to which the input signal is applied Electrically connected,
Wherein one of the source electrode and the drain electrode of the second transistor is electrically connected to the gate of the third transistor and the other of the source electrode and the drain electrode of the second transistor is connected to the output of the second element Electrically connected,
Wherein each channel forming region of the first transistor and the second transistor includes an oxide semiconductor layer,
An insulating layer is provided on the third transistor,
Wherein the first transistor and the second transistor are provided over the insulating layer. delete delete delete delete delete delete In a non-volatile latch circuit,
A first transistor;
A second transistor;
A first element including a third transistor;
A second element; And
And a capacitive element,
Wherein an output of the first element is electrically connected to an input of the second element and an output of the second element is electrically connected to an input of the first element through the second transistor,
Wherein the input of the first element is electrically connected to a wiring to which an input signal is applied through the first transistor, the output of the first element is electrically connected to a wiring to which an output signal is applied,
Wherein one of the source electrode and the drain electrode of the first transistor is electrically connected to the gate of the third transistor and the other of the source electrode and the drain electrode of the first transistor is connected to the wiring to which the input signal is applied Electrically connected,
Wherein one of the source electrode and the drain electrode of the second transistor is electrically connected to the gate of the third transistor and the other of the source electrode and the drain electrode of the second transistor is connected to the output of the second element Electrically connected,
Wherein each channel forming region of the first transistor and the second transistor includes an oxide semiconductor layer,
The one of the source electrode and the drain electrode of the first transistor and the one of the source electrode and the drain electrode of the second transistor are electrically connected to one electrode of the capacitor,
An insulating layer is provided on the third transistor,
Wherein the first transistor and the second transistor are provided over the insulating layer. The method according to claim 1 or 8,
Wherein the oxide semiconductor layer comprises indium, gallium, and zinc. 9. The method of claim 8,
Wherein data stored in the capacitance element and the gate capacitance value of the third transistor is held by the first transistor and the second transistor. The method according to claim 1 or 8,
Wherein the first element is a first inverter and the second element is a second inverter. The method according to claim 1 or 8,
Wherein the first element is a NAND and the second element is a clocked inverter. The method according to claim 1 or 8,
Wherein at least one of the first transistor and the second transistor includes a first gate electrode and a second gate electrode in which the oxide semiconductor layer is interposed therebetween. A semiconductor device comprising the non-volatile latch circuit according to any one of the preceding claims. A logic circuit comprising at least a first non-volatile latch circuit and a second non-volatile latch circuit,
Wherein each of said first non-volatile latch circuit and said second non-volatile latch circuit comprises:
A first transistor;
A second transistor;
A first element including a third transistor; And
And a second element,
Wherein an output of the first element is electrically connected to an input of the second element and an output of the second element is electrically connected to an input of the first element through the second transistor,
Wherein the input of the first element is electrically connected to a wiring to which an input signal is applied through the first transistor, the output of the first element is electrically connected to a wiring to which an output signal is applied,
Wherein one of the source electrode and the drain electrode of the first transistor is electrically connected to the gate of the third transistor and the other of the source electrode and the drain electrode of the first transistor is connected to the wiring to which the input signal is applied Electrically connected,
Wherein one of the source electrode and the drain electrode of the second transistor is electrically connected to the gate of the third transistor and the other of the source electrode and the drain electrode of the second transistor is connected to the output of the second element Electrically connected,
Wherein each channel forming region of the first transistor and the second transistor includes an oxide semiconductor layer,
The wiring of the second non-volatile latch circuit to which the input signal is applied is electrically connected to the wiring of the first non-volatile latch circuit to which the output signal is applied,
An insulating layer is provided on the third transistor,
Wherein the first transistor and the second transistor are provided over the insulating layer. 16. The method of claim 15,
Wherein the oxide semiconductor layer comprises indium, gallium, and zinc in each of the first non-volatile latch circuit and the second non-volatile latch circuit. 16. The method of claim 15,
Wherein the data stored in the gate capacitance value of the third transistor is held by the first transistor and the second transistor in each of the first non-volatile latch circuit and the second non-volatile latch circuit. 16. The method of claim 15,
Wherein the first element in the first non-volatile latch circuit or the second non-volatile latch circuit is a first inverter and the second element is a second inverter. 16. The method of claim 15,
Wherein the first element in the first non-volatile latch circuit or the second non-volatile latch circuit is NAND and the second element is a clocked inverter. 16. The method of claim 15,
At least one of the first transistor and the second transistor is connected to the first gate electrode and the second gate electrode in which the oxide semiconductor layer is interposed therebetween in the first non-volatile latch circuit or the second non-volatile latch circuit, &Lt; / RTI &gt; 16. The method of claim 15,
Further comprising a first capacitive element in the first non-volatile latch circuit,
The one of the source electrode and the drain electrode of the first transistor and the one of the source electrode and the drain electrode of the second transistor are electrically connected to one electrode of the first capacitor. 16. The method of claim 15,
Further comprising a second capacitive element in the second non-volatile latch circuit,
The one of the source electrode and the drain electrode of the first transistor and the one of the source electrode and the drain electrode of the second transistor are electrically connected to one electrode of the second capacitor. 16. The method of claim 15,
Further comprising a first capacitive element in the first non-volatile latch circuit and a second capacitive element in the second non-volatile latch circuit,
The one of the source electrode and the drain electrode of the first transistor and the one of the source electrode and the drain electrode of the second transistor are electrically connected to one electrode of the first capacitor,
The one of the source electrode and the drain electrode of the first transistor and the one of the source electrode and the drain electrode of the second transistor are electrically connected to one electrode of the second capacitor. A semiconductor device comprising the logic circuit according to claim 15. delete delete In the semiconductor device,
A first transistor;
A first circuit comprising a third transistor; And
A second circuit,
The output of the first circuit being electrically connected to the input of the second circuit, the output of the second circuit being electrically connected to the input of the first circuit,
The input of the first circuit is electrically connected to a wiring to which an input signal is applied through the first transistor, the output of the first circuit is electrically connected to a wiring to which an output signal is applied,
Wherein one of the source electrode and the drain electrode of the first transistor is electrically connected to the gate of the third transistor and the other of the source electrode and the drain electrode of the first transistor is connected to the wiring to which the input signal is applied Electrically connected,
An insulating layer is provided on the third transistor,
Wherein the first transistor is provided on the insulating layer,
Wherein the channel forming region of the first transistor includes an oxide semiconductor,
Wherein the channel forming region of the third transistor comprises silicon. 28. The method of claim 27,
And data stored in the gate capacitance value of the third transistor is held by the first transistor. In the semiconductor device,
A first transistor;
A first circuit comprising a third transistor;
A second circuit; And
A capacitive element,
The output of the first circuit being electrically connected to the input of the second circuit, the output of the second circuit being electrically connected to the input of the first circuit,
The input of the first circuit is electrically connected to a wiring to which an input signal is applied through the first transistor, the output of the first circuit is electrically connected to a wiring to which an output signal is applied,
Wherein one of the source electrode and the drain electrode of the first transistor is electrically connected to the gate of the third transistor and the other of the source electrode and the drain electrode of the first transistor is connected to the wiring to which the input signal is applied Electrically connected,
An insulating layer is provided on the third transistor,
Wherein the first transistor is provided on the insulating layer,
Wherein the channel forming region of the first transistor includes an oxide semiconductor,
Wherein the channel forming region of the third transistor includes silicon,
And said one of said source electrode and said drain electrode of said first transistor is electrically connected to one electrode of said capacitive element. 30. The method of claim 29,
And data stored in the capacitance element and the gate capacitance value of the third transistor are held by the first transistor. 30. The method of claim 27 or 29,
Wherein the oxide semiconductor comprises indium, gallium, and zinc. 30. The method of claim 27 or 29,
Wherein the first circuit is a first inverter and the second circuit is a second inverter. 30. The method of claim 27 or 29,
Wherein the first circuit is a NAND and the second circuit is a clocked inverter. delete 30. The method of claim 27 or 29,
Further comprising a second transistor,
One of a source electrode and a drain electrode of the second transistor is electrically connected to the gate of the third transistor,
And the other of the source electrode and the drain electrode of the second transistor is electrically connected to the output of the second circuit. In the semiconductor device,
A first circuit comprising a third transistor;
A second circuit; And
A second transistor,
The output of the first circuit being electrically connected to the input of the second circuit,
The output of the second circuit being electrically connected to the input of the first circuit through the second transistor,
Wherein the input of the first circuit is electrically connected to a wiring to which an input signal is applied,
The output of the first circuit is electrically connected to the wiring to which the output signal is applied,
One of a source electrode and a drain electrode of the second transistor is electrically connected to the output of the second circuit,
The other of the source electrode and the drain electrode of the second transistor is electrically connected to the gate electrode of the third transistor,
An insulating layer is provided on the third transistor,
The second transistor is provided on the insulating layer,
Wherein the channel forming region of the second transistor includes an oxide semiconductor,
Wherein the channel forming region of the third transistor comprises silicon. 37. The method of claim 36,
And data stored in the gate capacitance value of the third transistor is held by the second transistor. 37. The method of claim 36,
Further comprising a capacitive element,
And one electrode of the capacitive element is electrically connected to the other one of the source electrode and the drain electrode of the second transistor. In the semiconductor device,
A first transistor;
A first circuit comprising a third transistor;
A second circuit; And
A second transistor,
The output of the first circuit being electrically connected to the input of the second circuit,
The output of the second circuit being electrically connected to the input of the first circuit through the second transistor,
Wherein the input of the first circuit is electrically connected to a wiring to which an input signal is applied through the first transistor,
The output of the first circuit is electrically connected to the wiring to which the output signal is applied,
One of a source electrode and a drain electrode of the second transistor is electrically connected to the output of the second circuit,
The other of the source electrode and the drain electrode of the second transistor is electrically connected to the gate electrode of the third transistor,
Wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to the gate electrode of the third transistor,
The other of the source electrode and the drain electrode of the first transistor is electrically connected to a wiring to which an input signal is applied,
An insulating layer is provided on the third transistor,
Wherein the first transistor and the second transistor are provided on the insulating layer,
Wherein the channel forming region of each of the first transistor and the second transistor includes an oxide semiconductor,
Wherein the channel forming region of the third transistor comprises silicon. 40. The method of claim 36 or 39,
Wherein the oxide semiconductor comprises indium, gallium, and zinc. 40. The method of claim 39,
And data stored in the gate capacitance value of the third transistor is held by the first transistor and the second transistor. 40. The method of claim 36 or 39,
Wherein the first circuit is a first inverter and the second circuit is a second inverter. 40. The method of claim 36 or 39,
Wherein the first circuit is a NAND and the second circuit is a clocked inverter. 40. The method of claim 39,
Further comprising a capacitive element,
And one electrode of the capacitive element is electrically connected to the other of the source electrode and the drain electrode of the second transistor and the one of the source electrode and the drain electrode of the first transistor.

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