JP2000077982A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a resume function with simple circuit configuration without using a non-volatile memory provided in a peripheral circuit for saving data at the time of power supply cutoff by providing a non-volatile element such as a ferroelectric capacitor corresponding to the storage node of an order circuit in a processing circuit. SOLUTION: This semiconductor integrated circuit is provided with the processing circuit equipped with the order circuit and combination circuit for holding data such as a D flip-flop circuit, for example. The D flip-flop circuit is a circuit for fetching and holding data at the rising edge of a clock. Concerning the semiconductor integrated circuit, ferroelectric capacitors 9 and 8 are respectively connected to storage nodes N1 and N2 of the D flip-flop circuit. Then, power supply is cut off after the data of the storage nodes N1 and N2 are previously saved in the ferroelectric capacitors 9 and 8 before the cutoff of power supply and the data saved in the ferroelectric capacitors 9 and 8 are fed back to the storage nodes N1 and N2 when a power source is turned on again.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit. The present invention relates to a semiconductor integrated circuit capable of restoring data saved in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In information terminals such as personal computers, for example, with the advancement of functions, the startup time required after power-on until the terminal becomes usable tends to be long. In particular, in the case of information terminals intended for portable use, there is a strong demand for shortening the start-up time, and there is a high need for a resume function for restoring the state of the system saved in the semiconductor memory before power-off when power is turned on again. As a semiconductor memory for saving the state of the system, for example, EE
A nonvolatile semiconductor memory such as a PROM (electric erase programmable read only memory) or a flash memory is often used. This is because volatile semiconductor memories such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory) require a separate backup battery to supply power after the main power is turned off. That's why. In recent years, nonvolatile semiconductor memories using ferroelectric materials having hysteresis characteristics, such as PZT (lead zirconate titanate), for memory cells have also been developed. For example, JP-A-64-68699 discloses that
A nonvolatile semiconductor memory in which a volatile memory cell of an SRAM and a ferroelectric capacitor using a ferroelectric material are combined is described. Here, FIG. 8 shows a memory cell of the nonvolatile memory described in the above publication. The memory cell of the nonvolatile memory described in the above publication is, for example, a CMOS type SR.
It can be broadly divided into a volatile portion composed of an AM cell and a non-volatile portion provided with a ferroelectric capacitor. The volatile portion includes, for example, a flip flip including two p-channel transistors 101 and 102 and two n-channel transistors 103 and 104. In the non-volatile part, the flip-flop 2
Ferroelectric capacitors 107 and 10 connected to two storage nodes via transistors 111 and 112, respectively.
8 is included. In the nonvolatile memory described in the above publication, during normal operation (while power is turned on), the transistors 111 and 112 are turned off, and the flip-flop and the ferroelectric capacitor 10 are turned off.
7, 108 are separated. That is, during a normal operation, the memory cells of the nonvolatile memory are equivalent to the SRAM cells, and the bit lines 7, 8 are similar to the general SRAM.
In addition, writing and reading of information to and from the flip-flop can be performed by accessing the word line 9. When the power supply is cut off, the transistor 11
1 and 112 are turned on, the storage node of the flip-flop is connected to the ferroelectric capacitors 107 and 108, and the information of the storage node is read and stored in the ferroelectric capacitors 107 and 108. For this reason, in the nonvolatile memory described in the above publication, information is not lost even when the power is cut off. Therefore, if the above-described non-volatile memory is used, internal data held in a processing circuit including a sequential circuit and a combinational circuit, for example, a sequential circuit such as an ASIC (IC for a specific application) can be converted into hardware or software. By turning off the power before turning off the power in the non-volatile memory and turning off the power, and returning to the sequential circuit from the non-volatile memory when the power is turned on again,
Without going through a long start-up process, the user can continue the work that was done before the power was turned off when the power is turned on again.

[0003]

Incidentally, a register file or the like for storing small data of about several tens of bits, which is included in the above-mentioned processing circuit, is usually provided by a DRAM or an SD card.
In many cases, a sequential circuit such as a flip-flop circuit and a combinational circuit are used without using a RAM or the like. This means that in a DRAM or SRAM, a row decoder and a word driver for driving a word line in accordance with an input address, a sense amplifier for amplifying output data, an I / O circuit for controlling input / output data, and a control circuit for controlling these are provided. This is because a peripheral circuit is required, and if the bit capacity is small, the ratio occupied by the peripheral circuit becomes larger than the ratio occupied by the memory cells, resulting in an inefficient configuration in area. However, in the flip-flop circuit composed of CMOS transistors and the like as described above, when the power supply is cut off, the data held therein is lost. In addition to a processing circuit that holds and processes data, a non-volatile memory including the above-described SRAM and the like is required, and the area becomes inefficient. Also, it takes time to write or read data for accessing the nonvolatile memory. Further, a circuit and software for writing or reading data to or from the nonvolatile memory have been required. In order to solve the problems in the prior art, the present invention improves a semiconductor integrated circuit and provides a nonvolatile element such as a ferroelectric capacitor corresponding to a storage node of a sequential circuit of a processing circuit. It is an object of the present invention to provide a semiconductor integrated circuit capable of realizing a resume function with a simple circuit configuration by eliminating the need to use a nonvolatile memory having a peripheral circuit to save data when power is cut off. is there.

[0004]

To achieve the above object, the invention according to claim 1 includes a processing circuit including a sequential circuit and a combinational circuit, and stores data included in the sequential circuit of the processing circuit. In a semiconductor integrated circuit capable of saving the power saved in the nonvolatile element and returning the data saved in the nonvolatile element to the sequential circuit when the power is turned on again, the semiconductor integrated circuit has The semiconductor integrated circuit is provided with the above-mentioned nonvolatile element corresponding to a storage node of a sequential circuit of a processing circuit. According to a second aspect of the present invention, in the semiconductor integrated circuit according to the first aspect, the sequential circuit of the processing circuit is a flip-flop circuit or a latch circuit. According to a third aspect of the present invention, in the semiconductor integrated circuit according to the second aspect, the nonvolatile element is connected to a storage node of the flip-flop circuit. According to a fourth aspect of the present invention, in the semiconductor integrated circuit according to the third aspect, a coupling / separation element that couples or separates the nonvolatile element and the flip-flop circuit, and a short-circuit element that short-circuits the nonvolatile element. The gist is to be provided. According to a fifth aspect of the present invention, in the semiconductor integrated circuit according to the second aspect, the transistor constituting the flip-flop circuit has a gate electrode made of a ferroelectric material. . According to a sixth aspect of the present invention, in the semiconductor integrated circuit according to any one of the first to fifth aspects, the non-volatile element is included in the sequential circuit of the processing circuit in synchronization with a clock or input data. The main point is to save the data to be stored. According to the semiconductor integrated circuit of any one of claims 1 to 6, a resume function for saving data when power is cut off is provided by providing a nonvolatile element corresponding to a storage node of a sequential circuit of a processing circuit. Therefore, it is not necessary to use a non-volatile memory or the like having a peripheral circuit in order to realize the above. For this reason, the circuit configuration can be simplified, and there is no need for a dedicated circuit or software for accessing the nonvolatile memory. Further, the time for writing and reading can be reduced by the amount that it is not necessary to access the nonvolatile memory having the peripheral circuit.

[0005]

Embodiments of the present invention will be described below with reference to the accompanying drawings to provide an understanding of the present invention.
The following embodiment is a specific example of the present invention and does not limit the technical scope of the present invention. A semiconductor integrated circuit according to an embodiment of the present invention includes an ASIC including a processing circuit including a sequential circuit holding data, such as a D flip-flop circuit, and a combinational circuit.
(Application-specific IC). ASI above
The D flip-flop circuit included in C is a circuit that captures and holds data at the rising edge of a clock, for example, and its circuit configuration is shown in FIG. As shown in FIG. 1, the D flip-flop circuit includes a master half latch circuit having a data holding circuit including two inverters 2 and 3 and a slave half circuit including a data holding circuit including inverters 5 and 6. A half latch circuit. The semiconductor integrated circuit according to the present embodiment differs from the conventional semiconductor integrated circuit in that ferroelectric capacitors 9 and 8 are connected to storage nodes N1 and N2 of the D flip-flop circuit, respectively. In the semiconductor integrated circuit according to the present embodiment, the data of the storage nodes N1 and N2 are stored in advance in the ferroelectric capacitors 9 and 8 before the power is turned off.
Then, when the power is turned on, the data saved in the ferroelectric capacitors 9 and 8 is returned to the storage nodes N1 and N2. Hereinafter, the operation of the semiconductor integrated circuit will be described with reference to FIGS. Here, FIG. 2 is a diagram showing the relationship between the applied voltage and the polarization state to the ferroelectric capacitor, and FIG. 3 is a time chart for explaining the operation before the power is turned off and the operation when the power is turned on again. During normal operation, the clock signal CK is supplied to the D flip-flop circuit, and data corresponding to the input D is held in the storage nodes N1 and N2 at each rising edge of the clock signal. In the semiconductor integrated circuit, when the power is cut off, first, the clock signal CK is stopped at time t1. At this time, it is assumed that the storage node N1 is at a high level and the storage node N2 is at a low level. Next, as shown in FIG. 3, the potential of the cell plate CP is set to the high level from time t1 to time t2 after a predetermined time. At this time, since the storage node N2 is at a low level, a negative voltage is applied to the ferroelectric capacitor 8. That is, as shown in FIG.
The polarization state of the ferroelectric capacitor 8 becomes state c,
Data “0” is written in the ferroelectric capacitor 8. Next, from time t2 to time t3, the potential of the cell plate CP is set to a low level. At this time, since the storage node N1 is at a high level, a positive voltage is applied to the ferroelectric capacitor 9. That is, the polarization state of the ferroelectric capacitor 9 becomes the state a, and data “1” is written in the ferroelectric capacitor 9. Next, when the power supply VDD is cut off at the time t3, the storage nodes N1 and N2 are both at a low level and data is lost, but the polarization state of the ferroelectric capacitor 8 becomes the state d and the data ""0" is held, the polarization state of the ferroelectric capacitor 9 becomes the state b, and the data "1" is held. In this way, in the semiconductor integrated circuit provided with the processing circuit including the D flip-flop circuit, the data held in the storage nodes N1 and N2 before the power is turned off are saved in the ferroelectric capacitors 9 and 8, respectively. Later, the power is turned off. Next, when the power is turned on again, first, the cell plate CP is set to the high level from time t4. At this time, the polarization state of the ferroelectric capacitor 8 changes from the state d to the state c, and the polarization state of the ferroelectric capacitor 9 changes from the state b to the state c. A potential is generated at the storage nodes N2 and N1. In this case, state b
The state of the storage node N1 to which the ferroelectric capacitor 9 changed from the state to the state c is higher than the potential of the storage node N2. Next, at time t5, the power supply V
When DD is turned on again, the D flip-flop circuit including the transistors 1, 2, 3, and 4 operates as a latch type sense amplifier, and the potential of the storage node N1 becomes high level, and the potential of the storage node N2 becomes high. Is set to the low level. The operation of the latch type sense amplifier is the same as that used in a DRAM or the like and is well known, and therefore, the description thereof is omitted. Then, at time t6, the cell plate C6 is set to the low level, and the supply of the clock signal CK is restarted. Thus, in the semiconductor integrated circuit, the data saved in the ferroelectric capacitors 8 and 9 is stored in the storage node N.
2 and N1 respectively. Here, as a simple example using the D flip-flop circuit, the circuit configuration of a 3-bit counter is shown in FIG. 4 and the operation thereof is shown in FIG. As shown in FIG. 5, during normal operation, the 3-bit counter increases its output Q to 1, 2, 3 in synchronization with the clock signal CK. "5" when the signal CK is stopped and the clock signal CK is stopped in the ferroelectric capacitors provided in each D flip-flop circuit
Is saved. And time t
b, when the power is turned on again, the internal data is restored from the ferroelectric capacitor to each D flip-flop circuit, and when the supply of the clock signal CK is resumed, when the clock signal CK is stopped. After restarting from the count “5”, the output Q increases to 6,7. As described above, in the semiconductor integrated circuit according to the present embodiment, the data at the storage nodes N2 and N1 are evacuated to the ferroelectric capacitors 8 and 9 connected to the storage nodes N2 and N1 before the power is turned off. Since the power supply is restored after the power is turned off, it is not necessary to use a nonvolatile memory having a peripheral circuit to realize the resume function. For this reason, the circuit configuration can be simplified, and there is no need for a dedicated circuit or software for accessing the nonvolatile memory. Further, the reading and writing time can be reduced by the amount by which the access to the nonvolatile memory becomes unnecessary.

[0006]

In the above embodiment, data is written to the ferroelectric capacitor by setting the cell plate CP to a high level before the power is turned off and immediately before the power is turned on again. However, the present invention is not limited to this. Instead, for example, the clock signal CK or the complementary clock signal / CK is connected to the cell plate CP, data is written to the ferroelectric capacitor in synchronization with the clock, and read even when the power is turned on again. Good. Such a semiconductor integrated circuit is also an example of the semiconductor integrated circuit in the present invention. Further, in the above embodiment, writing and reading of data to and from the ferroelectric capacitor were performed by setting the cell plate CP to the high level or the low level. However, the present invention is not limited to this. Is set at an intermediate level between the power supply voltage VDD and the ground potential,
Data may be written to the ferroelectric capacitor in accordance with a change in the input Q, and read out when the power is turned on again. Such a semiconductor integrated circuit is also an example of the semiconductor integrated circuit in the present invention. In the above embodiment, the storage nodes N2 and N1 and the ferroelectric capacitors 8 and 9 are directly connected. However, the present invention is not limited to this. For example, as shown in FIG. Transistors 11 and 12 for electrically coupling or separating the ferroelectric capacitors 8 and 9 are provided between them, and the storage node is used only when reading and writing data of the ferroelectric capacitors 9 and 8. N1 and N2 may be connected to the ferroelectric capacitors 9 and 8, respectively. In this case, the number of times of polarization reversal of the ferroelectric capacitors 9 and 8 can be reduced, and fatigue of the ferroelectric capacitors can be suppressed for a long time. In this case, short-circuit transistors 13 and 14 for short-circuiting both ends of the ferroelectric capacitors 8 and 9 may be provided to clear the polarization state of the ferroelectric capacitors 8 and 9 as necessary. . Such a semiconductor integrated circuit is also an example of the semiconductor integrated circuit in the present invention. Further, in the above embodiment, the ferroelectric capacitor is used for the non-volatile element. However, the present invention is not limited to this. For example, as shown in FIG. 7, the non-volatile transistor 2 ′ using the ferroelectric for the gate electrode is used. , 3 ′, 8 ′, 9 ′ may constitute the D flip-flop circuit. In this case, for each clock signal CK, the ferroelectric substance of the gate electrode is in a polarized state according to the data, and even if the power is cut off and the storage nodes N1 and N2 are set to the ground potential, after the power is turned on again, A potential corresponding to the polarization state of the gate electrode is generated at the storage nodes N1 and N2, and data is restored. It is not necessary to use the non-volatile transistors for all the transistors constituting the D flip-flop circuit.
A ferroelectric material may be used for at least one of the gate electrodes of the 3 ′ and the N-type MOS transistors 8 ′ and 9 ′. Such a semiconductor integrated circuit is also an example of the semiconductor integrated circuit in the present invention. In the above embodiment, the D flip-flop circuit is used as the sequential circuit of the processing circuit. However, the present invention is not limited to this, and another sequential circuit such as another flip-flop circuit or a latch circuit can be used. It is. Such a semiconductor integrated circuit is also an example of the semiconductor integrated circuit in the present invention. In the above embodiment, the 3-bit counter using the D flip-flop circuit is used. However, the present invention is not limited to this, and the present invention can be applied to other circuits using a sequential circuit. Such a semiconductor integrated circuit is also an example of the semiconductor integrated circuit in the present invention.

[0007]

According to the semiconductor integrated circuit according to any one of the first to sixth aspects, a nonvolatile element is provided corresponding to a storage node of a sequential circuit of a processing circuit so that data can be stored when power is cut off. It is not necessary to use a nonvolatile memory or the like having a peripheral circuit in order to realize a resume function for saving the data. For this reason, the circuit configuration can be simplified, and there is no need for a dedicated circuit or software for accessing the nonvolatile memory. Further, the time for writing and reading can be reduced by the amount that it is not necessary to access the nonvolatile memory having the peripheral circuit.

[Brief description of the drawings]

FIG. 1 is a diagram showing a schematic configuration of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining hysteresis characteristics of a ferroelectric material.

FIG. 3 is a diagram for explaining the operation of the semiconductor integrated circuit at the time of resume.

FIG. 4 is a diagram showing a schematic configuration example of a 3-bit counter.

FIG. 5 is a diagram for explaining the operation of the 3-bit counter.

FIG. 6 is a diagram showing a schematic configuration of a semiconductor integrated circuit according to one embodiment of the present invention.

FIG. 7 is a diagram showing a schematic configuration of a semiconductor integrated circuit according to another embodiment of the present invention.

FIG. 8 is a diagram showing a schematic configuration of a conventional nonvolatile memory.

[Explanation of symbols]

 8, 9 ... ferroelectric capacitor 11, 12 ... coupling / separation transistor 13, 14 ... short-circuit transistor N1, N2 ... storage node

Claims (6)

[Claims] An information processing apparatus comprising: a processing circuit comprising a sequential circuit and a combinational circuit, wherein data included in the sequential circuit of the processing circuit is saved in a nonvolatile element in advance before power is turned off, and the power is cut off. In a semiconductor integrated circuit capable of returning data saved in the nonvolatile element at the time of input to the sequential circuit of the processing circuit, the nonvolatile element is provided corresponding to a storage node of the sequential circuit of the processing circuit. A semiconductor integrated circuit characterized by the above. 2. The semiconductor integrated circuit according to claim 1, wherein the sequential circuit of the processing circuit is a flip-flop circuit or a latch circuit. 3. The semiconductor integrated circuit according to claim 2, wherein said nonvolatile element is connected to a storage node of said flip-flop circuit. 4. The semiconductor integrated circuit according to claim 3, further comprising: a coupling / separation element for coupling or separating said nonvolatile element and said flip-flop circuit; and a short-circuit element for short-circuiting said nonvolatile element. 5. The semiconductor integrated circuit according to claim 2, wherein the transistor constituting the flip-flop circuit uses a ferroelectric for a gate electrode. 6. The semiconductor integrated circuit according to claim 1, wherein data contained in a sequential circuit of said processing circuit is stored in said nonvolatile element in synchronization with a clock or input data.