JP6004697B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device. In this specification, a semiconductor device refers to a semiconductor element itself or a device including a semiconductor element, and an example of such a semiconductor element is a thin film transistor. Accordingly, a liquid crystal display device, a memory device, and the like are also included in the semiconductor device.

  In recent years, metal oxides that exhibit semiconductor characteristics (hereinafter referred to as oxide semiconductors) have attracted attention. An oxide semiconductor can be applied to a transistor (Patent Documents 1 and 2).

JP 2007-123861 A JP 2007-096055 A

  Semiconductor elements are arranged in a matrix in display devices, memory devices, and the like. The semiconductor elements arranged in a matrix are controlled by a peripheral drive circuit. One of the circuits constituting the peripheral drive circuit is a D flip-flop circuit.

  An object of one embodiment of the present invention is to provide a semiconductor device including a D flip-flop circuit that retains data even when the power is turned off during processing and does not require a data saving operation and a data restoring operation. One.

  One embodiment of the present invention includes a first input terminal and a second input terminal, a first latch portion and a second latch portion, a first transmission gate and a second transmission gate, an output terminal, The first latch portion includes a first inverter, a first clocked inverter, and a transistor, and the transistor uses a semiconductor material having a band gap larger than that of silicon for the channel region. A second latch unit including a second inverter and a second clocked inverter, wherein the first input terminal is electrically connected to the first terminal of the first transmission gate; The second terminal of the first transmission gate is electrically connected to the first latch portion, and the gate of the transistor is electrically connected to the second input terminal. The first latch portion is electrically connected to the first terminal of the second transmission gate, and the second terminal of the second transmission gate is electrically connected to the second latch portion. The second latch unit is a semiconductor device including a circuit electrically connected to the output terminal.

  Another embodiment of the present invention includes a first input terminal and a second input terminal, a first transmission gate and a second transmission gate, a first inverter and a second inverter, The clocked inverter and the second clocked inverter, a transistor, and an output terminal, the transistor using a semiconductor material having a band gap larger than that of silicon for a channel region, The input terminal is electrically connected to the first terminal of the first transmission gate, and the second terminal of the first transmission gate is the input terminal of the first inverter and the output terminal of the first clocked inverter. And the output terminal of the first inverter is connected to the first end of the second transmission gate. And the gate of the transistor is electrically connected to the second input terminal, and the other of the source or drain of the transistor is the input terminal of the first clocked inverter. The second terminal of the second transmission gate is electrically connected to the input terminal of the second inverter and the output terminal of the second clocked inverter, and the output terminal of the second inverter Is a semiconductor device including a circuit electrically connected to the output terminal and the input terminal of the second clocked inverter.

  Another embodiment of the present invention includes a first input terminal and a second input terminal, a first transmission gate and a second transmission gate, a first inverter and a second inverter, The clocked inverter and the second clocked inverter, a transistor, and an output terminal, the transistor using a semiconductor material having a band gap larger than that of silicon for a channel region, The input terminal is electrically connected to the first terminal of the first transmission gate, and the second terminal of the first transmission gate is one of the source or drain of the transistor and the output terminal of the first clocked inverter. And the gate of the transistor is electrically connected to the second input terminal. The other of the source and the drain of the transistor is electrically connected to the input terminal of the first inverter, and the output terminal of the first inverter is the input of the first terminal of the second transmission gate and the input of the first clocked inverter. And the second terminal of the second transmission gate is electrically connected to the input terminal of the second inverter and the output terminal of the second clocked inverter, and the output of the second inverter. The terminal is a semiconductor device including a circuit electrically connected to the output terminal and the input terminal of the second clocked inverter.

  In the above structure, the semiconductor material having a band gap larger than that of silicon is preferably an oxide semiconductor.

In the above structure, a transistor in which an oxide semiconductor is used for a channel region has an off-current per channel width of 1 × 10 ⁻¹⁹ A / μm or less.

  In the above configuration, an output signal is output simultaneously with the restart. In the present specification, “simultaneous” includes substantially simultaneous.

  According to one embodiment of the present invention, a semiconductor device including a D flip-flop circuit that retains data even when turned off during processing and does not require a data saving operation and a data restoring operation can be obtained.

  In addition, the area of the D flip-flop circuit can be reduced by providing a transistor using a semiconductor material having a band gap larger than that of silicon in the channel region only in the front stage of the D flip-flop circuit only in the front stage of the D flip-flop circuit. Can be planned.

6A and 6B illustrate a D flip-flop circuit of a semiconductor device which is one embodiment of the present invention. 2 is a timing chart for explaining the operation of the D flip-flop circuit in FIG. 1. 6A and 6B illustrate a D flip-flop circuit of a semiconductor device which is another embodiment of the present invention. 4 is a timing chart for explaining the operation of the D flip-flop circuit of FIG. 3. FIG. 10 is a cross-sectional view of an applicable transistor. 6A and 6B illustrate a method for manufacturing the transistor illustrated in FIGS. FIG. 13 shows characteristics of a transistor including an oxide semiconductor. FIG. 10 is a circuit diagram for evaluating characteristics of a transistor including an oxide semiconductor. 10 is a timing chart for evaluating characteristics of a transistor including an oxide semiconductor. FIG. 13 shows characteristics of a transistor including an oxide semiconductor. FIG. 13 shows characteristics of a transistor including an oxide semiconductor. FIG. 13 shows characteristics of a transistor including an oxide semiconductor.

  Hereinafter, embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below.

  Note that the functions of “source” and “drain” may be interchanged when transistors having different polarities are employed or when the direction of current changes during circuit operation. Therefore, in this specification, the terms “source” and “drain” can be used interchangeably.

“Electrically connected” includes a case of being connected via “something having an electric action”. Here, the “having some electric action” is not particularly limited as long as it can exchange electric signals between the connection targets.

  The position, size, range, and the like of each component illustrated in the drawings and the like may not represent the actual position, size, range, or the like for easy understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, range, or the like disclosed in the drawings and the like.

Ordinal numbers such as “first”, “second”, and “third” are used to avoid confusion between components.

(Embodiment 1)
In this embodiment, a D flip-flop circuit which is an example of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.
<Circuit configuration example>

  FIG. 1 is a circuit diagram of a D flip-flop circuit 100 which is one embodiment of the present invention.

  In the D flip-flop circuit 100 illustrated in FIG. 1A, the input terminal to which the data signal D is input is electrically connected to the first terminal of the transmission gate 102, and the second terminal of the transmission gate 102 is The node 104 is electrically connected to the input terminal of the inverter 104 and the output terminal of the clocked inverter 106 via the node N1, and one of the output terminal of the inverter 104 and the source or drain of the transistor 107 is connected to the transmission gate 108 via the node N2. The transistor 107 is electrically connected to the first terminal, the gate of the transistor 107 is electrically connected to the input terminal to which the gate control signal OSG is input, and the other of the source and the drain of the transistor 107 is clocked through the node FN. Electrically to the input terminal of the inverter 106 The second terminal of transmission gate 108 is electrically connected to the input terminal of inverter 110 and the output terminal of clocked inverter 112 via node N3, and the output terminal of inverter 110 and the input of clocked inverter 112 are connected. The terminal is electrically connected to an output terminal from which an output signal Q is output via a node N4. Note that FIG. 1B illustrates a structure of the clocked inverter 106 and the clocked inverter 112.

  The inverter 104, the clocked inverter 106, and the transistor 107 sandwiched between the second terminal of the transmission gate 102 and the first terminal of the transmission gate 108 can be collectively referred to as a latch unit 120. The inverter 110 and the clocked inverter 112 sandwiched between the second terminal of the gate 108 and the output terminal from which the output signal Q is output can be collectively referred to as a latch unit 130.

  In addition, in a period in which the power source of the D flip-flop circuit 100 is on and the transistor 107 is on, when the potential of the clock signal CLK is L level and the inverted clock signal CLKB is H level, the latch unit 120 is A loop structure (also called an inverter loop) is obtained. By forming such an inverter loop, the node FN is changed from the H level or the L level due to a decrease in the charge accumulated in the node FN serving as the data holding unit when the power supply is stopped for a long period. Even if the potential is slightly deviated, the H level or L level potential is supplied again. As a result, the potential of the node FN can be returned to the state before the change.

  In this embodiment mode, when the power source of the D flip-flop circuit 100 is changed from the off state to the on state even when the transistor 107 is provided in the latch unit 130 that is a subsequent stage of the D flip-flop circuit as in the latch unit 120. In addition, since the clocked inverter 112 is in a non-conductive state and cannot form an inverter loop, and the stored data cannot be output to the output terminal Q instantaneously, it does not make sense to provide the transistor 107 in the latch unit 130. Absent. Therefore, the transistor 107 may be provided only in the latch unit 120 that is the previous stage of the D flip-flop circuit. For this reason, the area of the D flip-flop circuit can be reduced.

  The transmission gate 102, the clocked inverter 106, the transmission gate 108, and the clocked inverter 112 are switched on / off of each configuration by receiving the clock signal CLK and the inverted clock signal CLKB.

As the transistor 107, a transistor having an extremely low off-state current (leakage current) per channel width of 1 × 10 ⁻¹⁹ A / μm or less, for example, a transistor including an oxide semiconductor that is a wide band gap semiconductor in a channel region is used. be able to. Note that a transistor having an off-current per channel width of 1 × 10 ⁻¹⁹ A / μm or less can also be realized using a semiconductor material having a band gap larger than that of silicon. Note that a semiconductor material having a band gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more may be used.

  Data is obtained at a node FN that is electrically connected to the other of the source and the drain of the transistor 107 in which a channel region is formed using an oxide semiconductor that is a wide band gap semiconductor and is in a floating state when the transistor is turned off. Hold. Note that the off-state current (leakage current) of the transistor is extremely low. Therefore, after setting the potential of the node FN to a specific value, the potential can be kept constant or almost constant by turning off the transistor. Thereby, accurate data can be held in the D flip-flop circuit.

  An oxide semiconductor has an energy gap of 3.0 eV or more, which is much larger than the band gap of silicon (1.1 eV).

The off-resistance of the transistor (referred to as resistance between the source and drain when the transistor is off) is inversely proportional to the concentration of thermally excited carriers in the semiconductor film in which the channel region is formed. Even in the state where there is no carrier due to donors or acceptors (intrinsic semiconductor), since the band gap is 1.1 eV in the case of silicon, the concentration of thermally excited carriers at room temperature (300 K) is 1 × 10 ^11. It is about cm ⁻³ .

On the other hand, for example, in the case of a semiconductor having a band gap of 3.2 eV (assuming an oxide semiconductor), the concentration of thermally excited carriers is about 1 × 10 ⁻⁷ cm ⁻³ . Since the resistivity is inversely proportional to the carrier concentration when the electron mobility is the same, the resistivity of a semiconductor with a band gap of 3.2 eV is 18 orders of magnitude higher than that of silicon.

  Note that in order to describe the “very low off-state current” of a transistor in which a channel region is formed using an oxide semiconductor that is a wide band gap semiconductor, the off-state current of a transistor using a highly purified oxide semiconductor is described below. The results of obtaining are described.

<Measurement of off-state current of transistor using oxide semiconductor>
First, in consideration of a sufficiently small off-state current of a transistor including a highly purified oxide semiconductor, a transistor having a sufficiently large channel width W of 1 m was prepared, and off-state current was measured. FIG. 7 shows the result of measuring the off-state current of a transistor having a channel width W of 1 m. In FIG. 7, the horizontal axis represents the gate voltage VG, and the vertical axis represents the drain current ID. When the drain voltage VD is +1 V or +10 V, it was found that the off-state current of the transistor is 1 × 10 ⁻¹² A or less, which is the detection limit, when the gate voltage VG is in the range of −5 V to −20 V. It was also found that the off-state current of the transistor (here, a value per unit channel width (1 μm)) is 1 aA / μm (1 × 10 ⁻¹⁸ A / μm) or less.

Next, a result obtained by more accurately obtaining the off-state current of a transistor including a highly purified oxide semiconductor will be described. As described above, it was found that the off-state current of a transistor including a highly purified oxide semiconductor is 1 × 10 ⁻¹² A or less, which is the detection limit of the measuring instrument. Therefore, a description will be given of a result obtained by fabricating a characteristic evaluation element and obtaining a more accurate off-current value (a value equal to or lower than the detection limit of the measuring device in the above measurement).

  First, the element for characteristic evaluation used in the current measurement method will be described with reference to FIG.

  In the element for characteristic evaluation shown in FIG. 8, three measurement systems 800 are connected in parallel. The measurement system 800 includes a capacitor 802, a transistor 804, a transistor 805, a transistor 806, and a transistor 808. As the transistor 804, the transistor 805, the transistor 806, and the transistor 808, a transistor including a highly purified oxide semiconductor was used.

  In the measurement system 800, one of the source and the drain of the transistor 804, one of the terminals of the capacitor 802, and one of the source and the drain of the transistor 805 are electrically connected to a power source (a power source that supplies V2). The other of the source and the drain of the transistor 804, one of the source and the drain of the transistor 808, the other terminal of the capacitor 802, and the gate of the transistor 805 are electrically connected. The other of the source and the drain of the transistor 808, one of the source and the drain of the transistor 806, and the gate of the transistor 806 are electrically connected to a power source (a power source that supplies V1). The other of the source and the drain of the transistor 805 and the other of the source and the drain of the transistor 806 are electrically connected to serve as an output terminal.

  Note that the gate of the transistor 804 is supplied with a potential Vext_b2 for controlling the on state and the off state of the transistor 804, and the potential Vext_b1 for controlling the on state and the off state of the transistor 808 is supplied to the gate of the transistor 808. Is done. Further, the potential Vout is output from the output terminal.

  Next, a current measuring method using the above element for characteristic evaluation will be described.

  First, an outline of an initial period in which a potential difference is applied in order to measure off current will be described. In the initial period, a potential Vext_b1 that turns on the transistor 808 is input to the gate of the transistor 808 and the node is electrically connected to the other of the source and the drain of the transistor 804 (that is, the source or the drain of the transistor 808). One of the terminals of the capacitor 802 and the node N5 which is electrically connected to the gate of the transistor 805 is supplied with the potential V1. Here, the potential V1 is, for example, a high potential. The transistor 804 is kept off.

  After that, the potential Vext_b1 that turns off the transistor 808 is input to the gate of the transistor 808, so that the transistor 808 is turned off. After the transistor 808 is turned off, the potential V1 is set low. Again, the transistor 804 is kept off. The potential V2 is the same as the potential V1. Thus, the initial period ends. In the state where the initial period is completed, a potential difference is generated between the node N5 and one of the source and the drain of the transistor 804, and a potential difference is generated between the node N5 and the other of the source and the drain of the transistor 808. Therefore, a slight amount of charge flows through the transistor 804 and the transistor 808. That is, an off current is generated.

  Next, an outline of the off-current measurement period will be described. In the measurement period, the potential of one terminal of the source or drain of the transistor 804 (that is, V2) and the potential of the other terminal of the source or drain of the transistor 808 (that is, V1) are fixed to a low potential. On the other hand, during the measurement period, the potential of the node N5 is not fixed (set to a floating state). Thus, charge flows through the transistor 804, and the amount of charge held at the node N5 varies with time. Then, the potential of the node N5 varies as the amount of charge held at the node N5 varies. That is, the output potential Vout of the output terminal also varies.

  FIG. 9 shows details (timing chart) of the relationship between the potentials in the initial period in which the potential difference is applied and the subsequent measurement period.

  In the initial period, first, the potential Vext_b2 is set to a potential (a high potential) at which the transistor 804 is turned on. As a result, the potential of the node N5 becomes V2, that is, the low potential (VSS). Note that it is not essential to apply a low potential (VSS) to the node N5. After that, the potential Vext_b2 is set to a potential (low potential) at which the transistor 804 is turned off, so that the transistor 804 is turned off. Then, the potential Vext_b1 is set to a potential (high potential) at which the transistor 808 is turned on. As a result, the potential of the node N5 becomes V1, that is, the high potential (VDD). After that, Vext_b1 is set to a potential at which the transistor 808 is turned off. As a result, the node N5 enters a floating state, and the initial period ends.

  In the subsequent measurement period, the potential V1 and the potential V2 are set to potentials at which charge flows into the node N5 or flows out from the node N5. Here, the potential V1 and the potential V2 are low potentials (VSS). However, since it is necessary to operate the output circuit at the timing of measuring the output potential Vout, V1 may be temporarily set to the high potential (VDD). Note that the period during which V1 is set to the high potential (VDD) is set to a short period that does not affect the measurement.

  When the potential difference is applied as described above and the measurement period is started, the amount of charge held at the node N5 varies with time, and the potential of the node N5 varies accordingly. This means that the potential of the gate of the transistor 805 fluctuates, so that the potential of the output potential Vout of the output terminal also changes with the passage of time.

  A method for calculating the off current from the obtained output potential Vout will be described below.

Prior to the calculation of the off-current, the relationship between the potential V _{N5 of the} node _N5 and the output potential Vout is obtained. Thereby, the potential V _{N5 of the} node N5 can be obtained from the output potential Vout. From the above relationship, the potential V _{N5 of the} node N5 can be expressed as the following equation as a function of the output potential Vout.

Further, the charge Q _N5 of the node N5 is expressed by the following equation using the potential V _{N5 of} the node N5, the capacitance C _N5 connected to the node N5, and a constant (const). Here, the capacitance C _N5 connected to the node N5 is the sum of the capacity and other capacitance of the capacitor 802.

Since the current I _N5 at the node N5 is a time derivative of the charge flowing into the node N5 (or the charge flowing out from the node N5), the current I _{N5 at the} node N5 is expressed by the following equation.

As described above, the current I _{N5 of the} node N5 can be obtained from the capacitor C _N5 connected to the node N5 and the output potential Vout of the output terminal.

  By the method described above, leakage current (off-state current) flowing between the source and drain of the transistor in the off state can be measured.

  In this example, the transistor 804, the transistor 805, the transistor 806, and the transistor 808 were manufactured using a highly purified oxide semiconductor having a channel length L = 10 μm and a channel width W = 50 μm. In each measurement system 800 in parallel, each capacitance value of the capacitive element 802 is set to 100 fF, 1 pF, and 3 pF.

  In the measurement according to this example, VDD = 5V and VSS = 0V. Further, during the measurement period, Vout was measured by setting the potential V1 as VSS in principle and setting VDD as the VDD only for a period of 100 msec every range of 10 sec to 300 sec. Further, Δt used for calculation of the current I flowing through the element was about 30000 sec.

  FIG. 10 shows the relationship between the elapsed time Time for the current measurement and the output potential Vout. From FIG. 10, it can be confirmed that the potential changes as time passes.

FIG. 11 shows the off-current at room temperature (25 ° C.) calculated by the current measurement. FIG. 11 shows the relationship between the source-drain voltage V and the off-current I. FIG. 11 shows that the off-state current is about 40 zA / μm (that is, 4 × 10 ⁻²⁰ A / μm) under the condition where the source-drain voltage is 4V. Further, it was found that the off-state current was 10 zA / μm or less (1 × 10 ⁻²⁰ A / μm or less) under the condition where the source-drain voltage was 3.1 V.

Furthermore, FIG. 12 shows the off-current in the temperature environment of 85 ° C. calculated by the current measurement. FIG. 12 shows the relationship between the source-drain voltage V and the off-current I under a temperature environment of 85 ° C. From FIG. 12, it was found that the off-state current was 100 zA / μm or less (1 × 10 ⁻¹⁹ A / μm or less) under the condition where the source-drain voltage was 3.1V.

  As described above, according to this example, it was confirmed that the off-state current of the transistor including a highly purified oxide semiconductor is sufficiently small.

  A transistor in which such a wide band gap oxide semiconductor is used for a semiconductor film can realize extremely low off-state current.

Note that in the circuit diagram in this specification, a transistor using an oxide semiconductor is described as “OS” so that the transistor can be clearly identified as a transistor using an oxide semiconductor.
<Circuit operation example>

  Next, the operation of the D flip-flop circuit 100 will be described with reference to FIG. FIG. 2 is a timing chart for explaining the operation of the D flip-flop circuit 100. Note that the hatched lines in the timing chart indicate portions that are either high potential (H level) or low potential (L level).

  First, the timing chart shown in FIG. 2 will be described. In FIG. 2, the period is divided into seven periods t1 to t7. The period t1 is an off period, the period t2 is an activation period, the period t3 is a processing period, the period t4 is a data holding period, the period t5 is an off period, the period t6 is a restart period, A period t7 is a processing period. Note that the power supply is on during the start-up period, data holding period, restart period, and processing period.

  The potential of the high-potential-side power supply potential line VDD is H level during the on period and L level during the off period. The potential of the low potential side power supply potential line VSS is the ground potential (0 V). Furthermore, the potential when the potential of the high-potential-side power supply potential line VDD is at the L level matches the ground potential (0 V).

  The clock signal CLK is input at a constant cycle only during the ON period.

  The inverted clock signal CLKB is an inverted version of the clock signal CLK. However, in the off period, the inverted clock signal CLKB is also at the L level in the same manner as the clock signal CLK.

  The data signal D is a signal input as data to the D flip-flop circuit 100, and is input at a constant cycle only during the ON period.

  First, the power supply of the D flip-flop circuit 100 is changed from an off state (period t1) to an on state (period t2). By turning on the power supply, VDD becomes H level. Although the clock signal CLK is not input, the gate control signal OSG is input and the H level is set to end the activation period, and the process period starts (period t2 to period t3). At this time, the transistor 107 is turned on by the gate control signal OSG.

  That is, in the activation period (period t2), the clock signal CLK is not input to the clocked inverter 106 and the clocked inverter 112, and the potential of the wiring to which the clock signal CLK is input is kept constant.

  In the period t3, the input of the data signal D is started, and the clock signal CLK becomes H level. Therefore, the potential of the node N1 becomes H level and the potential of the node N2 becomes L level. Thereafter, when the clock signal CLK becomes L level, the potential of the node N3 becomes L level, and the potential of the node N4 and the output signal Q become H level. After that, when the clock signal CLK becomes H level again, the potential of the node N1 becomes L level and the potential of the node N2 becomes H level. After that, when the clock signal CLK becomes L level, the potential of the node N3 becomes H level, and the potential of the node N4 and the output signal Q become L level. (Period t3). Thus, the cycle in which the clock signal CLK changes to H level, L level, H level, and L level is repeated, and the potentials of the node N1, the node N2, the node N3, and the node N4 and the output signal Q are determined accordingly. .

  Next, the gate control signal OSG is set to the L level, the transistor 107 is turned off, and the data holding process is performed before the D flip-flop circuit 100 is turned off (period t4). This period t4 is a state in which the data of the node N2 is already written in the node FN which is a data holding unit. For this reason, the operation | movement which saves data can be made unnecessary.

  Then, the power supply of the D flip-flop circuit 100 is changed from the on state (data retention period (period t4)) to the off state (period t5). After that, when the power supply is turned on, VDD becomes H level (from the period t5 to the period t6). Although the clock signal CLK is not input, the gate control signal OSG is input to become H level, the restart period ends, and the process period starts (period t6 to period t7). Then, the input of the data signal D is started again (period t7).

  Here, paying attention to the output signal Q, unlike the period t2, the data immediately before the power source of the D flip-flop circuit 100 is turned off (data holding period (period t4)) to the off state (period t5) is output. ing. This is because the immediately preceding data is held in the node FN which is a data holding unit, and the output signal Q is instantaneously output via the clocked inverter 106, the inverter 104, the transmission gate 108, and the inverter 110. A node FN serving as a data holding portion is provided between the other of the source and the drain of the transistor 107 and the input terminal of the clocked inverter 106. In order to realize a data holding portion that can hold data even when the power is turned off, a transistor with a small off-state current may be used as the transistor 107.

  As the transistor 107 described above, a transistor in which an oxide semiconductor is used for a channel region is preferably used.

  In this manner, the D flip-flop circuit 100 illustrated in FIG. 1A can hold data before being turned off, and can be turned off even during processing.

  When attention is paid to the node N1, the node N2, and the node N3, the potential (H level) of the node FN is simultaneously with the moment when the power of the D flip-flop circuit 100 is turned from the off state (period t5) to the on state (period t6). The potential input to the input terminal of the clocked inverter 106 and inverted by the clocked inverter 106 becomes the potential (L level) of the node N1. At the same time when the potential of the node N1 is determined, the potential of the node N1 (L level) is input to the input terminal of the inverter 104, and the potential inverted by the inverter 104 becomes the potential of the node N2 (H level). Further, simultaneously with the moment when the potential of the node N2 is determined, the potential (H level) of the node N3 is also determined through the transmission gate 108.

  In this way, at the same time when the power source of the D flip-flop circuit 100 is turned from the off state (period t5) to the on state (period t6), the data of the node FN serving as the data holding unit causes the node N1, the node N2, and the node N3. The output signal Q can be instantaneously output. That is, the data restoration operation can be made unnecessary.

  Accordingly, a D flip-flop circuit that retains data even when it is turned off during processing and does not require a data saving operation and a data restoring operation can be obtained. Therefore, a semiconductor device including the D flip-flop circuit can operate at high speed. Response and high-speed driving are possible, and a higher-performance semiconductor device can be realized.

  The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 2)
In this embodiment, a D flip-flop circuit which is an example of a semiconductor device of another embodiment of the present invention will be described with reference to FIGS.
<Circuit configuration example>

  FIG. 3 shows a circuit diagram of a D flip-flop circuit 200 which is another embodiment of the present invention.

  In the D flip-flop circuit 200 shown in FIG. 3, the input terminal to which the data signal D is input is electrically connected to the first terminal of the transmission gate 102, and the second terminal of the transmission gate 102 is connected to the node N1. The gate of the transistor 107 is electrically connected to an input terminal to which a gate control signal OSG is input, and the transistor 107 is electrically connected to one of a source and a drain of the transistor 107 and an output terminal of the clocked inverter 106. The other of the source and the drain of the inverter 104 is electrically connected to the input terminal of the inverter 104 via the node FN, and the output terminal of the inverter 104 is connected to the input terminal of the clocked inverter 106 and the transmission gate 108 via the node N2. Electrically connected to the first terminal The second terminal of transmission gate 108 is electrically connected to the input terminal of inverter 110 and the output terminal of clocked inverter 112 via node N3, and the output terminal of inverter 110 and the input terminal of clocked inverter 112 are connected. Are electrically connected to an output terminal from which an output signal Q is output via a node N4.

  The inverter 104, the clocked inverter 106, and the transistor 107 sandwiched between the second terminal of the transmission gate 102 and the first terminal of the transmission gate 108 can be collectively referred to as a latch unit 220. The inverter 110 and the clocked inverter 112 sandwiched between the second terminal of the gate 108 and the output terminal from which the output signal Q is output can be collectively referred to as a latch unit 130.

  In addition, in a period in which the power source of the D flip-flop circuit 200 is on and the transistor 107 is on, when the potential of the clock signal CLK is L level and the inverted clock signal CLKB is H level, the latch unit 220 is A loop structure (also called an inverter loop) is obtained. By forming such an inverter loop, the node FN is changed from the H level or the L level due to a decrease in the charge accumulated in the node FN serving as the data holding unit when the power supply is stopped for a long period. Even if the potential is slightly deviated, the H level or L level potential is supplied again. As a result, the potential of the node FN can be returned to the state before the change.

  In this embodiment, when the power source of the D flip-flop circuit 200 is changed from the off state to the on state even when the transistor 107 is provided in the latch unit 130, which is the subsequent stage of the D flip-flop circuit, as in the latch unit 220. In addition, since the clocked inverter 112 is in a non-conductive state and cannot form an inverter loop, and the stored data cannot be output to the output terminal Q instantaneously, it does not make sense to provide the transistor 107 in the latch unit 130. Absent. Therefore, the transistor 107 may be provided only in the latch unit 220 that is the previous stage of the D flip-flop circuit. For this reason, the area of the D flip-flop circuit can be reduced.

The difference between the structure shown in this embodiment and Embodiment 1 is that the place where the transistor 107 is provided is changed, and each structure is the same as that shown in Embodiment 1.
<Circuit operation example>

  Next, the operation of the D flip-flop circuit 200 will be described with reference to FIG. FIG. 4 is a timing chart for explaining the operation of the D flip-flop circuit 200. Note that the hatched lines in the timing chart indicate portions that are either high potential (H level) or low potential (L level).

  First, the timing chart shown in FIG. 4 will be described. In FIG. 4, the period is divided into seven periods t1 to t7. The period t1 is an off period, the period t2 is an activation period, the period t3 is a processing period, the period t4 is a data holding period, the period t5 is an off period, the period t6 is a restart period, A period t7 is a processing period. Note that the power supply is on during the start-up period, the data holding period, the restart period, and the processing period.

  In this embodiment, as in Embodiment 1, the potential of the high-potential-side power supply potential line VDD is H level during the on period, L level during the off period, and the clock signal CLK is constant only during the on period. It is input with the period of. The inverted clock signal CLKB is an inverted version of the clock signal CLK. However, in the off period, the inverted clock signal CLKB is also at the L level in the same manner as the clock signal CLK. The data signal D is a signal input to the D flip-flop circuit 200 as data, and is input at a constant cycle only during the ON period.

  First, the power supply of the D flip-flop circuit 200 is changed from an off state (period t1) to an on state (period t2). By turning on the power supply, VDD becomes H level. Although the clock signal CLK is not input, the gate control signal OSG is input and the H level is set to end the activation period, and the process period starts (period t2 to period t3). At this time, the transistor 107 is turned on by the gate control signal OSG.

  That is, in the activation period (period t2), the clock signal CLK is not input to the clocked inverter 106 and the clocked inverter 112, and the potential of the wiring to which the clock signal CLK is input is kept constant.

  In the period t3, the input of the data signal D is started, and the clock signal CLK becomes H level. Therefore, the potential of the node N1 becomes H level and the potential of the node N2 becomes L level. Thereafter, when the clock signal CLK becomes L level, the potential of the node N3 becomes L level, and the potential of the node N4 and the output signal Q become H level. After that, when the clock signal CLK becomes H level again, the potential of the node N1 becomes L level and the potential of the node N2 becomes H level. After that, when the clock signal CLK becomes L level, the potential of the node N3 becomes H level, and the potential of the node N4 and the output signal Q become L level. (Period t3). Thus, the cycle in which the clock signal CLK changes to H level, L level, H level, and L level is repeated, and the potentials of the node N1, the node N2, the node N3, and the node N4 and the output signal Q are determined accordingly. .

  Next, the gate control signal OSG is set to the L level, the transistor 107 is turned off, and the data holding process before the D flip-flop circuit 200 is turned off is performed (period t4). This period t4 is a state in which the data of the node N1 is already written in the node FN which is a data holding unit. For this reason, the operation | movement which saves data can be made unnecessary.

  Then, the power supply of the D flip-flop circuit 200 is changed from the on state (data retention period (period t4)) to the off state (period t5). After that, when the power supply is turned on, VDD becomes H level (from the period t5 to the period t6). Although the clock signal CLK is not input, the gate control signal OSG is input to become H level, the restart period ends, and the process period starts (period t6 to period t7). Then, the input of the data signal D is started again (period t7).

  Here, paying attention to the output signal Q, unlike the period t2, the data immediately before the power source of the D flip-flop circuit 200 is turned off (data holding period (period t4)) to the off state (period t5) is output. ing. This is because the immediately preceding data is held in the node FN which is a data holding unit, and the output signal Q is instantaneously output via the inverter 104, the transmission gate 108, and the inverter 110. A node FN serving as a data holding portion is provided between the other of the source and the drain of the transistor 107 and the input terminal of the inverter 104. In order to realize a data holding portion capable of holding data even when the power is turned off, a transistor with a small off-state current may be used as the transistor 107.

  As the transistor 107 described above, a transistor in which an oxide semiconductor is used for a channel region is preferably used.

  As described above, the D flip-flop circuit 200 illustrated in FIG. 3 can hold data before being turned off, and can be turned off even during processing.

  When attention is paid to the node N1, the node N2, and the node N3, the potential (L level) of the node FN is simultaneously with the moment when the power of the D flip-flop circuit 200 is turned off (period t5) to on (period t6). The potential input to the input terminal of the inverter 104 and inverted by the inverter 104 becomes the potential (H level) of the node N2. At the same time when the potential of the node N2 is determined, the potential of the node N3 (H level) and the potential of the node N2 (H level) are input to the input terminal of the clocked inverter 106 via the transmission gate 108, The potential inverted by the inverter 106 determines the potential (L level) of the node N1.

  In this way, at the same time when the power of the D flip-flop circuit 200 is turned from the off state (period t5) to the on state (period t6), the data of the node FN that is the data holding unit causes the nodes N1, N2, and N3 The output signal Q can be instantaneously output. That is, the data restoration operation can be made unnecessary.

  Accordingly, a D flip-flop circuit that retains data even when it is turned off during processing and does not require a data saving operation and a data restoring operation can be obtained. Therefore, a semiconductor device including the D flip-flop circuit can operate at high speed. Response and high-speed driving are possible, and a higher-performance semiconductor device can be realized.

  The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 3)
In this embodiment, an example of a method for manufacturing a transistor that can be applied to the present invention will be described with reference to FIGS. FIG. 5 is a diagram illustrating an example of a schematic cross-sectional structure of a transistor. In FIG. 5, a transistor with a small off-state current is formed over a transistor provided over a semiconductor substrate. The transistor provided on the semiconductor substrate may include both a p-channel transistor and an n-channel transistor, or only one of them may be provided.

  The p-channel transistor and the n-channel transistor provided on the semiconductor substrate may be formed by a general method. After forming a p-channel transistor provided on the semiconductor substrate and an n-channel transistor provided on the semiconductor substrate, a transistor having a small off-state current is formed thereon. That is, a semiconductor substrate 300 provided with a p-channel transistor and an n-channel transistor is used as a formation substrate, and a transistor with low off-state current is formed over the substrate. As a transistor with low off-state current, a transistor in which an oxide semiconductor is used for a channel region can be given.

  Note that a semiconductor substrate 300 provided with a p-channel transistor and an n-channel transistor includes a high-concentration impurity region 301, a low-concentration impurity region 302, a gate insulating film 303, a gate electrode 304, and an interlayer that function as a source region and a drain region. An insulating film 305 is provided (see FIG. 5).

  A transistor 310 using an oxide semiconductor for a channel region is separated from and in contact with the oxide semiconductor film 311 provided over the semiconductor substrate 300 provided with the p-channel transistor and the n-channel transistor. The source electrode 312a and the drain electrode 312b provided in this manner, the gate insulating film 313 provided over at least the channel region of the oxide semiconductor film 311, and the gate insulating film 313 provided over the oxide semiconductor film 311 Gate electrode 314a (see FIG. 6D). Note that although not illustrated, the gate electrode 314a and the electrode 314b are electrically connected, and the gate electrode 304 and the electrode 314b are electrically connected.

  First, the oxide semiconductor film 311 is formed over the interlayer insulating film 305 (see FIG. 6A).

  The interlayer insulating film 305 also functions as a base insulating film for the oxide semiconductor film 311. As the interlayer insulating film 305, a single layer selected from a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, or a silicon nitride oxide film, or a stacked film thereof is used. Can do.

  As the interlayer insulating film 305, an insulating film (oxygen supply film) that releases oxygen by heat treatment is preferably used.

“Release oxygen by heat treatment” means that the amount of released oxygen converted to oxygen atoms is 1.0 × 10 ¹⁹ atoms / cm in TDS (Thermal Desorption Spectroscopy) analysis. ³ or more, preferably 3.0 × 10 ¹⁹ atoms / cm ³ or more, more preferably 1.0 × 10 ²⁰ atoms / cm ³ or more, more preferably 3.0 × 10 ²⁰ atoms / cm ³ or more. Say.

  Here, a method for measuring the amount of released oxygen converted into oxygen atoms in TDS analysis will be described below.

  The amount of gas released by TDS analysis is proportional to the integral value of the spectrum. For this reason, the amount of gas emission can be calculated from the ratio between the measured integral value of the spectrum and the reference value of the standard sample. The reference value of the standard sample is the ratio of the atomic density to the integral value of the spectrum in a sample having a predetermined atomic density.

For example, the amount of released oxygen molecules (N _O2 ) of the insulating film is obtained by the equation (1) from the TDS analysis result of a silicon wafer containing hydrogen of a predetermined density as a standard sample and the TDS analysis result of the insulating film. Can do. Here, it is assumed that all of the spectra detected when the mass-to-charge ratio (M / z) obtained by TDS analysis is 32 are derived from oxygen molecules. There is CH ₃ OH in addition to M / z of 32, but it is not considered here as it is unlikely to exist. In addition, oxygen molecules containing an oxygen atom with an M / z of 17 and an oxygen atom with an M / z of 18 that are isotopes of oxygen atoms are not considered because their abundance ratio in nature is extremely small.

N _H2 is a value obtained by converting hydrogen molecules desorbed from the standard sample by density. _SH2 is an integral value of a spectrum obtained by TDS of a standard sample. Here, the reference value of the standard sample is N _H2 / SH ₂ . S _O2 is an integral value of a spectrum obtained by TDS analysis of the insulating film. α is a coefficient that affects the spectral intensity in TDS. For details of the above formula, refer to Japanese Patent Laid-Open No. 6-275697. The oxygen release amount of the insulating film is a silicon wafer containing 1 × 10 ¹⁶ atoms / cm ³ hydrogen atoms as a standard sample using a temperature programmed desorption analyzer EMD-WA1000S / W manufactured by Electronic Science Co., Ltd. Use to measure.

  In TDS analysis, part of oxygen is detected as oxygen atoms. The ratio of oxygen molecules to oxygen atoms can be calculated from the ionization rate of oxygen molecules. Note that since the above α includes the ionization rate of oxygen molecules, the amount of released oxygen atoms can be estimated by evaluating the amount of released oxygen molecules.

Note that N _{2 O 2} is the amount of released oxygen molecules. The amount of release when converted to oxygen atoms is twice the amount of release of oxygen molecules.

Further, when the hydrogen concentration of the oxygen supply film is 7.2 × 10 ²⁰ atoms / cm ³ or more, the variation in the initial characteristics of the transistor increases, the dependency on the electrical characteristics of the transistor increases in the L length, and further, BT In the stress test, the hydrogen concentration of the insulating film containing excess oxygen is less than 7.2 × 10 ²⁰ atoms / cm ³ because it deteriorates greatly. That is, the hydrogen concentration of the oxide semiconductor film is preferably 5 × 10 ¹⁹ atoms / cm ³ or less, and the hydrogen concentration of the insulating film containing excess oxygen is preferably less than 7.2 × 10 ²⁰ atoms / cm ³ .

Further, a blocking film (such as AlO _x ) that suppresses oxygen release from the oxide semiconductor film is preferably provided so as to surround the oxide semiconductor film and be disposed outside the insulating film containing excess oxygen.

  By wrapping the oxide semiconductor film with an insulating film or blocking film containing excess oxygen, the oxide semiconductor film is in a state that substantially matches the stoichiometric composition, or has a supersaturated state that contains more oxygen than the stoichiometric composition. State. For example, when the oxide semiconductor film is IGZO, an example of the stoichiometric composition is In: Ga: Zn: O = 1: 1: 1: 4 [atomic ratio], and thus the atomic ratio of oxygen is 4 Or it will be in the state containing four or more.

  Note that in this specification, “oxynitride” such as silicon oxynitride indicates a composition having a higher oxygen content than nitrogen.

  Note that in this specification, “nitride oxide” such as silicon nitride oxide indicates a composition having a higher nitrogen content than oxygen.

  The interlayer insulating film 305 may be formed by a sputtering method or a CVD method, but is preferably formed by a sputtering method. In the case of forming a silicon oxide film as the interlayer insulating film 305, a quartz (preferably synthetic quartz) target may be used as a target, and argon gas may be used as a sputtering gas. Alternatively, a silicon target may be used as the target, and a gas containing oxygen may be used as the sputtering gas. Note that the gas containing oxygen may be a mixed gas of argon gas and oxygen gas, or may be only oxygen gas.

  After the interlayer insulating film 305 is formed and before the oxide semiconductor film 311 is formed, first heat treatment is performed. The first heat treatment is a step for removing water and hydrogen contained in the interlayer insulating film 305. The temperature of the first heat treatment is higher than a temperature at which water and hydrogen contained in the interlayer insulating film 305 are desorbed (a temperature having a desorption amount peak), and a semiconductor provided with a p-channel transistor and an n-channel transistor The temperature may be lower than the temperature at which the substrate 300 is denatured or deformed, preferably 400 ° C. or higher and 750 ° C. or lower, and lower than the second heat treatment performed later.

  Then, after the oxide semiconductor film 311 is formed, second heat treatment is performed. The second heat treatment is a step of supplying oxygen to the oxide semiconductor film 311 using the interlayer insulating film 305 as a supply source of oxygen. Note that the timing of performing the second heat treatment is not limited to this, and may be performed after the oxide semiconductor film 311 is processed.

  Note that the second heat treatment is preferably performed in a nitrogen gas or a rare gas atmosphere such as helium, neon, or argon, and the atmosphere preferably does not contain hydrogen, water, a hydroxyl group, hydride, or the like. Alternatively, the purity of nitrogen gas introduced into the heat treatment apparatus or a rare gas such as helium, neon, or argon is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

  Note that depending on the conditions of the second heat treatment or the material of the oxide semiconductor film 311, the oxide semiconductor film 311 may be crystallized to be a microcrystalline layer or a polycrystalline layer. For example, it may be a microcrystalline layer having a crystallization rate of 90% or more or 80% or more. Further, depending on the conditions of the second heat treatment or the material of the oxide semiconductor film 311, the amorphous semiconductor film does not include a crystalline component in some cases. In addition, microcrystals (crystal grain size of 1 nm or more and 20 nm or less) may be mixed in the amorphous layer.

  Note that the interlayer insulating film 305 serves as a supply source of oxygen in the second heat treatment.

  For the oxide semiconductor film 311, for example, an In-M-Zn-O-based material may be used. Here, the metal element M is an element whose binding energy with oxygen is higher than that of In and Zn. Alternatively, the element has a function of suppressing release of oxygen from the In-M-Zn-O-based material. Generation of oxygen vacancies in the oxide semiconductor film is suppressed by the action of the metal element M. Therefore, variation in electrical characteristics of the transistor due to oxygen deficiency can be reduced, and a highly reliable transistor can be obtained.

  Specifically, the metal element M is Al, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Ga, Y, Zr, Nb, Mo, Sn, La, Ce, Pr, Nd, Sm, Eu. Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta or W, preferably Al, Ti, Ga, Y, Zr, Ce or Hf. The metal element M may be selected from one or more of the above elements. Further, Si or Ge can be used instead of the metal element M.

  Here, in an oxide semiconductor represented by an In-M-Zn-O-based material, carrier mobility and carrier density increase as the concentration of In increases. As a result, the higher the In concentration, the higher the conductivity of the oxide semiconductor.

  The oxide semiconductor film 311 may have a single-layer structure or a stacked structure. The oxide semiconductor film 311 may be single crystal, polycrystalline (also referred to as polycrystal), or amorphous (also referred to as amorphous).

  In this embodiment, the oxide semiconductor film 311 is preferably a CAAC-OS (C Axis Crystallized Oxide Semiconductor) film.

  The CAAC-OS film is not completely single crystal nor completely amorphous. The CAAC-OS film is an oxide semiconductor film with a crystal-amorphous mixed phase structure where crystal parts and amorphous parts are included in an amorphous phase. Note that the crystal part is often large enough to fit in a cube whose one side is less than 100 nm. Further, in the observation image obtained by a transmission electron microscope (TEM), the boundary between the amorphous part and the crystal part included in the CAAC-OS film is not clear. Further, a grain boundary (also referred to as a grain boundary) cannot be confirmed in the CAAC-OS film by TEM. Therefore, in the CAAC-OS film, reduction in electron mobility due to grain boundaries is suppressed.

  The crystal part included in the CAAC-OS film has a c-axis aligned in a direction parallel to the normal vector of the formation surface of the CAAC-OS film or the normal vector of the surface, and is viewed from a direction perpendicular to the ab plane. It has a triangular or hexagonal atomic arrangement, and metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers as seen from the direction perpendicular to the c-axis. Note that the directions of the a-axis and the b-axis may be different between different crystal parts. In this specification, a simple term “perpendicular” includes a range from 85 ° to 95 °. In addition, a simple term “parallel” includes a range from −5 ° to 5 °.

  Note that the distribution of crystal parts in the CAAC-OS film is not necessarily uniform. For example, in the formation process of the CAAC-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, the ratio of crystal parts in the vicinity of the surface of the oxide semiconductor film is higher in the vicinity of the surface. In addition, when an impurity is added to the CAAC-OS film, the crystal part in a region to which the impurity is added becomes amorphous in some cases.

  Since the c-axis of the crystal part included in the CAAC-OS film is aligned in a direction parallel to the normal vector of the formation surface of the CAAC-OS film or the normal vector of the surface, the shape of the CAAC-OS film (formation surface) Depending on the cross-sectional shape of the surface or the cross-sectional shape of the surface). Note that the c-axis direction of the crystal part is in a direction parallel to the normal direction of the surface where the CAAC-OS film is formed or the normal direction of the surface. The crystal part is formed by film formation or by performing crystallization treatment such as heat treatment after film formation.

  A transistor including a CAAC-OS film can reduce variation in electrical characteristics due to irradiation with visible light or ultraviolet light. Therefore, the transistor has high reliability.

  The oxide semiconductor film is preferably in a supersaturated state in which oxygen is higher than that in the stoichiometric composition immediately after the formation. For example, in the case where an oxide semiconductor film is formed by a sputtering method, the film formation is preferably performed under a condition where the proportion of oxygen in the film formation gas is large, and the film formation is performed particularly in an oxygen atmosphere (oxygen gas 100%). It is preferable. When a film is formed under conditions where the proportion of oxygen in the film forming gas is large, particularly in an atmosphere containing 100% oxygen gas, for example, even when the film forming temperature is set to 300 ° C. or higher, the release of Zn from the film can be suppressed.

  The oxide semiconductor film 311 may have a structure in which a plurality of oxide semiconductor films are stacked. For example, the oxide semiconductor film 311 is formed as a stack of a first oxide semiconductor film and a second oxide semiconductor film, and metal oxides having different compositions are formed on the first oxide semiconductor film and the second oxide semiconductor film. You may use thing. For example, a ternary metal oxide may be used for the first oxide semiconductor film, and a binary metal oxide may be used for the second oxide semiconductor film. For example, the first oxide semiconductor film and the second oxide semiconductor film may both be ternary metal oxides.

  Alternatively, the constituent elements of the first oxide semiconductor film and the second oxide semiconductor film may be the same, and the composition ratio of the two may be different. For example, the atomic ratio of the first oxide semiconductor film is In: Ga: Zn = 1: 1: 1, and the atomic ratio of the second oxide semiconductor film is In: Ga: Zn = 3: 1: 2. It is good. The atomic ratio of the first oxide semiconductor film is In: Ga: Zn = 1: 3: 2, and the atomic ratio of the second oxide semiconductor film is In: Ga: Zn = 2: 1: 3. It is good.

  At this time, the In and Ga contents in the oxide semiconductor film on the side close to the gate electrode (channel side) of the first oxide semiconductor film and the second oxide semiconductor film are preferably In> Ga. The content ratio of In and Ga in the oxide semiconductor film far from the gate electrode (back channel side) is preferably In ≦ Ga.

  In oxide semiconductors, heavy metal s orbitals mainly contribute to carrier conduction, and increasing the In content tends to increase the overlap of s orbitals. Compared with an oxide having a composition of In ≦ Ga, high mobility is provided. In addition, since Ga has a larger energy generation energy of oxygen deficiency than In, and oxygen deficiency is less likely to occur, an oxide having a composition of In ≦ Ga has stable characteristics compared to an oxide having a composition of In> Ga. Prepare.

  By using an oxide semiconductor with an In> Ga composition on the channel side and an oxide semiconductor with an In ≦ Ga composition on the back channel side, the mobility and reliability of the transistor can be further improved. It becomes.

  Alternatively, oxide semiconductors having different crystallinities may be used for the first oxide semiconductor film and the second oxide semiconductor film. In other words, a single crystal oxide semiconductor, a polycrystalline oxide semiconductor, an amorphous oxide semiconductor, or a CAAC-OS film may be combined as appropriate. In addition, when an amorphous oxide semiconductor is applied to at least one of the first oxide semiconductor film and the second oxide semiconductor film, internal stress and external stress of the oxide semiconductor film 311 are relieved, The variation in characteristics of the transistor is reduced, and the reliability of the transistor can be further improved.

  On the other hand, an amorphous oxide semiconductor easily absorbs an impurity serving as a donor such as hydrogen, and oxygen vacancies easily occur. Therefore, it is preferable to use a crystalline oxide semiconductor such as a CAAC-OS film as the channel-side oxide semiconductor film.

  Alternatively, the oxide semiconductor film 311 may have a stacked structure of three or more layers, and a structure in which an amorphous semiconductor film is sandwiched between a plurality of crystalline semiconductor films. Alternatively, a structure in which a crystalline semiconductor film and an amorphous semiconductor film are alternately stacked may be employed.

  The above structures in the case where the oxide semiconductor film 311 has a stacked structure of a plurality of layers can be used in appropriate combination.

  Alternatively, the oxide semiconductor film 311 may have a multilayer structure, and oxygen may be added after each oxide semiconductor film is formed. For the addition of oxygen, heat treatment in an oxygen atmosphere, ion implantation, ion doping, plasma immersion ion implantation, plasma treatment performed in an atmosphere containing oxygen, or the like can be used.

  By adding oxygen each time an oxide semiconductor film is formed, the effect of reducing oxygen vacancies in the oxide semiconductor can be enhanced.

  Next, the source electrode 312a and the drain electrode 312b provided over and in contact with the oxide semiconductor film 311 are formed (see FIG. 6B).

  For the source electrode 312a and the drain electrode 312b, for example, a conductive film (eg, a metal film or a silicon film to which an impurity element of one conductivity type is added) is formed by a sputtering method, and an etching mask is formed over the conductive film. It may be selectively formed by forming and etching. Alternatively, an inkjet method or the like may be used. Note that the conductive film to be the source electrode 312a and the drain electrode 312b may be formed with a single layer or a stack of a plurality of layers. For example, a three-layer structure in which an Al layer is sandwiched between Ti layers may be used.

  Next, the gate insulating film 313 is formed at least over the channel formation region of at least the oxide semiconductor film 311, and an opening is formed after the gate insulating film 313 is formed (see FIG. 6C). The opening is formed in a portion overlapping with the gate electrode 304.

  For the gate insulating film 313, for example, an insulating material (eg, silicon nitride, silicon nitride oxide, silicon oxynitride, or silicon oxide) film may be formed by a film formation process using high-density plasma. Note that the gate insulating film 313 may be formed as a single layer or a stack of a plurality of layers. Here, for example, a two-layer structure in which a silicon oxynitride layer is stacked over a silicon nitride layer is employed. Note that plasma damage in the gate insulating film 313 can be reduced by generation of high-density plasma. Accordingly, dangling bonds in the gate insulating film 313 can be reduced, defects can be reduced, and an interface with the oxide semiconductor formed thereafter can be made extremely favorable. It is preferable that the gate insulating film 313 be an insulating oxide film because oxygen can be supplied to fill the oxygen vacancies.

  The gate insulating film 313 is preferably formed using an insulating oxide which contains oxygen at least in contact with the oxide semiconductor film 311 and from which part of oxygen is released by heating. That is, it is preferable to use the materials listed as examples of the material of the interlayer insulating film 305. For example, when the portion of the gate insulating film 313 that is in contact with the oxide semiconductor film 311 is formed using silicon oxide, oxygen can be diffused into the oxide semiconductor film 311 and the resistance of the transistor can be prevented from being lowered.

Note that as the gate insulating film 313, hafnium silicate (HfSi _x O _y , x> 0, y> 0), hafnium silicate to which nitrogen is added (HfSi _x O _y , x> 0, y> 0), nitrogen is added When a high-k material such as hafnium aluminate (HfAl _x O _y , x> 0, y> 0), hafnium oxide, yttrium oxide, or lanthanum oxide is used, gate leakage current can be reduced. Here, the gate leakage current refers to a leakage current that flows between the gate electrode and the source or drain electrode. Further, a layer formed using a high-k material and a layer formed using silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, and gallium oxide may be stacked. Note that even in the case where the gate insulating film 313 has a stacked structure, the portion in contact with the oxide semiconductor film 311 is preferably an insulating oxide.

  The gate insulating film 313 may be formed by a sputtering method. The thickness of the gate insulating film 313 may be 1 nm to 300 nm, preferably 5 nm to 50 nm. When the thickness of the gate insulating film 313 is 5 nm or more, the gate leakage current can be particularly reduced.

  Here, third heat treatment (preferably 200 ° C. to 400 ° C., for example, 250 ° C. to 350 ° C.) may be performed in an inert gas atmosphere or an oxygen gas atmosphere. By the third heat treatment, hydrogen or moisture remaining in the oxide semiconductor film 311 can be diffused into the gate insulating film. Further, by performing the third heat treatment, oxygen can be supplied to the oxide semiconductor film 311 using the gate insulating film 313 as a supply source.

  The third heat treatment may be performed not only after the gate insulating film 313 is formed over the oxide semiconductor film 311 but also after the conductive film to be the gate electrode 314a and the electrode 314b is formed.

  Next, a conductive film is formed over the gate insulating film 313, an etching mask is formed over the conductive film, and etching is performed, whereby the gate electrode 314a and the electrode 314b are formed. (See FIG. 6D).

  The gate electrode 314a and the electrode 314b may be formed using a material and a method similar to those of the source electrode 312a and the drain electrode 312b.

  Note that although not illustrated, it is preferable to form a source region and a drain region in the oxide semiconductor film 311 by adding a dopant to the oxide semiconductor film 311 using the gate electrode 314a as a mask.

  Here, the dopant may be added by an ion implantation method or an ion doping method. Alternatively, the dopant may be added by performing plasma treatment in a gas atmosphere containing the dopant. In addition, nitrogen, phosphorus, boron, or the like may be used as a dopant to be added.

  As described above, a transistor in which an oxide semiconductor is used for a channel region can be manufactured over the transistor provided in the semiconductor substrate illustrated in FIG.

  The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

100 D flip-flop circuit 102 Transmission gate 104 Inverter 106 Clocked inverter 107 Transistor 108 Transmission gate 110 Inverter 112 Clocked inverter 120 Latch unit 130 Latch unit 200 D flip-flop circuit 220 Latch unit 300 Semiconductor substrate 301 High concentration impurity region 302 Low concentration Impurity region 303 Gate insulating film 304 Gate electrode 305 Interlayer insulating film 310 Transistor 311 Oxide semiconductor film 312a Source electrode 312b Drain electrode 313 Gate insulating film 314a Gate electrode 314b Electrode 800 Measurement system 802 Capacitance element 804 Transistor 805 Transistor 806 Transistor 808 Transistor

Claims (5)

A first input terminal, a second input terminal, a first latch unit, a second latch unit, a first transmission gate, a second transmission gate, and an output terminal;
It said first latch portion includes a first inverter, a first clocked inverter, and
Second latch portion before SL includes a second inverter, and a second clocked inverter, and
Of the first latch portion and the second latch portion, only the first latch portion includes a transistor having an oxide semiconductor in a channel formation region,
The first input terminal is electrically connected to a first terminal of the first transmission gate;
A second terminal of the first transmission gate is electrically connected to the first latch portion;
A gate of the transistor is electrically connected to the second input terminal;
The first latch portion is electrically connected to a first terminal of the second transmission gate;
A second terminal of the second transmission gate is electrically connected to the second latch portion;
The semiconductor device, wherein the second latch portion is electrically connected to the output terminal. A first input terminal, a second input terminal, a first latch unit, a second latch unit, a first transmission gate, a second transmission gate, and an output terminal;
The first latch unit includes a first inverter and a first clocked inverter,
The second latch unit includes a second inverter and a second clocked inverter,
Of the first latch portion and the second latch portion, only the first latch portion includes a transistor having an oxide semiconductor in a channel formation region,
The first input terminal is electrically connected to a first terminal of the first transmission gate;
A second terminal of the first transmission gate is electrically connected to an input terminal of the first inverter and an output terminal of the first clocked inverter;
An output terminal of the first inverter is electrically connected to a first terminal of the second transmission gate and one of a source and a drain of the transistor;
A gate of the transistor is electrically connected to the second input terminal;
The other of the source and the drain of the transistor is electrically connected to the input terminal of the first clocked inverter,
A second terminal of the second transmission gate is electrically connected to an input terminal of the second inverter and an output terminal of the second clocked inverter;
An output terminal of the second inverter is electrically connected to the output terminal and an input terminal of the second clocked inverter. A first input terminal, a second input terminal, a first latch unit, a second latch unit, a first transmission gate, a second transmission gate, and an output terminal;
The first latch unit includes a first inverter and a first clocked inverter,
The second latch unit includes a second inverter and a second clocked inverter,
Of the first latch portion and the second latch portion, only the first latch portion includes a transistor having an oxide semiconductor in a channel formation region,
The first input terminal is electrically connected to a first terminal of the first transmission gate;
A second terminal of the first transmission gate is electrically connected to one of a source or a drain of the transistor and an output terminal of the first clocked inverter;
A gate of the transistor is electrically connected to the second input terminal;
The other of the source and the drain of the transistor is electrically connected to the input terminal of the first inverter,
An output terminal of the first inverter is electrically connected to a first terminal of the second transmission gate and an input terminal of the first clocked inverter;
A second terminal of the second transmission gate is electrically connected to an input terminal of the second inverter and an output terminal of the second clocked inverter;
An output terminal of the second inverter is electrically connected to the output terminal and an input terminal of the second clocked inverter. In any one of Claim 1 thru | or 3,
A clock signal and an inverted clock signal are input to the first clocked inverter,
The clock signal and the inverted clock signal are input to the second clocked inverter,
The first transmission gate has a function of switching on and off according to the clock signal and the inverted clock signal,
The second transmission gate has a function of switching on and off in accordance with the clock signal and the inverted clock signal. In claim 4,
After the supply of the clock signal and the inverted clock signal to the first clocked inverter, the second clocked inverter, the first transmission gate, and the second transmission gate is stopped, the transistor Is turned off,
After the transistor is turned off, the supply of power to the semiconductor device is stopped,
After the supply of power to the semiconductor device resumes, the transistor is turned on,
After the transistor is turned on, the clock signal and the inverted clock signal to the first clocked inverter, the second clocked inverter, the first transmission gate, and the second transmission gate A semiconductor device characterized in that supply is resumed.

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