JP4820632B2 - Semiconductor integrated circuit device and information system - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device and an information system, and more particularly to a technology effective when applied to the configuration of a semiconductor integrated circuit used in a microprocessor and a semiconductor integrated circuit requiring low power consumption operation characteristics.

  In recent years, with the miniaturization of semiconductor chip manufacturing processes, an increase in leakage current has become a problem. The leakage current mainly includes a sub-threshold leakage current due to a reduction in threshold voltage, a gate leakage current due to thinning of the gate insulating film due to miniaturization, and a GIDL (Gate induced drain leakage) current.

  As a technique studied by the present inventor, for example, there is a method of shutting off a part of a circuit during standby in order to reduce leakage current. In this method, as shown in Patent Document 1, the combinational circuit is composed of transistors having a low threshold voltage, and a switch having a large gate width W and a low resistance is arranged on the n-type transistor side and the p-type transistor side. Connect this switch in series with the circuit's power and ground wires. During standby, the combination circuit is powered off by turning off this switch. The latch circuit is composed of a transistor having a high threshold voltage, and no switch is placed between the gate, the power supply, and the ground line. During standby, the power supply is not shut off, and the latch circuit holds information.

  In the future, as further miniaturization progresses, it becomes important to reduce leakage current not only during standby but also during operation. As a unit of power shutdown, there are an area including a plurality of functional blocks, a functional block, and a state machine. In Patent Document 2, the power supply is cut off in units of functional blocks. A power cutoff register having a bit indicating power supply for each functional block is provided. When the functional block is not used, the corresponding bit of the register is invalidated to stop the power supply for each functional block.

  Non-Patent Document 1 describes power-off at the state machine level. The state machine is a logic circuit composed of a combinational circuit and a flip-flop (FF), and has a fine granularity as a unit for shutting off the power. In Non-Patent Document 1, an FF to which a clock is not supplied holds output data, and pays attention to the fact that the input data is don't care. During the period in which the clock is not supplied, the power supply of the logic circuit related to the input data is turned on. Cut off.

In Non-Patent Document 1, the power of the combinational circuit is shut off. However, in Patent Document 3, the power of the flip-flop (FF) is shut off. While the D type FF captures and holds data, the power source of the preceding stage D latch which is a dynamic part in the D type FF is shut off. A clock signal is used as a power-off signal.
JP-A-6-29834 Japanese Patent Laid-Open No. 7-141074 JP 2002-319852 A U. Kimiyoshi et al., “Dynamic Sleep Control for Finite-State-Machines to Redeactive Activity” ”, IEICE Trans. Fundamentals, December 2004, Volume E87-A, No. 12, p. 3116-3123

  By the way, as a result of the study of the technique for reducing leakage current as described above, the following has been clarified.

  For example, the technique disclosed in Non-Patent Document 1 is a fine power-off at the state machine level and can be expected to reduce the leakage current, but has the following two problems.

  The first problem in Non-Patent Document 1 will be described with reference to FIG. The first problem is that the timing of the path passing through the power switch when power is shut off or when power is supplied deteriorates and the frequency decreases. In Non-Patent Document 1, the power supply of a logic circuit related to input data is shut off during a period when the FF clock is not supplied. In FIG. 11, this corresponds to the power-off of the gate in the region 40 related to the input data during the period when the clock enable signal en of the FF is negated. Since the gates other than the region 40 are related to generation of the clock signal and the clock enable signal, the power cannot be shut off. The FF clock enable signal en is used as a switch control signal for the power switch 46 in the area 40.

  Here, timing deterioration will be specifically described using a path through which a gate passes. When the power switch 46 is not provided, it passes through at most three stages of gates such as the inverter 41, the OR gate 43, and the OR gate 44. However, when the power switch 46 is inserted, a path passing through five stages of gates such as the inverter 41, the AND-OR gate 42, the power switch 46, the OR gate 43, and the OR gate 44 is formed. The more gate stages, the worse the timing. In order to solve this problem, the control signal of the power switch needs to be a signal having a small number of logic stages.

  Accordingly, a first object of the present invention is to provide a semiconductor integrated circuit technology capable of powering off a state machine using a signal having a small number of logic stages.

  The second problem in Non-Patent Document 1 will be described with reference to FIG. The second problem is that when there are a plurality of control signals for the power switch, the number of gates that can shut off the power is reduced. In FIG. 12, the clock enable signal en1 of FF1 and the clock enable signal en2 of FF2 are used as switch control signals. The gate to be powered off needs to satisfy the following two conditions.

  (A) It is not involved in FF clock enable signal generation.

  (B) FF input data signal connected to different clock enable signals.

  Since the gate (1) 50 is used to generate the clock enable signal of the FF2, the condition (A) is not satisfied. Since the gate (5) 54 is used as input data of FF1 and FF2, the condition (B) is not satisfied. Only the gate (2) 51 can be cut off by the clock enable signal en1 of the FF1, and the gates (3) 52 and the gate (4) 53 can be cut off by the clock enable signal en1 of the FF2. In order to solve this problem, it is necessary to use a signal commonly used in many FFs as a control signal for the power switch.

  Accordingly, a second object of the present invention is to provide a semiconductor integrated circuit technology capable of shutting off the power of a state machine using a signal that is commonly used by many FFs.

  In Non-Patent Document 1, it is noted that the FF to which no clock is supplied holds the output data, and the input data is don't care. Cut off. Here, in order to further reduce the leakage power, when focusing on the FF, it is desired to shut off the power supply to the input circuit of the FF while satisfying the condition for holding the output data. If a signal common to the power switch of the combinational circuit related to input data is used, an increase in logic is unnecessary. In Patent Document 3, the power of the logic circuit on the input side of the FF is shut off using a clock signal. The power supply is cut off while the delay circuit output signal, which is delayed by a quarter of the clock signal, is at the H level. Since the power is shut down each time the clock is at the H level, the frequency is high and the power consumption due to switching of the power switch is large.

  Therefore, a third object of the present invention is to cut off the power of the FF input circuit using a signal for controlling the power off of the combination circuit of the state machine in order to reduce the power consumption due to the switching of the power switch. An object of the present invention is to provide a semiconductor integrated circuit technology that can be used.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, a semiconductor integrated circuit device and an information system according to the present invention have a functional block having a combinational circuit, a flip-flop, and a clock tree. The clock tree includes a first clock driver that performs clock control of the entire functional block, a second clock driver that performs clock control of a first number (several tens to several hundreds) of flip-flops, and the first A third clock driver that performs clock control of a second number (1 to 8) of flip-flops smaller than the number of 1 is hierarchically connected. A power switch for supplying power to the combinational circuit and the preceding latch in the flip-flop is provided, and the power switch is controlled by a control signal of the second clock driver.

  Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  By using a signal based on the control signal on the upper side of the clock tree as the control signal for the power switch, it is possible to control the power supply of a wide range of combinational circuits and flip-flops while suppressing deterioration in timing compared to the case without power control. Thus, the leakage current during operation is reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 1 shows a main part of a functional block (FB) according to the semiconductor integrated circuit device according to the first embodiment of the present invention. The functional block 1 and the clock generator (PLL) 2 shown in FIG. 1 are not particularly limited, but the semiconductor integrated circuit technology for forming a known CMOS (complementary MOS transistor), bipolar transistor, etc. It is formed on one semiconductor substrate.

  The functional block 1 is connected with a clock clk output from the PLL 2 and a module stop signal / mstp (inversion of mstp) as to whether to stop the clock of the functional block 1 as inputs. The functional block (FB) 1 includes a clock tree, flip-flops 7 and 8, a combinational circuit, a power switch 9, and the like.

  The clock tree includes a hierarchical multi-stage B clock driver (first clock driver; B-drv) 3, C clock driver (second clock driver; C-drv) 4, D clock driver (third clock driver). D-drv) 5 and 6 and clock buffers 14 and 15; Each clock driver has an AND gate for the clock signal and the clock enable signal, and a latch for removing clock glitches. B-drv3 is a clock driver located at the top of the clock tree, and is used to stop the clock from B-drv3 by negating the module stop signal / mstp of function block 1 when the entire function block does not operate. Is done. D-drvs 5 and 6 are connected to about 1 to 8 FFs, and generate FF clocks.

  In FIG. 1, en1 is used as the clock enable signal of D-drv5 of FF7, and en2 is used as the clock enable signal of D-drv6 of FF8. C-drv4 generates tens to hundreds of FF clocks. As the C-drv4 clock enable signal cen, for example, there is a cache miss signal, which is used to stop the FF clock when a cache miss occurs.

  The combinational circuit is composed of gates such as AND gates and inverters. The power switch 9 is inserted in series between the combinational circuit in the region 11 or the ground line (Vssm) of the FF 7 and FF 8 and the ground line (Vss) of the functional block 1.

  The features of the present invention will be described using the operation of the semiconductor integrated circuit device according to the first embodiment. Similar to Non-Patent Document 1, when the clock of the FF is stopped, the output data of the FF is retained, and the characteristic that the input data becomes don't care is used. As a control signal for the power switch 9, a pctl signal is given from the power control circuit (Vctl) 13.

  The power supply control circuit 13 receives the clock enable signal cen of C-drv4 as an upper stage clock driver of the clock tree. The internal configuration of the power supply control circuit 13 will be described later with reference to FIG.

  When the cen signal is negated, the clocks of the clock drivers C-drv4 to D-drv5, 6 are stopped, and the clocks of FF7 and FF8 are stopped. At this time, the region 11 which is the logic gate group of the inputs of FF7 and FF8 is don't care, and the power may be shut off. In addition, the power supply of some input circuits of the FF can be cut off. The power cutoff in the FF will be described later with reference to FIG.

  Since the AND gate 12 is involved in the C-drv4 clock enable signal cen generation signal, the power supply cannot be cut off. Regarding power supply, a control signal is given to turn on the power switch. By using a high-speed power switch, the ground line Vssm is immediately equivalent to Vss and can be handled in the same way as a normal gate without a power switch.

  FIG. 3 shows the configuration of the power supply control circuit 13. The power supply control circuit 13 receives the C-drv4 clock enable signal cen and the clock clk signal as inputs. The power supply control circuit 13 includes a Φ2 latch 32, a delay circuit 33 using an inverter, an RS latch (RSLT) 36 using NOR gates 34 and 35, and an OR gate 37. As the set signal S of the RS latch 36, cen_p2dly (inversion of cen_p2dly) passed through the delay circuit 33 is used as the Φ2 latch output of cen as the reset signal R. The operation will be described later with reference to the timing chart of FIG.

  The difference between Embodiment 1 and Non-Patent Document 1 is the following three points mentioned in [Problems to be Solved by the Invention].

  First, as a control signal for the power switch 9, a signal based on the enable signal cen of the higher-order clock driver C-drv4 of the clock tree is used. The power supply control circuit 13 requires several stages as the number of logic stages, but the clock driver enable signal itself is a signal with a small number of logic stages, so that it is possible to avoid timing deterioration in the path passing through the power switch.

  Second, it is used to control the power switch 9 based on signals commonly used in many FFs. Since C-drv4 generates several tens to several hundreds of FF clocks and can be handled as a common enable signal by many FFs, the effect of reducing leakage power when the power is shut off is great.

  Third, not only the power supply of the combinational circuit is cut off, but also the power supply of the FF input side circuit is cut off to further reduce the leakage power. Furthermore, the control signal of the power switch can be shared by the combinational circuit and the FF.

  Next, with reference to FIG. 2, FIG. 3, and FIG. FIG. 2 shows a circuit configuration of the FFs 7 and 8 used in the first embodiment. FFs 7 and 8 are edge-triggered D-type flip-flops, and a D-type front-stage latch DLT_A23 and a rear-stage latch DLT_B24 are placed in series. Before and after the latch, an input inverter 22 and an output inverter 28 for enhancing the driving force are placed. CK1 attribute CK and Φ2 attribute CKB signals are used for the clock. Vssm is connected as a ground line to the inverter 22 and the inverter 26 and the clocked inverter 27 of the preceding latch DLT_A. The clock inverter 21, the inverter 29 of the latch DLT_B at the subsequent stage, the clocked inverter 30, and the output inverter 28 are connected to Vss as a ground line.

  FIG. 4 shows a timing chart of the FF when the power is shut off and the power is supplied. FF7 in FIG. 1 is assumed as the FF in FIG. clk is the input clock of the functional block FB, cen is the clock enable signal of the clock driver C-drv4, cen_p2 is the Φ2 latch 32 output of cen in the power supply control circuit 13, CK is the clock of the internal Φ1 attribute of FF, / cen_p2dly (cen_p2dly Is the output of the delay circuit 33 in the power supply control circuit 13, pctl is the output of the power supply control circuit 13, DI is the input data of FF, and DO is the output data of FF. pctl is a signal used for power control of the combinational circuit or the FF, and power is supplied when asserted and power is shut off when negated. CK is a gated clock, which is asserted between times t1 and t2 and between t5 and t6, and is negated at other times.

  In order to prevent malfunction, the power supply and clock must satisfy the following order. As a power-off sequence, (1) it is necessary to cut off the power after stopping the clock. Further, as a power supply sequence, (2) it is necessary to supply a clock after power supply. In order to satisfy the order of (1), in FIG. 4A, after the clock CK is stopped at time t2, the power supply control signal pctl is negated after delaying (dly), and the power supply is shut off. In order to satisfy the order of (2), in FIG. 4B, in order to supply power before supplying the clock, pctl is asserted as soon as the cen signal is asserted.

  In the circuit of FIG. 3, the Φ2 latch 32 and the delay circuit 33 are used for the delay of the delay from CK in (A), and the cen signal and the OR gate 37 are used for the power supply signal in (B). This is realized by using an RS latch 36 for holding the signal. Since the input DI of the FF has indefinite data at the time of power-off and other fixed value data, it is assumed here that it is 0 before time t2 and 1 after time t4. Thus, it can be said that the output DO always has a definite value even when the power is shut off, and holds 0 before time t5 and 1 after time t5.

  The power cut-off in the combinational circuit region 11 is the same as the power cut-off of the FF, and the power control is performed at the same timing using the power control circuit 13 output pctl signal.

(Embodiment 2)
FIG. 5 shows a functional block configuration of the semiconductor integrated circuit device according to the second embodiment of the present invention. In the second embodiment, one power switch is provided for each gate or each cell. As for the cell for shutting off the power, the pctl signal output from the power control circuit 13 is connected as the control signal for the power switch, and Vdd is connected for the cell not shutting off the power.

  The power shut-off and power supply operations are the same as those in the first embodiment shown in FIG. The method having a power switch in each gate or cell in the second embodiment has an area overhead because it has a power switch even with respect to a power non-interruptible gate, but the power supply design in the layout process is easy due to the regularity of the power switch. There is an advantage to.

(Embodiment 3)
FIG. 6 shows a functional block configuration of the semiconductor device according to the third embodiment of the present invention. As described in the first problem of [Problem to be Solved by the Invention], the problem in performing power-off at the state machine level using a power switch is that the power switch in power-off or power-supply The path passing through the timing deteriorates and the frequency decreases.

  In the first embodiment of FIG. 1, a countermeasure is taken by using a signal based on the signal cen having a small number of logic stages as a control signal for the power switch. In the third embodiment, as a means for preventing further deterioration in timing, a method of using a power-off mechanism only when the functional block operates at a low frequency is used. That is, in addition to the configuration of FIG. 1, the semiconductor integrated circuit device according to the third embodiment includes a frequency control register FRQCR 71 of a clock control unit (CCTL) 70. The frequency control register is a register mapped in the I / O space of the address, and the high-speed mode H-spd and low-speed mode L-spd of the functional block can be set by software. The frequency mode freq_mode from the FRQCR 71, the power control circuit output pctl, and the OR gate 72 are ORed to generate a power switch control signal. By adopting such a configuration, pctl is effective only in the low speed mode, and power is always supplied in the high speed mode. Other operations are the same as those of the first embodiment shown in FIG.

(Embodiment 4)
FIG. 7 shows a functional block configuration of a semiconductor integrated circuit device according to the fourth embodiment of the present invention. FIG. 7 shows a modification of the power supply control circuit in FIG. 1 which is the first embodiment. In FIG. 7, the power supply control signal pctl indicates a signal generated in the external module or in the module, and is not limited to the clock enable signal cen as shown in FIG. However, the power control signal pctl needs to satisfy the order of the clock and the power shutoff and non-shutoff as shown in the timing chart of FIG.

(Embodiment 5)
FIG. 8 shows a configuration of a power supply control circuit (Vctl) according to the semiconductor integrated circuit device according to the fifth embodiment of the present invention. The power supply control circuit (Vctl) shown in FIG. 8 is logically simplified with respect to the power supply control circuit (Vctl) 13 according to the first embodiment shown in FIG. In FIG. 3, a circuit such as the clock enable signal cen, the Φ2 latch 32 of the cen, and the RS latch 36 is required, but in FIG. 8, only the Φ2 latch 32 of the cen is provided. FIG. 9 shows a timing chart of the FF when the power is cut off and the power is supplied when the power control circuit (Vctl) of FIG. 8 is used. As a power-off sequence, (1) it is necessary to cut off the power after stopping the clock. Further, as a power supply sequence, (2) it is necessary to supply a clock after power supply.

  In FIG. 9, since the power control signal pctl and the Φ2 latch output cen_ph2 of cen are equivalent, in the order relationship of (1), as shown in FIG. As for the order relationship (2), as shown in FIG. 9B, the clock is supplied after the power is supplied. Although the power supply control circuit can simplify the logic, it must be carefully designed so that the clock stop does not lag behind the power shutdown.

(Embodiment 6)
As a suitable application example of the semiconductor integrated circuit device according to the first to fifth embodiments, an example of an information system including a functional block for shutting off the power at the state machine level is shown in FIG. The information system shown in FIG. 10 is a mobile phone system, for example, and is roughly composed of a communication part and an application part.

  The communication part includes a high-frequency unit (RF) 90 that transmits and receives radio waves using an antenna, a baseband processor (first information processing unit; BBP) 89 that performs a baseband modem and codec, and a memory (first storage unit; MRYa) 88. Have. The application part includes a central processing unit (CPU) 95, an MPEG codec (MPG) 92, a 3D graphics accelerator (3DG) 93, a 2D graphics accelerator (2DG) 94, an interrupt controller (INTC) 96, and a clock controller as an IP group. An application processor (second information processing unit; AP) 80 incorporating (CCTL) 70 is mainly configured. The application processor 80 is connected to a baseband processor (BBP) 89 by a bus (BUS) via an interface (I / F) 81, and is connected to a camera (CMR) 83, a memory card (CARD) via a peripheral interface (PPH) 82. ) 84, a sound source unit (SOD) 85, and a keyboard (KEY) 86, and connected to a liquid crystal display (LCD) 87 and a memory (storage unit; MRYb) 91 via an external bus. As the functional block 1 that performs power shutdown according to the present invention, it can be applied to the CPU 95 and the IP groups MPG92, 3DG93, 2DG94, and BBP89. This system configuration example is intended for mobile phones, but configuration examples using various systems such as portable information terminals and digital cameras are conceivable. With this system, power consumption is reduced because the power supply is appropriately shut down when the IP operation is unnecessary, and the added value of the portable information system can be increased.

  As mentioned above, the invention made by the present inventor has been specifically described based on the first to sixth embodiments. If the effects obtained by the representative ones of the first to sixth embodiments are briefly described, the following will be described. It is as follows.

  As miniaturization of semiconductor integrated circuits progresses, it is important to reduce leakage current not only during standby but also during operation. The effectiveness of shutting down the power supply is known for reducing the leakage current. Therefore, in the present invention, the leakage current is reduced by dynamically performing power-off at the fine-grain state machine level as a unit of power-off at the time of operation. In the functional block, when the clock of the flip-flop stops, the contents of the flip-flop are not lost, and the power supply to a part of the flip-flop is cut off in addition to the combinational circuit.

  Conventionally, in power shutdown at the state machine level, timing deterioration due to power control and circuits that can shut off power are limited to small combinational circuits. Although power control is performed by a power switch, in the present invention, a signal based on a control signal on the upper side of the clock tree is used as a control signal for the power switch, thereby suppressing timing deterioration compared to the case without power control. A wide range of combinational circuits and flip-flop power control are now possible. In addition, a mode that does not affect the timing is provided by controlling the power supply only when the frequency is low.

  As a result, it is possible to perform fine-grained power shutdown during operation in the functional block, and reduce leakage current during operation.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be used in the manufacturing industry of semiconductor integrated circuit devices and electronic devices.

In the semiconductor integrated circuit device by Embodiment 1 of this invention, it is a figure which shows the structure of a functional block. 1 is a circuit diagram showing a configuration of a flip-flop in a semiconductor integrated circuit device according to a first embodiment of the present invention. 1 is a circuit diagram showing a configuration of a power supply control circuit in a semiconductor integrated circuit device according to a first embodiment of the present invention. 5 is a timing chart showing an operation related to power supply cutoff of the flip-flop in the semiconductor integrated circuit device according to the first embodiment of the present invention. In the semiconductor integrated circuit device by Embodiment 2 of this invention, it is a figure which shows the structure of a functional block. In the semiconductor integrated circuit device by Embodiment 3 of this invention, it is a figure which shows the structure of a functional block. In the semiconductor integrated circuit device by Embodiment 4 of this invention, it is a figure which shows the structure of a functional block. FIG. 10 is a circuit diagram showing a configuration of a power supply control circuit in a semiconductor integrated circuit device according to a fifth embodiment of the present invention. 10 is a timing chart showing an operation related to power-off of a flip-flop in a semiconductor integrated circuit device according to a fifth embodiment of the present invention. It is a figure which shows the structure of the system for mobile phones in the information system by Embodiment 6 of this invention. In the semiconductor integrated circuit device examined as a premise of the present invention, it is an explanatory diagram showing an example of timing deterioration. In the semiconductor integrated circuit device examined as a premise of the present invention, it is an explanatory diagram showing an example of the number of gates that can be shut off.

Explanation of symbols

1 functional block 2 clock generator 3 B clock driver (first clock driver)
4 C clock driver (second clock driver)
5,6 D clock driver (third clock driver)
7, 8, 61, 62 Flip-flop 9, 46 Power switch 11, 40 Region 12, 45, 50, 53 AND gate 13 Power control circuit 14, 15 Clock buffer 23, 24 D-type latches 21, 22, 26, 28, 29, 41 Inverter 27, 30 Clocked inverter 25, 31 Transmission gate 32 φ2 latch 33 Delay circuit 34, 35 NOR gate 36 RS latch 37, 43, 44, 51, 54, 72 OR gate 42 AND-OR gate 52 2 inputs Selector 70 Clock control unit 71 Frequency control register 80 Application processor (second information processing unit)
81 Interface 82 Peripheral interface 83 Camera 84 Memory card 85 Sound source unit 86 Keyboard 87 Liquid crystal display 88 Memory (first storage unit)
89 Baseband processor (first information processing unit)
90 High-frequency unit 91 Memory (second storage unit)
92 MPEG codec 93 3D graphics accelerator 94 2D graphics accelerator 95 Central processing unit 96 Interrupt controller

Claims (8)

A semiconductor integrated circuit device having a functional block comprising a combinational circuit composed of a plurality of logic gates, a plurality of flip-flops, and a clock tree for supplying a clock to the flip-flops,
The clock tree is
A first clock driver that performs clock control of the entire functional block;
A second clock driver for clock control of the first number of flip-flops;
A third clock driver which performs clocking of the first smaller than the number of the second number of the flip-flop state, and are not hierarchically connected,
A power switch for supplying power to the combinational circuit and the previous latch in the flip-flop;
The semiconductor integrated circuit device , wherein the power switch is switch-controlled by a clock enable signal for enabling / disabling the operation of the second clock driver . The semiconductor integrated circuit device according to claim 1 .
The flip-flop comprises a clock buffer, an input inverter, the front stage latch, a rear stage latch, and an output inverter,
The front stage latch and the rear stage latch each have a transmission gate, an inverter, and a clocked inverter,
The semiconductor integrated circuit device, wherein the input inverter, the inverter in the preceding latch, and the clocked inverter in the preceding latch are connected to the power switch. The semiconductor integrated circuit device according to claim 1 .
A semiconductor integrated circuit device, wherein each of the gates and the flip-flops constituting the combinational circuit is provided with the power switch. The semiconductor integrated circuit device according to claim 1 .
Having a clock controller with a register for frequency control;
2. The semiconductor integrated circuit device according to claim 1, wherein the functional block inputs a frequency mode signal representing a frequency mode from the register and performs switch control of the power switch based on the frequency mode signal. An antenna,
A first information processing unit that performs code processing on a signal obtained from the antenna;
A first storage unit coupled to the first information processing unit;
A second information processing unit having a plurality of functional blocks, a clock transmitter and a clock control unit;
A second storage unit coupled to the second information processing unit,
The functional block includes a combinational circuit including a plurality of logic gates, a plurality of flip-flops, and a clock tree that supplies a clock to the flip-flops.
The clock tree includes a first clock driver that performs clock control of the entire functional block, a second clock driver that performs clock control of the first number of the flip-flops, and a second number that is less than the first number. the number of the third clock driver which performs clocking of the flip-flop of state, and are not hierarchically connected,
A power switch for supplying power to the combinational circuit and the previous latch in the flip-flop;
The information system according to claim 1, wherein the power switch is switch-controlled by a clock enable signal for enabling / disabling the operation of the second clock driver . The information system according to claim 5 , wherein
The flip-flop comprises a clock buffer, an input inverter, the front stage latch, a rear stage latch, and an output inverter,
The front stage latch and the rear stage latch each have a transmission gate, an inverter, and a clocked inverter,
The information system, wherein the input inverter, the inverter in the preceding latch, and the clocked inverter in the preceding latch are connected to the power switch. The information system according to claim 5 , wherein
An information system, wherein each of the gates and the flip-flops constituting the combinational circuit is provided with the power switch. The information system according to claim 5 , wherein
Having a clock controller with a register for frequency control;
The information system according to claim 1, wherein the functional block inputs a frequency mode signal representing a frequency mode from the register and performs switch control of the power switch based on the frequency mode signal.

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