JP2005079360A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the following problems: when a state of a logic circuit in a latch circuit is held at the time of power switch-off, a leakage of a current cannot be completely decreased or a long time holding is difficult to consume the power required for a refleshing by the conventional technology. <P>SOLUTION: A typical circuit is provided by a field effect transistor composed of a polycrystal thin film having a channel region of not more than 5 nm, and a dynamic latch composed of a CMOS circuit with the transistor connected to its gate input terminal. This holds the state of the logic circuit at the time of a shut-off of the power switch. Further, the power switch is provided at every circuit block. When a failure is found in the information holding means at the time of a test, the power switch of the function block is kept conductive even the block is not used. Further, the power switch is tuned off and the state of the logic circuit can be held in the dynamic latch in an unused circuit block even at the time of operation of the whole semiconductor integrated circuit. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to information retention of a latch circuit in a semiconductor integrated device, particularly a semiconductor integrated circuit in which a switch is provided between a power source and a circuit for blocking leakage current.

  Most of the current semiconductor integrated circuits are constructed using CMOS circuits. The CMOS circuit has an advantage that an AC current accompanying charge / discharge of the load capacitance flows only during operation, and hardly flows during standby. Therefore, it is particularly suitable for realizing a low power semiconductor integrated circuit. However, in the latest semiconductor integrated circuit using a fine field effect transistor having a processing dimension of about 0.15 μm or less, an increase in DC current is a problem. This is because the power supply voltage is lowered with the miniaturization of the field effect transistor, and the threshold voltage of the field effect transistor needs to be set low in order to secure the speed. That is, since the threshold voltage is low, a subthreshold leakage current that cannot be ignored always flows. The subthreshold leakage current increases rapidly when the threshold voltage of the field effect transistor is set low. For this reason, the increase in power due to the subthreshold leakage current is expected to become more serious in the future as miniaturization progresses.

  As means for reducing the subthreshold leakage current, a method has been proposed in which a power switch composed of a field effect transistor is provided between a CMOS circuit and a power supply line, and the field effect transistor is turned off during standby. For example, the method described on pages 847 to 854 of the IEEE Journal of Solid State Circuits issued in August 1995 (Non-patent Document 1) And the method described on pages 192 to 193 of the proceedings of the International Conference on Solid State Devices (ISSCC) held in San Francisco in February 1998 is known (non-patented) Reference 2). The former is a method in which a field effect transistor having a high threshold voltage and negligible leakage current is used as a power switch. The latter is a method of preventing leakage current by setting the gate voltage to a negative potential during standby instead of using a field effect transistor having a low threshold voltage for the power switch to operate to a lower voltage. The former is called MTCMOS (Multi-Threshold CMOS), and the latter is called SCCMOS (Super Cut-off CMOS). Various other methods for cutting the leakage current using a power switch have been proposed. Hereinafter, such methods are collectively referred to as a power switch method.

  In the simple power switch method, the latch information is lost when the power is cut off, and thus the internal state of the logic circuit cannot be restored when the power is turned on again. Therefore, a method for solving this problem has also been proposed. For example, there are a method of saving latch information in an external memory and a method of devising a latch circuit. The former example is described in the 128th column of JP-A-5-110392 (Patent Document 1). In the standby state, the latch information is saved in an external memory to cut off the power, and during operation, the power switch is turned on and the data is returned to the latch. An example of the latter is the method described on pages 125-126 of the proceedings of the Symposium on VLSI Circuits held in Kyoto in June 1995 (Symposium on VLSI Circuits). (Hereinafter referred to as the balloon latch method) (Non-patent Document 3), the method described in Japanese Patent Application Laid-Open No. 2000-77982 (hereinafter referred to as the non-volatile latch method) (Patent Document 2), or Japanese Patent Application Laid-Open No. 5-110392. 3 (hereinafter referred to as a dynamic method) (Patent Document 3).

  In the balloon latch system, in addition to the original latch, a latch composed of a small-sized field effect transistor to which power is always supplied is provided for standby. In the nonvolatile latch system, information in the latch is saved in a ferroelectric capacitor provided in the latch. Since the ferroelectric capacitor operates as a non-volatile memory, the contents of the latch can be stored even if the power is cut off during standby. In the dynamic method, latch information is held in a dynamic cell composed of a normal capacitor and a field effect transistor. Since the charge stored in the capacitor leaks, a refresh operation is necessary. However, it can be expected that the power consumption is less than that of a balloon latch provided with a latch for standby.

JP 5-110392 A (column 128)

Japanese Unexamined Patent Publication No. 2000-77982 Japanese Unexamined Patent Publication No. 5-110392 JP 2000-269457 A (paragraph 0010, FIG. 23) JP 2002-94029 A (paragraph 0017, FIG. 1) IEEE Journal of Solid State Circuits (issued August 1995, pages 847 to 854) 1998 Solid State Device Conference (ISSCC) Preliminary Proceedings (pages 192 to 193) 1995 International Symposium on Semiconductor Circuits (Symposium on VSI Circuit) Proceedings (125-126 pages)

Of the conventional examples described above, the method of saving latch information to an external memory takes time if the number of latches is large because the external memory is accessed for saving and restoring data. Therefore, it is not suitable for a semiconductor integrated circuit on which a large-scale circuit is mounted. On the other hand, the type in which the latch circuit is devised in the conventional example described above does not require a long time for saving and rereading data. However, each has the following problems. First, in the balloon latch system, power must always be supplied to the latch circuit for holding information, so that the leakage current cannot be cut completely. If the semiconductor process is further miniaturized in the future, the number of latches increases as the number of mounted circuits increases, and the voltage is further lowered. Therefore, the leakage current in the latch portion for holding information may become a non-negligible amount. There is. On the other hand, the nonvolatile latch system is excellent in terms of power consumption because the power supply can be completely shut off. However, as is well known, ferroelectric capacitors have a limited number of times of writing. For this reason, there may be a problem in reliability when a short-term standby state frequently occurs. For example, assume that a system that requires a waiting time of about 10 milliseconds is operated continuously for 10 years. Then, since a standby state of 3 × 10 ¹⁰ (3 × 10 ¹⁰ ) times occurs, the number of times of writing to the ferroelectric material should be at least 10 11 (10 ¹¹ ) times with a margin. It is necessary to guarantee about 10 ¹² times (10 ¹² ) times. However, it is generally said that the limit of the number of times of writing a ferroelectric material is 10 10 (10 ¹⁰ ) to 12 (10 ¹² ) at most. Therefore, it is difficult to ensure reliability during mass production under the above conditions. Furthermore, when using a non-volatile element, the test is generally complicated and time-consuming, which may cause a problem of increased test cost. In the dynamic method, an increase in power due to refresh is a problem. The above document shows that the threshold voltage of a field effect transistor connected to a capacitor is increased. However, in a normal field effect transistor, even if the threshold voltage is increased, the junction leakage current cannot be ignored. Although it depends on the design, in the worst case where the variation of elements and temperature conditions are combined, the retention time may be about 10 to 100 microseconds. In this case, power consumed by refresh during the standby time becomes a problem.

  As described above, the conventional latch circuit in the switch cutoff method has various problems such as power consumption for holding information and a limit on the number of times of writing.

  Furthermore, no consideration has been given to how to deal with a failure in the information holding mechanism of the latch circuit. In the conventional example, studies aimed at reducing leakage current for the purpose of reducing standby current have been made, but in the future, the amount of DC current associated with leakage will not be negligible with respect to AC current during operation. It is also expected to become. Therefore, this also needs to be considered.

  In order to solve the above problems, the present invention uses the following means.

  The essence of the present invention includes a logic circuit and a latch circuit, and the latch circuit includes a first field effect transistor having an average thickness of a channel portion of 5 nm or less. A semiconductor integrated circuit.

  More specifically, a logic circuit having a plurality of logic gates and a plurality of latch circuits connected to the logic gates, a plurality of latch circuits connected to the logic gates, the first latch circuit, and A power switch for controlling power supply to each of the plurality of logic gates, and the plurality of latch circuits can hold a state of the first latch circuit and the first latch circuit. And the second latch circuit capable of holding the state signal of the first latch circuit has a field effect transistor having an average thickness of the channel region of 5 nm or less. It can be called a circuit.

The characteristics are explained in detail as follows. First, the latch circuit portion is composed of a normal static latch circuit and a dynamic latch circuit as information holding means. The latter dynamic latch circuit is composed of a first field effect transistor composed of a polycrystalline thin film having a channel region of about 5 nm or less, and a CMOS inverter having the first transistor connected to the input terminal. . When the power is shut off, latch information is held as a charge in the gate capacitor of the CMOS inverter, that is, the second field effect transistor, the first field effect transistor is turned off, and the CMOS inverter shuts off the power. . Since the first field effect transistor has a very thin channel portion, the leakage current can be extremely reduced to about 10 ¹⁹ (10 ⁻¹⁹ ) ampere. Even if temperature and variation are taken into account, it can be as low as 10 minus 16 (10 ⁻¹⁶ ) amperes. For this reason, the problem of retention in the conventional dynamic method can be avoided. Further, since the information holding portion is disconnected from the power source, there is no leakage and the problem of the number of rewrites does not occur unlike the nonvolatile element.

  Further, when a defect is found in the information holding means during the test, a means is provided for keeping the static latch circuit portion of the corresponding latch circuit and the power switch of the logic circuit connected thereto conductive. . Thereby, even if a defect exists in the information holding means of a small number of latches inside the semiconductor integrated circuit, the semiconductor integrated circuit does not have to be discarded as a defective product. Therefore, the yield can be improved. At this time, the leakage current increases according to the number of power interruptions, but there is no problem if the defect rate of the information holding means is low. Furthermore, a power switch is provided for each circuit block constituting the semiconductor integrated circuit, and even when the entire semiconductor integrated circuit is in operation, it is possible to turn off the power switch and hold the information in the latch for the unused circuit block. Become. As a result, the current during operation of the semiconductor integrated circuit can be reduced.

  In the present invention, when the power of the circuit block that is not used in the standby state or the operating state of the semiconductor integrated circuit is reduced by the leakage current, the data of the latch circuit can be held at the same time.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit configuration diagram showing a basic configuration of an embodiment of a semiconductor integrated circuit to which the present invention is applied. FIG. 1 shows a latch circuit LCKT and a CMOS circuit CCKT, which are basic elements of a semiconductor integrated circuit. An actual semiconductor integrated circuit is composed of circuit blocks (cores or macros) divided for each function, and each circuit block includes a large number of CMOS circuits and latch circuits, which will be described here. For simplicity, one CMOS circuit and one latch circuit are shown in one circuit block. In the following description, the CMOS circuit is assumed to be a general logic circuit, but it goes without saying that it may be a memory peripheral circuit such as a decoder or an arithmetic circuit.

  The power supply control unit PCU is means for cutting off a leak current flowing from the power supply Vdd to the circuit block when the circuit block is in an unused state (standby state). The output VddI of the power supply control unit PCU is connected to the power supply terminals of the latch circuit LCKT and the CMOS circuit CCKT (hereinafter, VddI is referred to as an internal power supply for convenience).

  The latch circuit LCKT and the CMOS circuit CCKT operate in synchronization with the clock signal CLK. The input signal of the latch circuit is indicated as D output signal, that is, the input signal of the CMOS circuit is indicated as Q, and the output signal of the CMOS circuit is indicated as OUT. The latch control signal φL is a signal for controlling the latch circuit LCKT. As in the embodiments described later, the latch control signal φL may be composed of a reset signal and other signals.

  The latch circuit LCKT of the present invention is composed of a static latch circuit SL and a dynamic latch circuit DL that are normally used. In the specification of the present application, the circuit referred to as the first latch circuit corresponds to a normally used static latch circuit described here, while the second latch capable of holding the state of the first latch circuit. The latch circuit referred to as a latch circuit corresponds to the dynamic latch circuit described here. The dynamic latch circuit extracts internal state information of the latch circuit from a desired intermediate node of the static type latch circuit, and is input to the dynamic latch circuit.

  The dynamic latch DL is a means for holding the state of the static latch SL when the power is cut off, and a field effect transistor TR1 having a thin film channel whose channel portion is about 5 nm or less, and a CMOS inverter circuit INVD in which the transistor TR1 is connected to an input terminal Consists of. It should be noted that the field effect transistor TR1 having the thin film channel is shown by increasing the thickness of a part of the line of the transistor symbol so that it can be easily distinguished from a normal field effect transistor on the drawing.

  Here, the channel portion of a field effect transistor having a thin film channel has an average thickness of about 5 nm or less. In addition, the thickness of the channel region of the transistor is a problem. From this point of view, it can be said that the average channel height is 5 nm or less. Furthermore, it can be said that the channel region of the transistor is composed of a plurality of semiconductor crystal grains having a minor axis of 5 nm or less, that is, a polycrystalline thin film (usually a silicon polycrystalline thin film). This transistor uses a quantum mechanical carrier confinement effect. From this viewpoint, the channel thickness is preferably 5 nm or less. Further, this thickness is more preferably about 2 nm than 2.5 nm.

  When the power is shut off, the static latch information is held as charges in the gate capacitor portion of the CMOS inverter, and the field effect transistor TRI is turned off. Since the field effect transistor has an extremely thin channel portion, the leakage current at the time of off can be reduced by several orders of magnitude or more than a normal logic transistor. For this reason, the problem of retention in the conventional dynamic method can be avoided. Further, since the information holding part is disconnected from the power source, there is no leakage. Further, the problem of the number of rewrites does not occur unlike a nonvolatile element.

  Examples of specific circuit configurations of the power supply control unit PCU and the latch circuit LCKT shown in FIG. 1 will be described below with reference to FIGS. FIG. 2 shows an embodiment in which a power switch composed of a field effect transistor is applied to a power control unit PCU. The power supply control unit PCU is configured by using a switch of pMOS (reference numeral P in the figure) having a high threshold voltage. When the power switch control signal / φPW is set to a low potential, the field effect transistor P is turned on, and the power supply VddI of the latch circuit L and the CMOS circuit CCKT is connected to the power supply Vdd. On the other hand, when the power switch control signal / φPW is set to a high potential, the field effect transistor P is turned off, the power supply VddI of the latch circuit L and the CMOS circuit CCKT is disconnected from the power supply Vdd, and the leakage current is cut off. In this embodiment, the power switch is provided on the power supply Vdd side, but it is needless to say that it may be provided on the ground power supply Vss side. In that case, since the power switch can be configured by an n-type field effect transistor having a current driving capability than the p-type field effect transistor, there is an advantage that the occupied area can be further reduced. A power switch based on the SCCMOS method can also be used. In that case, it is possible to operate at a lower voltage than in the case of using a field effect transistor having a high threshold voltage. Although one power switch is collectively provided for one circuit block here, it is of course possible to provide a plurality of switches for the circuit block for reasons such as circuit arrangement on the semiconductor chip. When the switch is divided into a plurality of parts, the degree of freedom of circuit arrangement (so-called layout) increases, and as a result, the occupied area may decrease. When a plurality of power switches are provided, the size of the field effect transistor used for the power switch may be optimized depending on the circuit scale to which the power switch is connected.

  FIG. 3A is an embodiment showing a specific circuit configuration of the latch circuit L. FIG. In the following description, in the present invention, a transfer gate in which a p-type field effect transistor and an n-type field effect transistor are connected in parallel is indicated by a symbol as shown in FIG. . The input signal written beside the symbol indicates that the transfer gate becomes conductive when the polarity of the signal becomes a high potential. In the embodiment of FIG. 3A, in the inverter INV1, NAND circuit NAND2, etc., the connection from the power sources VddI and Vss is shown in the inverter and NAND circuit symbols. This will be used below as a notation for clearly indicating the power supply to which these circuits are connected. Similarly, for the NAND circuit NAND1 and the inverter INV2, transistors M1 and M2 and a capacitor C are connected to a circuit symbol. This indicates that transistors and capacitors are connected to the power supply in these circuits. In the following, the signal names with / without (for example, / φ2 and φ2) for the same signal name are the relationship in which the potential is inverted (for example, if / φ2 is low potential, φ2 is high potential). It shall be shown that

  In the embodiment of FIG. 3, the static latch SL is a latch circuit that operates in synchronization with the clock CLK. / RST is a reset signal. When / RST becomes a low potential, the output Q of the latch circuit L is fixed to a high potential, and the internal potential of the latch circuit is also fixed to a constant value. The static latch SL has a function in which a signal input from the input terminal D is sequentially transferred and output through the transfer gates TG1 and TG2 along with the transition of CLK. First, the outline of the operation of the static latch will be described, and then the operation of the dynamic latch DL, which is a feature of the present invention, will be described using the timing chart of FIG. The operation of the static latch portion is as follows.

  When the reset signal / RST is at a high potential, the input signal φ2 of the field effect transistor connected to NAND1 is at a low potential (/ φ2 is a high potential), and / φPW is at a low potential, a normal operation state is obtained. When the clock CLK becomes a low potential, the potential of the input terminal D is input to the inverter INV1. Subsequently, when the clock CLK becomes a high potential, the transfer gate TG1 is closed and TG2 and TG3 are opened. As a result, the previously input signal is latched by a circuit loop constituted by the inverter INV1 and the NAND circuit NAND2. The input signal is input to the NAND circuit NAND1 through the transfer gate TG3 and output from the output Q. At this time, since the signal passes through the inverter INV1 and the NAND circuit NAND1, the polarity of the signal is restored. Subsequently, when the clock CLK becomes a low potential again, the previous input signal output to the output Q by the NAND circuit NAND1 and the inverter circuit INV2 is latched. Subsequently, a new input signal is input from the input terminal D to the inverter INV1. Since the power supply terminals of the inverter and NAND circuit constituting the static latch circuit are connected to the internal power supply VDDI, information cannot be retained when the power switch is turned off and the current from the power supply Vdd is cut off. The dynamic latch DL holds information on the static latch when the power switch is shut off. The operation will be described below with reference to the timing chart of FIG.

  The sign of each signal in FIG. 4 is as described above. 4 indicates that the circuit block to which the latch circuit belongs is in use (operating state). During this period, the power switch is turned on (power ON) and the clock CLK is input. When the circuit block is in an unused state (standby state), first, the clock CLK is stopped and the signal φ1 is raised. When φ1 rises, the transistor TR1 in the dynamic latch DL in FIG. 3 becomes conductive, and the potential of the output of the inverter INV2 inside the static latch becomes equal to the potential of the gate capacitance of the inverter INVD inside the dynamic latch (SET). Subsequently, when the signal φ1 is set to a low potential, the potential is stored in the gate capacitance.

  Here, as will be described later, the transistor TR1 is not a normal field effect transistor but a transistor having a channel formed of a polycrystalline thin film of 5 nm or less. Therefore, there is almost no leakage current, and the stored charge can be held for a long time. Next, when the signal / φPW is set to a high potential, the power switch is turned off, and the leakage current of the latch circuit and the logic circuit is cut off. In the above description, the signal φ1 is raised after the circuit block enters the standby state, and writing to the dynamic latch DL is performed. This is because, when the signal φ1 is raised, the load capacity of the signal path of the static latch is increased by the input capacity of the inverter INVD of the dynamic latch to avoid affecting the operation speed. When the effect of the load capacity does not become a problem, such as when the operation speed is slow, keep φ1 at a high potential in the operating state, and when the writing to the dynamic latch is completed in the standby state, the low potential is You may control to do. in this case. Since writing to the dynamic latch is started simultaneously with the stop of the clock, the time until the power switch is cut off may be shortened.

  Next, an operation when the unused state (standby state) of the circuit block ends and the power is turned on again will be described. As shown in FIG. 4, when / φPW is lowered and the power switch is turned on, the reset signal / RST of the static latch SL is lowered. This is because if a power supply is turned on while the potential of the input terminal of the circuit inside the static latch or the output boy of the static latch is in a floating state, a large through current may flow through the circuit or logic circuit inside the static latch. Subsequently, the signal φ2 is raised and the information held in the dynamic latch DL is written back to the static latch. As can be seen from FIG. 3, when φ2 is raised, the NAND circuit NAND1 is disconnected from the internal power supply VddI, and the transfer gate TG5 in the dynamic latch DL becomes conductive. As a result, the potential of the input terminal of the inverter INV2 of the static latch is set through the output line O of the dynamic latch by the inverter INVD. As a result, the information held in the dynamic latch is written back to the static latch (SET). Subsequently, after the φ2 is lowered, the clock CLK is input to shift to a normal operation state.

  As described above, in this embodiment, since information is held in the dynamic latch by a transistor with little leakage, there is no need for refresh when the standby time is not particularly long. For this reason, the current consumption during standby of the circuit block can be made very small as compared with the conventional dynamic method requiring frequent refresh operation and the balloon latch method that consumes leakage current during standby.

  In some cases, the waiting time of the circuit block is long and the retention time of the dynamic latch is exceeded (that is, when the potential of the input part of the inverter INVD changes gradually and may exceed the logic threshold). There can be. In that case, the contents of the dynamic latch can be easily refreshed by the method described below. The simplest method is to restore the entire circuit block from the standby state to the operating state with the clock signal CLK fixed at a low potential, return the data from the dynamic latch to the static latch, and then dynamically change the data again. It is a method of writing back to the latch. The timing chart at that time is the same as FIG.

  In the above-described embodiment, the power supply of the entire circuit block is restored. However, only the power of the latch circuit needs to be restored for refreshing. It is also possible to perform refresh by turning on only the power switch. In this case, power consumption can be reduced as described above. In order to further reduce the power, a power switch for the inverters INV2 and INVD can be provided separately from the power switches of the remaining circuits, and only the inverters INV2 and INVD can be operated for refresh. As can be easily seen from the circuit diagram of FIG. 3, the signal φ2 is set to a high potential, the power switches of the inverters INV2 and INVD are turned on, and then the signal φ1 is set to a high potential. As a result, the information of the dynamic latch is refreshed by the loop of the inverters INV2 and INVD. In this case, since only two inverters are operated, power consumption is further reduced. In any case, since the leakage current of the transistor TR1 is very small, the frequency of the refresh operation as described above is low, and the accompanying increase in power is very small.

  In the embodiment shown in FIGS. 3 and 4, after the circuit block shifts from the operating state to the standby state, first, after writing data into the dynamic latch by the signal φ1, / φPW is raised to turn off the power switch. It was. Since the transistor TR1 is a field effect transistor having a thin channel portion, the on-current value is relatively small as compared to a normal field effect transistor. For this reason, in some cases, the writing time becomes longer, and there is a possibility that the time until the power switch is turned off becomes longer. In that case, since the time until the leakage current of the circuit is cut off becomes long, the power consumption reduction rate is reduced.

  In such a case, the embodiments shown in FIGS. 5 and 6 are effective. FIG. 5 is a circuit diagram showing an example of this power supply control circuit, and FIG. 6 is a timing chart in this example.

  In this embodiment, the power supply can be shut off simultaneously with the rise of φ1 (start of writing to the dynamic latch). In this embodiment, the power switch is separated into two as shown in FIG. In the figure, a p-type field effect transistor P2 and an internal power supply VddI2 are for a NAND circuit NAND1 and an inverter INV2, and pMOS (P1) and VddI1 are for other circuits. A capacitor CI2 is connected to the terminal of VddI2. The remaining circuits are the same as in the embodiment of FIG. The operation of this embodiment is shown in FIG. FIG. 6 shows only the transition from the operating state (ACT) to the standby state (other parts are the same as in the embodiment of FIG. 4 and are omitted). As described above, in this embodiment, the signal φ1 is raised and at the same time the power switch control signal / φPW is raised to turn off both the power switches P1 and P2. As can be easily seen from FIG. 3, the inverter INV2 must operate to write to the dynamic latch DL, and the NAND circuit NAND1 must not operate to maintain the potential of the input signal. Must not. In the circuit of FIG. 5, the power switch P2 is turned off, but since there is a capacitor CI2, these circuits can be operated for a while by the electric charge stored in the capacitor. Note that the capacitance value of the capacitor CI2 should be set sufficiently large compared to the load capacitance of the inverter INV2 and NAND circuit NAND1 including the input capacitance of the dynamic latch, so that the power supply voltage drop during operation does not become a problem. Of course.

  As described above, in the embodiment shown in FIGS. 5 and 6, the power supply can be shut off immediately after the clock is stopped, so that the leakage current can be effectively reduced. It is also possible to configure the power switch so that both the power switch separation as shown in FIG. 5 and the power switch separation for the refresh operation are performed. Such a configuration and a method for generating a power switch control signal necessary for the configuration can be easily designed by the integrated circuit designer from the above description, and the details are omitted.

  7 and 8 are schematic cross-sectional views showing examples of the transistor TR1 in the dynamic latch DL. In the embodiment shown in FIG. 7, the transistor TR1 is planarly formed on the element isolation region ISO formed in the semiconductor substrate SUB. In this example, CH is a channel portion formed of a thin film having a thickness of about 5 nm or less, OX is an insulating film, G2 is a gate electrode of the transistor TR1, S2 is a source electrode, and I is an input terminal of the dynamic latch DL. This input terminal naturally corresponds to the drain of the transistor TR1. In this example, the transistor TR1 is planarly formed on the substrate in the same manner as a normal transistor. For this reason, there is no large level difference between where the transistor TR1 is formed and where it is not. Therefore, there is an advantage that steps such as wiring and contact for connecting the transistor TR1 and a normal transistor are facilitated.

  FIG. 8 is a schematic cross-sectional view showing an example of a structure for realizing dynamic latches with high integration. In this example, the planar structure is particularly effective when an increase in area becomes a problem. In this example, a transistor TR1 having a vertical structure is formed in a hole opened on the gate electrode of the n-channel transistor nT1 constituting the inverter INVD in the dynamic latch DL in FIG. In the figure, G1 and G2 are the gate electrodes of the n-channel transistor nT1 and transistor TR1 constituting the inverter INVD, respectively, and S1 and D1 are the source electrode and the drain electrode of the transistor nT1, respectively. CH is a channel portion of the transistor TR1, and is formed of a thin film having a thickness of about 5 nm or less. The gate electrode has a cylindrical shape, and the oxide film OX and the channel portion CH surround the periphery of the gate electrode. I is an input terminal of the dynamic latch DL.

7 and 8, the channel portion CH becomes conductive when the potential of the gate electrode G2 becomes high, and becomes non-conductive when the potential becomes low. Since the thickness of the channel CH is very thin, about 5 nm or less, the leakage current at the time of off can be extremely reduced as compared with a normal transistor. The leakage current at the time of turning off the normal transistor is about 10 ⁻¹⁰ (10 ⁻¹⁰ ) to about 10 ⁻¹² (10 ⁻¹² ) ampere, whereas the channel is 5 nm as in this embodiment. For a thin film transistor having a thickness of about 10 or less, it can be set to 10 to the power of minus 19 (10 ⁻¹⁹ ). As for the field effect transistor itself having a thin film channel having such a structure, for example, the inventions entitled Semiconductor Device and Semiconductor Integrated Circuit, Japanese Patent Laid-Open No. 2000-269457 (Patent Document 4), and Japanese Patent Laid-Open No. 2002-2002. No. 94029 (Patent Document 5). According to this embodiment, since the leakage current of the transistor TR1 is very small, the information held in the gate capacitance of the inverter INVD in the dynamic latch DL can be held for a long time.

Since the amount of charge that can be stored in the gate electrode of the inverter INVD is on the order of about 10 to the 15th power (10 ⁻¹⁵ ) C (Coulomb), the leakage current of TR1 is 10 to the 19th power (10 ⁻¹⁹ ). Assuming that 10% of the charge leaks is about 1000 seconds. Considering the variation in leakage current of the transistor TR1 and the operation at a high temperature, the guaranteed value in design is smaller, for example, it may be necessary to make it about 10 minus 16 (10 ⁻¹⁶ ). However, in normal applications, if the latch information can be held for about 1 second after the power switch is cut off, the leakage current reducing effect is often sufficiently obtained. Therefore, it can be said that the capability of the transistor of this embodiment is a sufficient value. Of course, if it is necessary to hold for a long time exceeding the holding performance of the dynamic latch, the information of the dynamic latch may be rewritten (refreshed). The specific method is as described above. As described above, according to the embodiment shown in FIGS. 7 and 8, the holding performance of the dynamic latch can be made sufficiently long. Further, since the transistor has a thin film channel, there is no limit on the number of times of writing unlike the conventional example using a ferroelectric. Of course, the oxide film thickness of the transistors constituting the inverter INVD in the above embodiment is set to such a thickness that the gate leakage current can be ignored.

  So far, the outline of the present invention and the configuration and operation of the dynamic latch have been described. Next, specific examples when the present invention is applied to a large-scale integrated circuit will be described.

  As described above, in the semiconductor integrated circuit, the problem of the leakage current of the field effect transistor has become obvious. In the future, this problem will become serious not only during standby but also during operation. That is, the DC current associated with the leakage is not negligible with respect to the AC current during operation. The embodiment of FIG. 9 is an embodiment that can reduce the leakage current not only during standby but also during operation using the present invention. In this embodiment, the present invention is applied to a semiconductor integrated circuit in which a CPU core, a DSP core, various logic cores, a memory core, and the like are integrated on one chip. In this embodiment, not only a semiconductor integrated circuit in a single chip form, but also a system or board on which a plurality of chips are mounted, or a semiconductor integrated form in a so-called multichip package in which a plurality of chips are integrated in one package. It can also be applied to circuits and combinations thereof. An example of mounting such a plurality of chips will be described below based on the form of one chip as shown in FIG. 9 for simplicity.

  The semiconductor chip CHIP shown in FIG. 9 is composed of a plurality of circuit blocks. The main circuit blocks are CPU core CPU, DSP core DSP, instruction cache IC, data cache DC, XY memory XY-M, secondary cache 2ND-C, direct memory access control circuit DMAC, peripheral IP core PER-IP, bus control Includes circuit BC. Further, the task ID register TID-R is a register inside the CPU core and is a register for managing each task, and the resource management register RM-R is a register for managing a resource (core) to be used. . In addition, a power control unit PCU is provided for each resource (circuit block) as a unit for performing power control, and the state decoder ST-DEC controls the state signal φST to use or not use each resource (circuit block). Send to unit PCU. I-BUS, D-BUS, P-BUS1, and P-BUS2 are an instruction bus, a data bus, a first peripheral bus, and a second peripheral bus, respectively.

  Among the components shown in FIG. 9, various cores including CPU cores, memories, buses, etc. are basic circuit blocks constituting a chip for digital processing, and each has basic functions. It is. Hereinafter, a functional unit circuit block such as a core and a memory is referred to as a component. Since operations of these components are sufficient, a description of the functions is omitted here.

  In this embodiment, the leakage current is reduced by shutting off the power switch for unused parts during the operation of the semiconductor integrated circuit. First, based on the contents of the task ID register TID-R in the CPU core and the resource management register RM-R that manages the resources (parts) to be used, the state decoder ST-DEC is used for each part. A state signal φST indicating whether or not to perform is transmitted. In each component, the power control unit PCU detects whether or not the component is used by the state signal φST. When the unused state is entered, the latch information is stored in the dynamic latch and the power switch is shut off. When returning to the use state, the dynamic latch information is written back and the power switch is turned on. These operations can be easily performed by applying the embodiment shown in FIGS. As a result, it is possible to hold the latch information while shutting off leakage currents of parts not used during standby as well as during operation. Thus, also in this example, the current consumption can be greatly reduced. It should be noted that if the generation of the state signal φST from the state decoder ST-DEC is delayed, there may be a problem that a reduction in the power reduction effect and a delay in the operation return when shifting to the standby state become problems. In particular, when returning to the operating state, it is necessary to prepare for returning the latch information before the switch is turned on. Furthermore, if the circuit scale of the component is large, there may be a case where some waiting time (preheating time) is required until the switch becomes stable even after the switch is turned on. In such a case, as necessary, the contents of the task ID register TID-R and the resource management register RM-R are prefetched to predict the next state transition and start necessary operations. Is effective. In that case, power for preparation is wasted if the prediction is lost, but it becomes possible to avoid the problem of the delay of the operation except in the case where the prediction is impossible such as an interrupt.

  In the configuration of FIG. 8, the power control unit PCU is not added to the power control unit CPU core and its primary cache, ie, the data cache DC and the instruction cache IC. This is because there is not much time during which these power supplies can be shut off during operation. It is possible not to add the power control unit PCU for other parts that have a short power-off period.

  FIG. 10 is an embodiment showing an example of a change in the task and the power switch control signal / φPWi in the embodiment of FIG. In this embodiment, the number of parts to be controlled by the leakage current is n, and the power switch control signals are indicated by / φPW1 to / φPWn. A, B,..., F in the horizontal column indicate the tasks of the power control unit CPU, and the components to be used differ depending on the task, and the power switch is controlled accordingly. In this example, when the component is used, the power switch control signal / φPWi is “L” (low level) and the power switch is turned on. When the component is not used, the power switch control signal / φPWi is “H” (high level) indicates that the power switch is shut off. For example, the part 1 is used in tasks A to C and F, and is not used in tasks D to E. Therefore, in the tasks D and E, the component 1 cuts off the power switch to reduce the leakage current. As described above, according to the embodiment shown in FIG. 9 and FIG. 10, it is possible to reduce the leakage during operation by shutting off the power switch of the component using the management of the task of the CPU. As described above, since the embodiment shown in FIGS. 1 to 8 is applied to the control of the power switch and the latch circuit, the power switch can be shut off without losing the latch information. Accordingly, since the result when one task is completed is stored, the result can be used by another task. As a result, the power switch can be shut off at the end of the task regardless of the processing contents of the task, so that the current during operation can be effectively reduced.

  FIG. 11 is an embodiment showing a configuration of a latch circuit for easily performing a test in a semiconductor chip to which the present invention is applied. In the latch circuit L, a selector SEL, a static latch circuit SL and a dynamic latch circuit DL connected thereto are arranged. The static latch circuit SL and the dynamic latch circuit DL are connected as described above. In the figure, D1 is input data, D2 is test scan path data, φS is a signal, Q is an output signal of the latch circuit, that is, an input signal of a circuit connected to the latch circuit.

  In this embodiment, by switching the signal φS, the selector SEL provided in the latch circuit L can select either the input data D1 or the test scan path data D2. As a result, even in a semiconductor chip to which the present invention is applied, it is possible to easily configure a scan path used in a normal logic circuit test. Therefore, it is possible to increase the reliability while reducing both the leakage current and the retention of information, which are the features of the present invention.

  7 and 8, as an example of the transistor TR1 in the dynamic latch DL, the channel portion formed of a thin film has been described. As already described, since such a transistor has a small leakage current, the information retention characteristic of the dynamic latch DL is improved. However, since the structure is special, in some cases, the yield of the semiconductor chip may be reduced due to the failure of the transistor. An embodiment effective in such a case will be described below.

  As a result of the test, when the dynamic latch DL is found to be defective, the simplest countermeasure is to provide the dynamic latch DL redundantly. In other words, if a defect is detected as a result of the test, it may be switched to the spare dynamic latch DL. Since there is little probability that two dynamic latches will fail simultaneously, the yield is improved by providing redundant dynamic latches. When a spare for the dynamic latch DL is prepared, an increase in area due to this may be a problem. In that case, it is possible to redundantly provide only the transistor TR1. In that case, the increase in the area is smaller than the provision of a spare for the entire dynamic latch portion. In order to completely eliminate the deterioration of retention caused by the defective transistor TR1 having a large leak, a current path can be physically cut off by providing a fuse between the inverter INVD for storing information and the defective transistor TR1. It is necessary to provide means.

  Although it is effective to use a spare circuit as described above, there are cases in which an adverse effect such as an increase in area or a long test time for switching a defective portion during a test may occur. Examples effective in such a case are shown in FIGS.

  The embodiment shown in FIGS. 12 and 13 is an embodiment that is effective when a power supply control unit is provided for each component as in the example of FIG. In this embodiment, when a dynamic latch failure caused by the transistor TR1 or the like is detected, the power switch of the component is not shut off.

  As shown in FIG. 12, in this embodiment, the power switch PWU is controlled by the logical product (AND) of the switch enable signal φSWE-i and the power control signal / φPW-i. The signal letter i indicates that the signal is for the component i. If φSWE-i is high potential, power switch PWU is controlled by power control signal / φPW-i (/ φPW-i is low potential and switch on, high potential off), and φSWE-i is low potential , / ΦPW-i, the power switch PWU is turned on. Therefore, when a failure is detected, the power supply of the component i is always in a conductive state if the switch enable signal φSWE-i in that component is fixed at a low potential. When such control is performed, it may be safer to electrically isolate the two so that the defective dynamic latch DL does not adversely affect the operation of the static latch SL.

  In such a case, the embodiment of FIG. 13 can be used. In this embodiment, the dynamic latch DL and the static latch SL can be electrically separated by the transfer gates TGI and TGO when the switch enable signal φSWE-i is at a low potential (that is, when the dynamic latch is defective). it can. Note that, when disconnected, the gate voltage of the inverter INV3 becomes indefinite, and in some cases, a through current may flow. In order to avoid this, as shown in the figure, a p-type field effect transistor P-INV3 is provided between the power supply VddI and the inverter INV3, and a reverse phase signal / φSWE of the switch enable signal φSWE-i is provided at its gate electrode. It is effective to disconnect INV3 from the power supply VddI by inputting -i. If a defect is found in the φ dynamic latch and the power switch is kept conductive, the signal φ2 must also be fixed at a low potential so that the NAND circuit NAND1 in the static latch does not stop. Of course.

  12 and 13 described above, even if a failure is found in a dynamic latch inside a certain component, the operation of the entire semiconductor chip does not become defective. Of course, the leak current from the power source cannot be cut off in the part where the defect is found. However, in the case of being composed of a plurality of parts as shown in FIG. 9, if the number of defective parts relative to the number of parts is small, the increase in leakage current is small, which is not a problem. Rather, the effect of improving productivity by improving the yield is great.

  FIG. 14 shows another embodiment for improving the yield. In this embodiment, the transistor TR1 of the dynamic latch circuit DL is composed of two transistors TRA and TRB in series. I is input and O is output. Other configurations are the same as in the example of FIG. According to this embodiment, even if the leakage current of one of the transistors is larger than expected due to process variations or the like, the transistors are connected in series, so that the deterioration of retention can be prevented. As a result, even if the failure rate of the transistor TR1 is high, the failure rate of the dynamic latch can be suppressed.

  Of course, the embodiment of FIG. 14 and the embodiments of FIGS. 12 and 13 can be used in combination. In this case, since the failure rate of the dynamic latch is kept low by the embodiment of FIG. 14, the number of parts for stopping the switch control is reduced, and the yield is further increased.

As mentioned above, although embodiment of this invention was described, the main forms of this invention are enumerated.
(1) A semiconductor integrated circuit having a logic circuit and a latch circuit, wherein the latch circuit includes a first field effect transistor having a channel portion thickness of 5 nm or less.
(2) In the semiconductor integrated circuit according to the item (1), the latch circuit includes a first capacitor element and a write transistor that writes a charge to the first capacitor element, and the write transistor includes: A semiconductor integrated circuit comprising the first field effect transistor.
(3) The semiconductor integrated circuit according to the above item (2), wherein the first capacitor element includes a gate capacitor of a second field effect transistor.
(4) In the semiconductor integrated circuit according to any one of the items (1) to (3), the semiconductor integrated circuit includes at least one switch that controls supply of current from a power source to the logic circuit and the latch circuit. The semiconductor integrated circuit is characterized in that when the switch is turned off, the internal state of the logic circuit is held as a charge stored in the first capacitor element.
(5) The semiconductor integrated circuit according to item (4), wherein the switch includes a second capacitor element at one terminal thereof.
(6) In the semiconductor integrated circuit according to any one of items (1) to (5), the semiconductor integrated circuit includes a plurality of circuit blocks, and the circuit block includes a logic circuit, a latch circuit, and a power supply. At least one switch for controlling supply of current to the logic circuit and the latch circuit is provided. The switch is controlled to be turned on and off by a switch control signal. When the circuit block is in use, the switch is turned on and unused. A semiconductor integrated circuit which is controlled to be turned off when in the state.
(7) The semiconductor integrated circuit according to the item (6), further comprising means for allowing the switch to be always turned on regardless of the switch control signal.
(8) In the semiconductor integrated circuit according to item (6), when the logic circuit shifts from a use state to an unused state, the latch circuit holds the internal state of the logic circuit and the switch When the logic circuit shifts from the unused state to the used state, the switch is turned on and the internal state held in the dynamic latch circuit is changed to the logic state before the logic circuit is used. A semiconductor integrated circuit characterized by being written back to a circuit.
(9) The semiconductor integrated circuit according to item (6), wherein the semiconductor integrated circuit includes a processor, and the switch control signal is generated in synchronization with task switching of the processor. Integrated circuit.

FIG. 1 is a circuit configuration diagram of an embodiment showing a configuration of a semiconductor integrated circuit according to the present invention. FIG. 2 is a circuit configuration diagram showing an embodiment of the power supply control unit PCU. FIG. 3 is a circuit configuration diagram showing an embodiment of the static latch SL and the dynamic latch DL. FIG. 4 is a diagram showing an example of a timing chart of the embodiment of FIG. FIG. 5 is a circuit configuration diagram showing an embodiment of a power switch for turning off the power switch simultaneously with the start of writing to the dynamic latch DL in the embodiment of FIG. FIG. 6 is a diagram showing an example of a timing chart of the embodiment of FIG. FIG. 7 is a cross-sectional view of the main part of the device showing an embodiment of the structure of the transistor TR1 in the dynamic latch DL. FIG. 8 is a cross-sectional view of the main part of the device showing another embodiment of the structure of the transistor TR1 in the dynamic latch DL. FIG. 9 is a block diagram showing an embodiment when the present invention is applied to a semiconductor integrated circuit composed of a plurality of logical cores (components). FIG. 10 is a diagram illustrating an example of a relationship between a switch control signal and a task. FIG. 11 is a block diagram showing an embodiment in which a scan path for testing is provided. FIG. 12 is a circuit configuration diagram showing an embodiment in which the power supply is not shut down by the switch control signal in a component having a defective holding characteristic of the dynamic latch DL. FIG. 13 is a circuit configuration diagram showing an embodiment for electrically separating the dynamic latch DL from the static latch SL in a component having a defective dynamic latch DL. FIG. 5 is a circuit configuration diagram showing an embodiment in which two transistors TR1 are connected in series in the dynamic latch DL.

Explanation of symbols

Vdd, VddI ... (high potential) power supply, Vss ... (low potential) power supply, PCU ... power supply control unit, SL ... static latch, DL ... dynamic latch, RSC ... restore circuit , LCKT ... Latch circuit, CCKT ... CMOS circuit, TG0, TG1, TG2, TG3, TG4 ... Transfer gate, NAND1, NAND2 ... NAND circuit, INV1, INV2, INVD ... Inverter, TR1 ... Transistor I in dynamic latch DL ... Input terminal of dynamic latch DL, CH ... Channel part, OX ... Oxide film, ISO ... Element isolation region, G1 ... n-channel transistor nT1 Gate electrode, S1 ... source electrode of n-channel transistor nT1, D1 ... drain electrode of n-channel transistor nT1, G2 ... gate electrode of transistor TR1, S2 ... source electrode of transistor TR1, P- INVD ・ ・ ・ p-type field effect transistor , ΦPW, / φPW, / φPW-1, φPW-2, / φPW-i, / φPW-n ... Power control signal, φSWE-I, / φSWE-i ... Switch enable signal, φL ... Latch control signal, CLK, / CLK ... clock signal, / RST ... reset signal, CHIP ... semiconductor chip, CPU ... CPU core, DSP ... DSP core, IC ... instruction cache, DC ... Data cache, XY-M ... XY memory, 2ND-C ... Secondary cache, DMAC ... Direct memory access control circuit, PER-IP ... Peripheral IP core, BC ... Bus control circuit, TID-R ... Task ID register, RM-R ... Resource management register, ST-DEC ... State decoder, PCU ... Power control unit, I-BUS ... Instruction Bus, D-BUS ... Data bus, P-BUS1 ... First peripheral bus, P-BUS2 ... Second peripheral bus. The signal name / indicates a reverse phase signal.

Claims (12)

A logic circuit and a latch circuit;
The latch circuit includes a first field effect transistor having an average thickness of a channel portion of 5 nm or less. A logic circuit having a plurality of logic gates and a plurality of latch circuits connected to the logic gates;
A plurality of latch circuits connected to the logic gate; the first latch circuit; and a power switch for controlling power supply to each of the plurality of logic gates; and A latch circuit and a second latch circuit capable of holding the state of the first latch circuit;
The second latch circuit capable of holding the state signal of the first latch circuit has a field effect transistor having an average thickness of a channel region of 5 nm or less. 3. The semiconductor integrated circuit according to claim 2, wherein the channel of the field effect transistor included in the second latch circuit is made of a plurality of semiconductor crystal grains having an average height of 5 nm or less. 3. The semiconductor integrated circuit according to claim 2, wherein the channel of the field effect transistor included in the second latch circuit is made of a plurality of semiconductor crystal grains having an average minor axis of 5 nm or less. The latch circuit includes a first capacitor element and a write transistor that writes electric charge to the first capacitor element, and the write transistor includes the field effect transistor having an average channel region thickness of 5 nm or less. The semiconductor integrated circuit according to claim 2, wherein: 4. The semiconductor integrated circuit according to claim 3, wherein the first capacitor element includes a gate capacitor of a second field effect transistor to which the semiconductor integrated circuit is connected to an input terminal. The semiconductor integrated circuit includes at least one switch that controls supply of current from a power source to the logic circuit and the latch circuit. When the switch is turned off, the internal state of the logic circuit is The semiconductor integrated circuit according to claim 2, wherein the semiconductor integrated circuit is held as a charge stored in the first capacitor element. 8. The semiconductor integrated circuit according to claim 7, wherein the switch has a second capacitor element at one terminal thereof. A plurality of circuit blocks each having the logic circuit having a plurality of logic gates and a plurality of latch circuits connected to the logic gates;
3. The power switch is controlled to be turned on and off by a switch control signal, and is controlled to be turned on when the circuit block is in a use state and turned off when the circuit block is in an unused state. Semiconductor integrated circuit. 10. The semiconductor integrated circuit according to claim 9, further comprising means for allowing the power switch to be always turned on regardless of the switch control signal. When the logic circuit shifts from the use state to the unused state, the logic circuit holds the internal state of the logic circuit and turns off the power switch, and the logic circuit is changed from the unused state to the use state. 11. When shifting to (1), prior to using the logic circuit, the power switch is turned on and the internal state held in the dynamic latch circuit is written back to the logic circuit. Semiconductor integrated circuit. The semiconductor integrated circuit according to claim 9, wherein the semiconductor integrated circuit includes a processor, and the power switch control signal is generated in synchronization with a task switching of the processor.

Images