KR101088584B1 - 다층 배선 기판 및 그 제조 방법 - Google Patents
다층 배선 기판 및 그 제조 방법 Download PDFInfo
- Publication number
- KR101088584B1 KR101088584B1 KR1020077012697A KR20077012697A KR101088584B1 KR 101088584 B1 KR101088584 B1 KR 101088584B1 KR 1020077012697 A KR1020077012697 A KR 1020077012697A KR 20077012697 A KR20077012697 A KR 20077012697A KR 101088584 B1 KR101088584 B1 KR 101088584B1
- Authority
- KR
- South Korea
- Prior art keywords
- insulating film
- conductive material
- layer
- hole
- wiring board
- Prior art date
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 44
- 238000000034 method Methods 0.000 title claims description 37
- 239000004020 conductor Substances 0.000 claims abstract description 220
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- 238000009792 diffusion process Methods 0.000 claims abstract description 123
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 52
- 229910052802 copper Inorganic materials 0.000 claims description 52
- 239000010949 copper Substances 0.000 claims description 52
- 230000004888 barrier function Effects 0.000 claims description 47
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 38
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 36
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- 230000015572 biosynthetic process Effects 0.000 claims description 14
- 238000001312 dry etching Methods 0.000 claims description 14
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical group [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 13
- 230000003647 oxidation Effects 0.000 claims description 13
- 238000007254 oxidation reaction Methods 0.000 claims description 13
- 239000000377 silicon dioxide Substances 0.000 claims description 13
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- 238000005229 chemical vapour deposition Methods 0.000 claims description 9
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- 239000010953 base metal Substances 0.000 description 26
- 238000007747 plating Methods 0.000 description 24
- 239000000463 material Substances 0.000 description 17
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 14
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 12
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 10
- 239000010936 titanium Substances 0.000 description 10
- 229910052719 titanium Inorganic materials 0.000 description 10
- 229920005989 resin Polymers 0.000 description 9
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- 229910052759 nickel Inorganic materials 0.000 description 7
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- 230000000052 comparative effect Effects 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 229910052709 silver Inorganic materials 0.000 description 6
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- 229910052581 Si3N4 Inorganic materials 0.000 description 5
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- 229910052751 metal Inorganic materials 0.000 description 5
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- LCPVQAHEFVXVKT-UHFFFAOYSA-N 2-(2,4-difluorophenoxy)pyridin-3-amine Chemical compound NC1=CC=CN=C1OC1=CC=C(F)C=C1F LCPVQAHEFVXVKT-UHFFFAOYSA-N 0.000 description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 4
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- NIHNNTQXNPWCJQ-UHFFFAOYSA-N fluorene Chemical compound C1=CC=C2CC3=CC=CC=C3C2=C1 NIHNNTQXNPWCJQ-UHFFFAOYSA-N 0.000 description 4
- CHQMHPLRPQMAMX-UHFFFAOYSA-L sodium persulfate Substances [Na+].[Na+].[O-]S(=O)(=O)OOS([O-])(=O)=O CHQMHPLRPQMAMX-UHFFFAOYSA-L 0.000 description 4
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 3
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- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 229910000365 copper sulfate Inorganic materials 0.000 description 2
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
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- 239000011521 glass Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
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- 239000002356 single layer Substances 0.000 description 2
- -1 Chlorine ions Chemical class 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- YYRMJZQKEFZXMX-UHFFFAOYSA-N calcium;phosphoric acid Chemical compound [Ca+2].OP(O)(O)=O.OP(O)(O)=O YYRMJZQKEFZXMX-UHFFFAOYSA-N 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 150000001844 chromium Chemical class 0.000 description 1
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- 239000007789 gas Substances 0.000 description 1
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 1
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 150000002484 inorganic compounds Chemical class 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 229920003986 novolac Polymers 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
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- 229910000679 solder Inorganic materials 0.000 description 1
- 239000002426 superphosphate Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4076—Through-connections; Vertical interconnect access [VIA] connections by thin-film techniques
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/02—Pretreatment of the material to be coated
- C23C16/0227—Pretreatment of the material to be coated by cleaning or etching
- C23C16/0245—Pretreatment of the material to be coated by cleaning or etching by etching with a plasma
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/06—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
- C23C16/18—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metallo-organic compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0041—Etching of the substrate by chemical or physical means by plasma etching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0073—Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces
- H05K3/0079—Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces characterised by the method of application or removal of the mask
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/44—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits
- H05K3/445—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits having insulated holes or insulated via connections through the metal core
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
- H05K3/4605—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated made from inorganic insulating material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4679—Aligning added circuit layers or via connections relative to previous circuit layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09563—Metal filled via
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/096—Vertically aligned vias, holes or stacked vias
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/09—Treatments involving charged particles
- H05K2203/095—Plasma, e.g. for treating a substrate to improve adhesion with a conductor or for cleaning holes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- General Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Ceramic Engineering (AREA)
- Inorganic Chemistry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
코어 기판 다층 배선 기판 |
양품 판정 | 접속 시험 |
실시예 1 | ○ | 접속 이상 없음 |
실시예 2 | ○ | 접속 이상 없음 |
실시예 3 | ○ | 접속 이상 없음 |
실시예 4 | ○ | 접속 이상 없음 |
실시예 5 | ○ | 접속 이상 없음 |
실시예 6 | ○ | 접속 이상 없음 |
실시예 7 | ○ | 접속 이상 없음 |
실시예 8 | ○ | 접속 이상 없음 |
실시예 9 | ○ | 접속 이상 없음 |
비교예 1 | × | 접속 이상 발생 |
비교예 2 | × | 접속 이상 발생 |
Claims (23)
- 코어 기판 상에 전기 절연층을 통해 2층 이상의 배선을 갖는 다층 배선 기판에 있어서,코어 기판은 실리콘 코어 기판이며, 도전성 물질이 충전되어 표리의 도통이 이루어진 복수의 관통 구멍을 구비하고,상기 관통 구멍은 개구 직경이 10∼100 ㎛의 범위 내이며,상기 관통 구멍 내벽면 상과, 상기 코어 기판의 표면 및 이면 중 적어도 한 면에는, 제1 절연막, 상기 코어 기판으로의 상기 도전성 물질의 확산을 방지하기 위한 도전성 물질 확산 방지층, 및 제2 절연막이 이 순서로 적층되어 있고,상기 제1 절연막은 상기 실리콘 코어 기판의 열산화에 의해 형성된 산화규소막이고, 상기 제2 절연막을 통해 도전성 물질이 상기 관통 구멍 내에 충전되어 있으며, 전기 절연층을 통해 코어 기판 상에 형성된 첫 번째 층의 배선은 비아를 통해 상기 관통 구멍 내의 상기 도전성 물질에 접속되어 있는 것인 다층 배선 기판.
- 제1항에 있어서, 상기 도전성 물질 확산 방지층은 질화티탄 박막인 것인 다층 배선 기판.
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- 제1항에 있어서, 상기 제2 절연막은 이산화규소막인 것인 다층 배선 기판.
- 코어 기판 상에 전기 절연층을 통해 2층 이상의 배선을 갖는 다층 배선 기판에 있어서,코어 기판은 실리콘 코어 기판이며, 도전성 물질이 충전되어 표리의 도통이 이루어진 복수의 관통 구멍을 구비하고,상기 관통 구멍은 개구 직경이 10∼100 ㎛의 범위 내이며,상기 관통 구멍 내벽면에 제1 절연막, 제2 절연막, 상기 코어 기판으로의 상기 도전성 물질의 확산을 방지하기 위한 도전성 물질 확산 방지층, 제3 절연막이 이 순서로 적층되어 있고,상기 제1 절연막은 상기 실리콘 코어 기판의 열산화에 의해 형성된 산화규소막이고, 상기 제2 절연막과 상기 제3 절연막의 성분은 동일하고, 상기 제3 절연막을 통해 도전성 물질이 상기 관통 구멍 내에 충전되어 있으며, 전기 절연층을 통해 코어 기판 상에 형성된 첫 번째 층의 배선은, 비아를 통해 상기 관통 구멍 내의 상기 도전성 물질에 접속되어 있는 것인 다층 배선 기판.
- 제1항에 있어서, 상기 도전성 물질은 전해 도금에 의해 관통 구멍 내에 형성된 구리인 것인 다층 배선 기판.
- 제1항에 있어서, 상기 도전성 물질은 관통 구멍 내에 충전된 도전성 페이스트인 것인 다층 배선 기판.
- 제1항에 있어서, 상기 관통 구멍의 개구 직경은 10∼70 ㎛의 범위 내인 것인 다층 배선 기판.
- 제1항에 있어서, 상기 코어 기판의 두께는 50∼725 ㎛의 범위 내인 것인 다층 배선 기판.
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- 코어 기판 상에 전기 절연층을 통해 2층 이상의 배선을 갖는 다층 배선 기판의 제조 방법에 있어서,코어 기판용의 실리콘 코어재의 한쪽의 면으로부터, 플라즈마를 이용한 드라이 에칭에 의해 개구 직경이 10∼100 ㎛의 범위 내에 있는 미세 구멍을 소정의 깊이까지 형성하는 공정과,상기 미세 구멍의 내벽면과, 상기 실리콘 코어재의 표면 및 이면 중 적어도 한 면에, 도전성 물질 확산 방지층이 절연막으로 피복되도록 절연막 및 도전성 물질 확산 방지층을 형성하며, 그 후, 적어도 미세 구멍의 내벽면에 위치하는 절연막 상에 기초 도전층을 형성하는 공정과,상기 미세 구멍 내를 제외한 상기 실리콘 코어재 상에 원하는 레지스트 막을 형성하며, 상기 기초 도전층을 급전층으로 하여 상기 미세 구멍 내에 전해 도금에 의해 도전성 물질을 충전하는 공정과,상기 레지스트 막을 제거하며, 상기 실리콘 코어재의 다른쪽의 면을 연마하여 상기 미세 구멍을 노출시킴으로써 관통 구멍을 형성하고, 상기 도전성 물질에 의해 관통 구멍을 통한 표리의 도통이 이루어진 실리콘 코어 기판으로 하는 공정과,상기 실리콘 코어 기판 상에, 관통 구멍 내에 충전된 도전성 물질에 접속하도록 비아를 형성하는 동시에, 전기 절연층을 통한 첫 번째 층의 배선을 형성하는 공정을 포함하고,상기 절연막 및 상기 도전성 물질 확산 방지층을 형성하는 공정은, 제1 절연막, 도전성 물질 확산 방지층, 제2 절연막의 순서로 적층하는 방법과, 제1 절연막, 제2 절연막, 도전성 물질 확산 방지층, 제3 절연막의 순서로 적층하는 방법 중 어느 하나를 사용하여 절연막 및 도전성 물질 확산 방지층을 형성하고, 상기 제1 절연막의 형성은, 상기 실리콘 코어 기판의 열산화를 이용하여 행하는 것인 다층 배선 기판의 제조 방법.
- 제13항에 있어서, 상기 기초 도전층의 형성을 MO-CVD법에 의해 행하는 것인 다층 배선 기판의 제조 방법.
- 코어 기판 상에 전기 절연층을 통해 2층 이상의 배선을 갖는 다층 배선 기판의 제조 방법에 있어서,코어 기판용의 실리콘 코어재의 한쪽의 면으로부터, 플라즈마를 이용한 드라이 에칭에 의해 개구 직경이 10∼100 ㎛의 범위 내에 있는 미세 구멍을 소정의 깊이까지 형성하는 공정과,상기 실리콘 코어재의 다른쪽의 면을 연마하여 상기 미세 구멍을 노출시켜 관통 구멍을 형성하는 공정과,상기 관통 구멍의 내벽면과, 상기 실리콘 코어재의 표면 및 이면 중 적어도 한 면에, 도전성 물질 확산 방지층이 절연막으로 피복되도록 절연막 및 도전성 물질 확산 방지층을 형성하는 공정과,상기 관통 구멍 내에 도전성 물질을 충전하여 표리의 도통이 이루어진 실리콘 코어 기판으로 하는 공정과,상기 실리콘 코어 기판 상에, 관통 구멍 내에 충전된 도전성 물질에 접속하도록 비아를 형성하는 동시에, 전기 절연층을 통한 첫 번째 층의 배선을 형성하는 공정을 포함하고,상기 절연막 및 상기 도전성 물질 확산 방지층을 형성하는 공정은, 제1 절연막, 도전성 물질 확산 방지층, 제2 절연막의 순서로 적층하는 방법과, 제1 절연막, 제2 절연막, 도전성 물질 확산 방지층, 제3 절연막의 순서로 적층하는 방법 중 어느 하나를 사용하여 절연막 및 도전성 물질 확산 방지층을 형성하고, 상기 제1 절연막의 형성은, 상기 실리콘 코어 기판의 열산화를 이용하여 행하는 것인 다층 배선 기판의 제조 방법.
- 제15항에 있어서, 상기 절연막 및 상기 도전성 물질 확산 방지층을 형성하는 공정에서는, 관통 구멍의 내벽면을 포함하는 실리콘 코어재 표면에, 도전성 물질 확산 방지층이 절연막으로 피복되도록 절연막 및 도전성 물질 확산 방지층을 형성한 후에, 적어도 관통 구멍의 내벽면에 위치하는 절연막 상에 기초 도전층을 형성하며,관통 구멍 내에 도전성 물질을 충전하는 공정에서는, 상기 관통 구멍 내를 제외하는 상기 실리콘 코어재 상에 원하는 레지스트 막을 형성하고, 전해 도금에 의해 도전성 물질을 충전하는 것인 다층 배선 기판의 제조 방법.
- 제16항에 있어서, 상기 기초 도전층의 형성을 MO-CVD법에 의해 행하는 것인 다층 배선 기판의 제조 방법.
- 코어 기판 상에 전기 절연층을 통해 2층 이상의 배선을 갖는 다층 배선 기판의 제조 방법에 있어서,코어 기판용의 실리콘 코어재의 한쪽의 면으로부터, 플라즈마를 이용한 드라이 에칭에 의해 개구 직경이 10∼100 ㎛의 범위 내에 있는 미세 구멍을 소정의 깊이까지 형성하는 공정과,상기 실리콘 코어재의 다른쪽의 면을 연마하여 상기 미세 구멍을 노출시켜 관통 구멍을 형성하는 공정과,상기 실리콘 코어재의 양면과 상기 관통 구멍의 내벽면에 도전성 물질 확산 방지층이 절연막으로 피복되도록 절연막 및 도전성 물질 확산 방지층을 형성하며, 그 후, 상기 실리콘 코어재의 한쪽의 전면(全面)에 기초 도전층을 형성하는 공정과,상기 기초 도전층상과 상기 실리콘 코어재의 반대면의 상기 절연막 상에 원하는 레지스트 막을 형성하여, 상기 기초 도전층을 급전층으로 하여 전해 도금에 의해 상기 관통 구멍 내에 도전성 물질을 충전하여 표리의 도통이 이루어진 실리콘 코어 기판으로 하는 공정과,상기 실리콘 코어 기판 상에, 관통 구멍 내에 충전된 도전성 물질에 접속하도록 비아를 형성하는 동시에, 전기 절연층을 통한 첫 번째 층의 배선을 형성하는 공정을 포함하고,상기 절연막 및 상기 도전성 물질 확산 방지층을 형성하는 공정은, 제1 절연막, 도전성 물질 확산 방지층, 제2 절연막의 순서로 적층하는 방법과, 제1 절연막, 제2 절연막, 도전성 물질 확산 방지층, 제3 절연막의 순서로 적층하는 방법 중 어느 하나를 사용하여 절연막 및 도전성 물질 확산 방지층을 형성하고, 상기 제1 절연막의 형성은, 상기 실리콘 코어 기판의 열산화를 이용하여 행하는 것인 다층 배선 기판의 제조 방법.
- 제18항에 있어서, 상기 기초 도전층의 형성을 증착법, 스퍼터링법 중 어느 하나에 의해 행하는 것인 다층 배선 기판의 제조 방법.
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- 제13항 또는 제15항 또는 제18항 중 어느 한 항에 있어서, 상기 도전성 물질 확산 방지층의 형성을 MO-CVD법에 의해 행하는 것인 다층 배선 기판의 제조 방법.
- 제13항 또는 제15항 또는 제18항 중 어느 한 항에 있어서, 상기 미세 구멍을 그 개구 직경이 10∼70 ㎛의 범위 내가 되도록 형성하는 것인 다층 배선 기판의 제조 방법.
- 삭제
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KR20070085789A (ko) | 2007-08-27 |
JP4564342B2 (ja) | 2010-10-20 |
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CN101066005A (zh) | 2007-10-31 |
WO2006057174A1 (ja) | 2006-06-01 |
US7800002B2 (en) | 2010-09-21 |
US9659849B2 (en) | 2017-05-23 |
EP1830615A4 (en) | 2010-04-28 |
US10765011B2 (en) | 2020-09-01 |
US20190394886A1 (en) | 2019-12-26 |
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US20080083558A1 (en) | 2008-04-10 |
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