JP5330115B2 - 積層配線基板 - Google Patents
積層配線基板 Download PDFInfo
- Publication number
- JP5330115B2 JP5330115B2 JP2009144038A JP2009144038A JP5330115B2 JP 5330115 B2 JP5330115 B2 JP 5330115B2 JP 2009144038 A JP2009144038 A JP 2009144038A JP 2009144038 A JP2009144038 A JP 2009144038A JP 5330115 B2 JP5330115 B2 JP 5330115B2
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- silicon substrate
- resistance silicon
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- passage portion
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- 239000000758 substrate Substances 0.000 claims description 156
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 149
- 229910052710 silicon Inorganic materials 0.000 claims description 149
- 239000010703 silicon Substances 0.000 claims description 149
- 230000000149 penetrating effect Effects 0.000 claims description 6
- 230000003287 optical effect Effects 0.000 description 13
- 239000004065 semiconductor Substances 0.000 description 11
- 238000000034 method Methods 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 238000000708 deep reactive-ion etching Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000005304 joining Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 239000012670 alkaline solution Substances 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000012777 electrically insulating material Substances 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/147—Semiconductor insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49872—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials the conductive materials containing semiconductor material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Micromachines (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
Description
[第1の実施形態]
[第2の実施形態]
Claims (7)
- 厚さ分の深さを有する環状溝によって包囲された電気通路部を含む低抵抗シリコン基板と、
前記低抵抗シリコン基板の一方側の主面に積層され、厚さ方向に貫通する第1の開口が前記電気通路部に対応するように形成された第1の絶縁層と、
前記第1の絶縁層の一方側の主面に積層され、厚さ分の深さを有する第1の凹部が前記第1の開口に対応するように形成された第1の高抵抗シリコン基板と、を備え、
前記低抵抗シリコン基板は、所定の比抵抗を有し、前記第1の高抵抗シリコン基板は、前記所定の比抵抗よりも高い比抵抗を有し、
前記第1の高抵抗シリコン基板の一方側の主面、及び前記第1の凹部の内面には、第1の絶縁膜を介して第1の配線膜が設けられており、前記第1の配線膜は、前記第1の開口を介して前記電気通路部と電気的に接続されていることを特徴とする積層配線基板。 - 前記第1の凹部は、前記第1の高抵抗シリコン基板の厚さ方向から見た場合に、前記第1の凹部の他方側の端部が前記電気通路部の一方側の端面に含まれるように形成されていることを特徴とする請求項1記載の積層配線基板。
- 前記第1の凹部は、前記第1の高抵抗シリコン基板の他方側の主面から一方側の主面に向かって末広がりとなるように形成されていることを特徴とする請求項1又は2記載の積層配線基板。
- 前記第1の凹部は、前記第1の高抵抗シリコン基板の厚さ方向から見た場合に、前記第1の凹部の一方側の端部が前記電気通路部の一方側の端面に含まれるように形成されていることを特徴とする請求項3記載の積層配線基板。
- 前記環状溝内は、空隙となっていることを特徴とする請求項1〜4のいずれか一項記載の積層配線基板。
- 前記電気通路部の他方側の端面には、電極膜が設けられていることを特徴とする請求項1〜5のいずれか一項記載の積層配線基板。
- 前記低抵抗シリコン基板の他方側の主面に積層され、厚さ方向に貫通する第2の開口が前記電気通路部に対応するように形成された第2の絶縁層と、
前記第2の絶縁層の他方側の主面に積層され、厚さ分の深さを有する第2の凹部が前記第2の開口に対応するように形成された第2の高抵抗シリコン基板と、を更に備え、
前記第2の高抵抗シリコン基板は、前記所定の比抵抗よりも高い比抵抗を有し、
前記第2の高抵抗シリコン基板の他方側の主面、及び前記第2の凹部の内面には、第2の絶縁膜を介して第2の配線膜が設けられており、前記第2の配線膜は、前記第2の開口を介して前記電気通路部と電気的に接続されていることを特徴とする請求項1〜5のいずれか一項記載の積層配線基板。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009144038A JP5330115B2 (ja) | 2009-06-17 | 2009-06-17 | 積層配線基板 |
PCT/JP2010/059457 WO2010147000A1 (ja) | 2009-06-17 | 2010-06-03 | 積層配線基板 |
US13/378,110 US8847080B2 (en) | 2009-06-17 | 2010-06-03 | Laminated wiring board |
EP10789375.2A EP2445004B1 (en) | 2009-06-17 | 2010-06-03 | Laminated wiring board |
CN201080026802.XA CN102460687B (zh) | 2009-06-17 | 2010-06-03 | 层叠配线基板 |
TW099118602A TWI508240B (zh) | 2009-06-17 | 2010-06-08 | Laminated wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009144038A JP5330115B2 (ja) | 2009-06-17 | 2009-06-17 | 積層配線基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2011003633A JP2011003633A (ja) | 2011-01-06 |
JP5330115B2 true JP5330115B2 (ja) | 2013-10-30 |
Family
ID=43356321
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009144038A Expired - Fee Related JP5330115B2 (ja) | 2009-06-17 | 2009-06-17 | 積層配線基板 |
Country Status (6)
Country | Link |
---|---|
US (1) | US8847080B2 (ja) |
EP (1) | EP2445004B1 (ja) |
JP (1) | JP5330115B2 (ja) |
CN (1) | CN102460687B (ja) |
TW (1) | TWI508240B (ja) |
WO (1) | WO2010147000A1 (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2014087877A1 (ja) * | 2012-12-07 | 2014-06-12 | 信越化学工業株式会社 | インターポーザー用基板及びその製造方法 |
TWI548052B (zh) * | 2014-04-22 | 2016-09-01 | 矽品精密工業股份有限公司 | 半導體中介板及封裝結構 |
JP6693068B2 (ja) * | 2015-03-12 | 2020-05-13 | ソニー株式会社 | 固体撮像装置および製造方法、並びに電子機器 |
CN113169234A (zh) * | 2018-12-03 | 2021-07-23 | 艾尤纳公司 | 高密度光学互连组件 |
WO2020218223A1 (ja) * | 2019-04-25 | 2020-10-29 | 三洋電機株式会社 | 電圧検出線および電圧検出線モジュール |
CN110071047B (zh) * | 2019-04-28 | 2020-12-18 | 北京航天控制仪器研究所 | 一种微系统集成应用的硅基转接板制作方法 |
EP3855483A1 (en) * | 2020-01-21 | 2021-07-28 | Murata Manufacturing Co., Ltd. | Through-interposer connections using blind vias |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6221769B1 (en) * | 1999-03-05 | 2001-04-24 | International Business Machines Corporation | Method for integrated circuit power and electrical connections via through-wafer interconnects |
US20030086248A1 (en) * | 2000-05-12 | 2003-05-08 | Naohiro Mashino | Interposer for semiconductor, method for manufacturing same, and semiconductor device using same |
JP3530149B2 (ja) * | 2001-05-21 | 2004-05-24 | 新光電気工業株式会社 | 配線基板の製造方法及び半導体装置 |
EP1419526A2 (en) * | 2001-08-24 | 2004-05-19 | MCNC Research and Development Institute | Through-via vertical interconnects, through-via heat sinks and associated fabrication methods |
US6818464B2 (en) * | 2001-10-17 | 2004-11-16 | Hymite A/S | Double-sided etching technique for providing a semiconductor structure with through-holes, and a feed-through metalization process for sealing the through-holes |
US7030481B2 (en) * | 2002-12-09 | 2006-04-18 | Internation Business Machines Corporation | High density chip carrier with integrated passive devices |
SE526366C3 (sv) * | 2003-03-21 | 2005-10-26 | Silex Microsystems Ab | Elektriska anslutningar i substrat |
JP2005136266A (ja) | 2003-10-31 | 2005-05-26 | Matsushita Electric Ind Co Ltd | セラミック多層配線基板およびセラミック多層配線基板の製造方法ならびに半導体装置 |
US7276787B2 (en) * | 2003-12-05 | 2007-10-02 | International Business Machines Corporation | Silicon chip carrier with conductive through-vias and method for fabricating same |
JP4564342B2 (ja) * | 2004-11-24 | 2010-10-20 | 大日本印刷株式会社 | 多層配線基板およびその製造方法 |
CA2607885A1 (en) | 2005-05-18 | 2006-11-23 | Kolo Technologies, Inc. | Through-wafer interconnection |
JP5025922B2 (ja) * | 2005-06-30 | 2012-09-12 | オンセミコンダクター・トレーディング・リミテッド | 回路基板、回路基板の製造方法および半導体装置 |
US8633572B2 (en) * | 2006-03-27 | 2014-01-21 | Koninklijke Philips N.V. | Low ohmic through substrate interconnection for semiconductor carriers |
JP5179046B2 (ja) * | 2006-11-22 | 2013-04-10 | 新光電気工業株式会社 | 電子部品および電子部品の製造方法 |
JP4970979B2 (ja) * | 2007-02-20 | 2012-07-11 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2009054824A (ja) * | 2007-08-28 | 2009-03-12 | Panasonic Electric Works Co Ltd | 貫通配線付基板の製造方法 |
-
2009
- 2009-06-17 JP JP2009144038A patent/JP5330115B2/ja not_active Expired - Fee Related
-
2010
- 2010-06-03 US US13/378,110 patent/US8847080B2/en not_active Expired - Fee Related
- 2010-06-03 CN CN201080026802.XA patent/CN102460687B/zh not_active Expired - Fee Related
- 2010-06-03 WO PCT/JP2010/059457 patent/WO2010147000A1/ja active Application Filing
- 2010-06-03 EP EP10789375.2A patent/EP2445004B1/en not_active Not-in-force
- 2010-06-08 TW TW099118602A patent/TWI508240B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP2445004A1 (en) | 2012-04-25 |
CN102460687B (zh) | 2016-01-20 |
CN102460687A (zh) | 2012-05-16 |
EP2445004B1 (en) | 2019-05-01 |
EP2445004A4 (en) | 2018-02-14 |
WO2010147000A1 (ja) | 2010-12-23 |
JP2011003633A (ja) | 2011-01-06 |
TWI508240B (zh) | 2015-11-11 |
US8847080B2 (en) | 2014-09-30 |
TW201110289A (en) | 2011-03-16 |
US20120132460A1 (en) | 2012-05-31 |
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