KR100546331B1 - 스택 뱅크들 마다 독립적으로 동작하는 멀티 포트 메모리장치 - Google Patents

스택 뱅크들 마다 독립적으로 동작하는 멀티 포트 메모리장치 Download PDF

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KR100546331B1
KR100546331B1 KR1020030035606A KR20030035606A KR100546331B1 KR 100546331 B1 KR100546331 B1 KR 100546331B1 KR 1020030035606 A KR1020030035606 A KR 1020030035606A KR 20030035606 A KR20030035606 A KR 20030035606A KR 100546331 B1 KR100546331 B1 KR 100546331B1
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data
write
read
data line
bank
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KR20040105007A (ko
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이승훈
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삼성전자주식회사
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Priority to KR1020030035606A priority Critical patent/KR100546331B1/ko
Priority to DE102004027882A priority patent/DE102004027882A1/de
Priority to US10/858,659 priority patent/US7120081B2/en
Priority to TW093115983A priority patent/TWI256647B/zh
Priority to JP2004166015A priority patent/JP2004362760A/ja
Publication of KR20040105007A publication Critical patent/KR20040105007A/ko
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
  • Memory System (AREA)
KR1020030035606A 2003-06-03 2003-06-03 스택 뱅크들 마다 독립적으로 동작하는 멀티 포트 메모리장치 Expired - Fee Related KR100546331B1 (ko)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1020030035606A KR100546331B1 (ko) 2003-06-03 2003-06-03 스택 뱅크들 마다 독립적으로 동작하는 멀티 포트 메모리장치
DE102004027882A DE102004027882A1 (de) 2003-06-03 2004-05-28 Multiportspeicherbaustein mit gestapelten Bänken
US10/858,659 US7120081B2 (en) 2003-06-03 2004-06-01 Multi-port memory device with stacked banks
TW093115983A TWI256647B (en) 2003-06-03 2004-06-03 Multi-port memory device with stacked banks
JP2004166015A JP2004362760A (ja) 2003-06-03 2004-06-03 マルチポートメモリ装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020030035606A KR100546331B1 (ko) 2003-06-03 2003-06-03 스택 뱅크들 마다 독립적으로 동작하는 멀티 포트 메모리장치

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KR20040105007A KR20040105007A (ko) 2004-12-14
KR100546331B1 true KR100546331B1 (ko) 2006-01-26

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KR1020030035606A Expired - Fee Related KR100546331B1 (ko) 2003-06-03 2003-06-03 스택 뱅크들 마다 독립적으로 동작하는 멀티 포트 메모리장치

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US (1) US7120081B2 (https=)
JP (1) JP2004362760A (https=)
KR (1) KR100546331B1 (https=)
DE (1) DE102004027882A1 (https=)
TW (1) TWI256647B (https=)

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US20070150667A1 (en) * 2005-12-23 2007-06-28 Intel Corporation Multiported memory with ports mapped to bank sets
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KR100781129B1 (ko) * 2006-06-05 2007-11-30 엠텍비젼 주식회사 다중 포트 메모리 장치 및 그 데이터의 출력 방법
KR100790446B1 (ko) 2006-06-30 2008-01-02 주식회사 하이닉스반도체 스택뱅크 구조를 갖는 반도체 메모리 장치
KR100846386B1 (ko) * 2006-09-21 2008-07-15 주식회사 하이닉스반도체 멀티포트 메모리 장치
KR100837811B1 (ko) 2006-11-15 2008-06-13 주식회사 하이닉스반도체 데이터 변환 회로 및 이를 이용한 반도체 메모리 장치
KR100871083B1 (ko) * 2007-02-27 2008-11-28 삼성전자주식회사 입출력 센스앰프를 구비하는 반도체 메모리 장치의레이아웃 구조
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JP7655853B2 (ja) 2019-02-11 2025-04-02 サンライズ メモリー コーポレイション 垂直型薄膜トランジスタ、及び、垂直型薄膜トランジスタの、３次元メモリアレイのためのビット線コネクタとしての応用メモリ回路方法
JP2020166346A (ja) * 2019-03-28 2020-10-08 ラピスセミコンダクタ株式会社 半導体記憶装置
CN114026676B (zh) 2019-07-09 2023-05-26 日升存储公司 水平反或型存储器串的三维阵列制程
US11917821B2 (en) 2019-07-09 2024-02-27 Sunrise Memory Corporation Process for a 3-dimensional array of horizontal nor-type memory strings
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US11515309B2 (en) 2019-12-19 2022-11-29 Sunrise Memory Corporation Process for preparing a channel region of a thin-film transistor in a 3-dimensional thin-film transistor array
TWI767512B (zh) 2020-01-22 2022-06-11 美商森恩萊斯記憶體公司 薄膜儲存電晶體中冷電子抹除
US12550382B2 (en) 2020-01-22 2026-02-10 Sunrise Memory Corporation Thin-film storage transistor with ferroelectric storage layer
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US11507301B2 (en) 2020-02-24 2022-11-22 Sunrise Memory Corporation Memory module implementing memory centric architecture
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Also Published As

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US7120081B2 (en) 2006-10-10
JP2004362760A (ja) 2004-12-24
TW200519963A (en) 2005-06-16
US20040246807A1 (en) 2004-12-09
DE102004027882A1 (de) 2005-01-13
TWI256647B (en) 2006-06-11
KR20040105007A (ko) 2004-12-14

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